JP2943527B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring layer.

[0002]

2. Description of the Related Art FIG. 3 is a plan view showing an example of a conventional multilayer wiring structure of a semiconductor device, and FIG. 4 is a sectional view taken along line AA 'of FIG.

[0005] A silicon oxide film 2 is formed on a silicon substrate 1, and a first metal wiring layer 3 is patterned on the silicon oxide film 2. Further, on the first metal wiring layer 3 and the silicon oxide film 2, an interlayer insulating film 4 is provided by applying a film such as SOG and flattening. A connection hole 6 is provided in the interlayer insulating film 4.
Is completely buried with a buried metal film 7 such as tungsten formed by a chemical vapor deposition method. On the interlayer insulating film 4 and the buried metal film 7, a second metal wiring layer 5 is patterned and connected.

[0004]

In this conventional semiconductor device, an SOG film is used for part or all of the interlayer insulating film 4 in order to sufficiently planarize the interlayer insulating film. However, the SOG film has a problem that the laminated film thickness varies depending on the wiring width of the wiring layer below the SOG film.

In the prior art shown in FIGS. 3 and 4, the wiring width W1 of the right first metal wiring layer 3 is larger than the wiring width W2 of the two left first metal wiring layers 3. In the right portion where the wiring width is large, the thickness of the interlayer insulating film 4 is increased,
The depth of the connection hole 6 formed in the interlayer insulating film is increased. As a result, the buried metal 7 is not easily deposited normally, and a cavity 8 is formed in the center of the connection hole, which has the disadvantage of deteriorating the yield and reliability of the semiconductor device.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
A first wiring width and a second wiring smaller than the first wiring width
A flattened insulating film is provided on the lower wiring layer having a width , and a first insulating film reaching the first wiring width portion of the lower wiring layer is provided .
1 connection hole and the second wiring width portion of the lower wiring layer
Second connection holes are provided in the insulating film, respectively.
And connecting the lower layer wiring through the first and second connection holes.
An upper layer wiring at each of the first and second wiring width portions of the layer
In the semiconductor device with a multilayer wiring structure layers are connected, before
The area of the upper part of the first connection hole is changed to the upper part of the second connection hole.
Larger than the area of the first connection hole and the first connection hole.
An angle (a sharp angle) between the side wall surface of the substrate and the second connection.
It is characterized in that it is smaller than an angle (a sharp angle) formed between the hole and the side wall surface . Here, when the width of the wiring layer becomes 10 μm or more, the thickness of the connection hole is made two or more by using an insulating film whose film thickness is suddenly increased, and the area above the connection hole is reduced by the wiring under the connection hole. When the width of the layer is 10 μm or more, it is preferable that the width of the wiring layer below the connection hole is 1.5 to 2.5 times larger than that of less than 10 μm.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention. As in the conventional example, a silicon oxide film 2 having a thickness of 800 nm (nanometer) is formed on a silicon substrate 1.
Is formed, and the first metal wiring layer 3 is further formed to a thickness of about 500
It is formed with an aluminum film having a thickness of nm and is patterned. In the first metal wiring layer 3, the first metal wiring layer 3 on the right side in the figure has a large wiring width W1, and the two first metal wiring layers 3 on the left side are smaller than those on the right side. It has a width W2. Next, an interlayer insulating film 4 is formed by applying an SOG film.

However, in this case, the thickness of the interlayer insulating film on the first metal wiring layer depends on the width of the first metal wiring layer as shown in the graph of FIG. In particular, when the width of the first metal wiring layer is 10 μm or more, the film thickness suddenly increases.

Therefore, when the wiring width W2 of the two metal wiring layers 3 on the left side in the figure below the connection hole is less than 10 μm, the connection hole 6 formed in the interlayer insulating film 4 of FIG. 6
When the wiring width W1 of the metal wiring layer 3 on the right side in the figure is 10 μm or more, the connection The size of the upper portion of the hole 6 is 1.0 μm, which is 1.5 times as large as the area of the left connection hole. The connection hole 6 has an angle between 80 ° and 87 ° between the substrate surface and the connection hole side wall surface so that the buried metal film 7 is easily deposited.
Is formed to have a forward taper.

The buried metal film 7 is formed so as to fill the connection hole by laminating about 800 nm and etching back. In the connection hole having a large upper area, a hole is formed in the center, but the connection hole has a forward taper, so that the center is concavely formed. Finally, a second metal wiring layer 5 is formed with a film thickness of 1.0 μm and patterned. The concave dent of the buried metal in the connection hole having a large upper area is completely buried by the second metal wiring layer 5.

The taper of the connection hole can be easily formed by cooling the dry-etched electrode plate using a magnetic field. By optimizing the electrode plate temperature, the taper angle can be reduced according to the upper area of the connection hole. For example, if the taper angle is set to 87 ° when the upper area is 0.8 μm, and the taper angle is set to 74 ° when the upper area is 1.0 μm, the connection width under the connection hole is 10 μm or more. The size of the top of the hole is 1.0 μm
The connection hole of the opening can be more favorably buried with the buried metal film.

[0013]

As described above, according to the present invention, when a connection hole is formed in an interlayer film planarized with an SOG film or the like, the connection hole formed on a metal wiring layer having a wiring width of 10 μm or more is formed by a conventional wiring. By making the area of the upper connection hole 1.5 to 2.5 times larger than that of the layer (the wiring width is less than 10 μm), it can be completely buried with the buried metal film and the second metal wiring layer. When the area of the upper portion of the connection hole was changed according to the wiring width below the connection hole, the non-defective product rate of the connection hole could be improved as compared with the case where the size of the connection hole was completely constant.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a first metal wiring layer width and an interlayer insulating film thickness on the first metal wiring layer.

FIG. 3 is a plan view showing a conventional semiconductor device.

FIG. 4 is a sectional view taken along the line AA ′ in FIG. 3;

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 silicon oxide film 3 first metal wiring layer 4 interlayer insulating film 5 second metal wiring layer 6 connection hole 7 buried metal film

Claims (1)

(57) [Claims] A first wiring width and a width of the first wiring;
A flattened insulating film is provided on a lower wiring layer having a small second wiring width, and a portion of the lower wiring layer having the first wiring width is provided.
Minute of the first connection hole and the lower wiring layer.
Each of the second connection holes reaching the width of 2 wiring widths is
Provided on the rim and through the first and second connection holes
The first and second wiring widths of the lower wiring layer
In a semiconductor device having a multi-layer wiring structure in which upper wiring layers are connected to each other, an area of an upper portion of the first connection hole is set to be larger than that of the second connection hole.
Larger than the area of the portion, and the first connection with the substrate surface
The angle (acute angle) between the side wall surface of the hole and the substrate surface is defined by the second contact.
A semiconductor device characterized by being smaller than an angle (a sharp angle) formed by a side wall surface of a continuous hole .