JP2943511B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to an electrode wiring.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a large number of semiconductor chips are formed on a wafer, and the chips are formed into individual chips by dicing. Therefore, the chips are rectangular due to the dicing direction and other restrictions. is there. In a limited area on the semiconductor chip, elements such as transistors and capacitors and electrode wiring must be formed,
The area of the semiconductor chip must be used effectively.

In an IC memory with the highest degree of integration, memory cells occupy 80% of the semiconductor chip area. Circuit elements such as transistors and capacitors are formed on the outer periphery of the memory cell array, and furthermore, electrode wiring is provided outside. Are located.

By arranging as described above, the area inside the chip can be used effectively, but the electrode wiring is arranged on the outer periphery of the semiconductor chip along the outer shape of the semiconductor chip as shown in FIG. ing.

[0005]

In a conventional semiconductor device, as shown in FIG. 2, a metal film such as Al is used for the uppermost electrode wirings 3 and 4 on a silicon substrate 1 and silicon oxynitride (abbreviated as SiON). The structure is such that the film is covered with a cover film such as a film or the like and sealed with a mold resin 6.

As shown in Table 1, the silicon substrate 1, the Al film, the SiON film, and the mold resin have different coefficients of thermal expansion.

[0007]

[Table 1]

Therefore, when the semiconductor device is subjected to the temperature cycle shown in Table 2 at least 10 times, the following defects occur.

[0009]

[Table 2]

A mold resin having a large coefficient of thermal expansion repeatedly expands and contracts during such a temperature cycle test. However, since the silicon substrate has a small coefficient of thermal expansion, expansion and contraction are small. For this reason, the mold resin tends to move while repeating expansion and contraction, and C
_1, stress the portions of the C _2.

This stress increases in proportion to the distance from the chip center, and rapidly increases at a corner of the semiconductor chip within a radius of 200 μm as shown in FIG. This stress also increases in proportion to the width of the electrode wiring, and as shown in FIG. 4, the maximum stress increases as the width of the electrode wiring increases.

In the conventional semiconductor device shown in FIG. 2, the electrode wirings 3 are arranged within a radius of 200 μm of the corner of the semiconductor chip, and the width of the electrode wiring 3 is 30 to 50 μm. There is a problem that the electrode wirings 3 are concentrated and shifted, or cracks occur.

[0013]

According to the present invention, there is provided a semiconductor device comprising:
It has a plurality of conductive films of a predetermined width arranged in parallel at predetermined intervals and a connecting portion connecting adjacent conductive films.
An electrode wiring, the conductive film of the semiconductor chip code
Around the area within 200μm radius
It is that it is arranged .

Further, the width at the connection portion is set to 15 μm or less, and the radius at the corner of the semiconductor chip is set to 200 μm.
By disposing the conductive film so as to bypass the region within, the displacement and disconnection of the electrode wiring can be prevented.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip schematically showing an embodiment of the present invention. However, for convenience, the cover film,
The mold resin is not shown. The wide wiring 103 is divided into four to six Al films and arranged in parallel. The width of each Al film is 6 μm and the interval is 2 μm. In order to make all the divided Al films have the same potential, two adjacent Al films are connected at a certain interval at a linear portion along the side of the semiconductor chip, and the adjacent connecting portions A1 to A5 are at a constant interval. , Staggered. At this time, the total width of the Al film at the connection portion is 14 μm. In the place where the width of the electrode wiring changes, the number of divisions is changed so that the maximum width of the Al film is
The connection is made to be 15 μm or less.

The electrode wiring 104 is an Al film having a width of 15 μm, and is arranged along the outermost periphery of the semiconductor chip.

At the corner 107 of the semiconductor chip, the electrode wiring 104 is arranged in a region within a radius of 200 μm from the corner, but the electrode wiring 104 arranged at the outermost periphery of the semiconductor chip has a width of 15 μm or less. It has been confirmed that cracks can be prevented if present.

Further, since the stress is concentrated in a region within a radius of 200 μm from the corner portion of the semiconductor chip, the electrode wiring 103 is arranged so as to bypass the region of a radius of 200 μm from the corner portion. It is preferable to arrange patterns that are not directly related to the characteristics of the semiconductor device, such as check patterns and product names.

As the conductive film, in addition to the Al film, Al-
An Al-based alloy film such as a Si film can be used.

[0021]

As described above, according to the present invention, a plurality of conductive films are arranged in parallel at regular intervals, two adjacent conductive films are arranged in parallel at regular intervals, and two adjacent conductive films are arranged. Are connected at regular intervals to form electrode wiring , and
Area within a radius of 200 μm from the corner of the conductor chip
Since so as to place the conductive film, bypassing, the conductive film
Applied stress with disperse the radius from the co Na 2
And to avoid the stress concentrated on the region within 00μm, the occurrence of the wiring displacement and cracks can be prevent.

[Brief description of the drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a plan view (FIG. 2A) and an enlarged sectional view (FIG. 2B) showing a conventional example.

FIG. 3 is a graph showing a relationship between a position of an electrode wiring and a maximum stress value.

FIG. 4 is a graph showing a relationship between a width of an electrode wiring and a maximum stress value.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2,102 Interlayer insulating film 3,103 Electrode wiring 4,104 Electrode wiring 5 Cover film 6 Mold resin A1-A5 Connection part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] A plurality of conductive films according to claim 1] arranged a predetermined width in parallel with a predetermined distance, a semiconductor device including an electrode wiring which have a connecting portion for connecting the conductive film between the adjacent
Therefore, the conductive film is partially half
A semiconductor device, which is arranged so as to bypass a region having a diameter of 200 µm or less . 2. The semiconductor device according to claim 1, wherein the width of the connection portion does not exceed 15 μm.