JPH1079471A - Semiconductor device, its manufacture and flexible card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase yield by dividing at least one of the layers forming a device on a semiconductor substrate having a thickness within a specific range and connecting the divided devices in parallel. SOLUTION: A cell structure is formed by dividing Ti-Pt lower electrode layer 43 and a BST high dielectric layer 44, and a Ti-Pt-Au upper electrode layer 45, formed on an SiO2 layer 2 on an Si monocrystal substrate 1, into cells. An MIM-type structure is formed on the entire wafer surface, and then the upper electrode layer 45 is removed and divided by ion milling with a photoresist layer as a mask. Next, an SiO2 insulating film 46 is formed on the surface, and then conduction holes connecting the upper electrode layer 45 to the lower electrode layer 43 are formed, and wiring layers 47 and 48 are formed. The divided cells are connected in parallel to each other with the wiring layers 47 and 48, thus constructing a large capacity capacitor. The Si is grind-removed from the rear surface side of the Si monocrystal substrate 1, and the substrate is etched with a chemical etchant to have a thickness of 1-100μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for an IC card or a multi-chip module, a method for manufacturing the same, and a flexible card.

[0002]

2. Description of the Related Art Thin and lightweight high-performance electronic devices represented by IC cards are rapidly increasing in demand due to their convenience, and their application fields are expanding. There are two types of IC cards: a method of obtaining electric signals and power by a contact method and a method of obtaining a non-contact method.
There is a feature that is strong against static electricity. The structure of a conventional IC card is
"IC Card" is described on page 33 (edited by the Institute of Electronics, Information and Communication Engineers, issued by Ohmsha, 1st edition, issued on May 25, 1990). -87299 and JP-A-7-
No. 99267 discloses this.

FIG. 8 is a sectional structural view showing the structure of a main part of a conventional IC card. The LSI chip 81 and the capacitor chip 82 are connected by a wire 88.
It is fixed to resin films 83 and 87 and a core layer 85 constituting the entire C card by adhesive layers 84 and 86.

When the thickness of the LSI chip is large, it is strong against mechanical deformation, but is liable to bend. Therefore, a structure in which the LSI is not broken even if the card is bent or twisted has been studied. Japanese Patent Laid-Open No. 7-99267 discloses a structure in which an LSI having an extremely thin substrate is mounted on a neutral surface at the center in the thickness direction of the card. There are strong features. For this reason, it is considered that the future technology of IC cards will be mainly composed of a combination of this and a non-contact method of an electric signal or a power supply. This non-contact IC card is referred to as a flexible IC
The card is called F card for short. This requires a thin capacitor and a thin coil device in addition to a thin LSI. Chips such as LSIs and capacitors used for F-cards are required to be as thin as 100 μm or less, and large-capacity capacitors of about 30 nF are used for non-contact IC cards.

[0005]

Conventionally, the substrate of the LSI chip or the capacitor chip of the IC card which is usually used is thinner than the thickness of the IC card as shown in FIG.
A chip having a thickness of about 200 μm is used to maintain the strength of the chip. On the other hand, it is preferable to use a thin chip having a substrate thickness of 100 μm or less as an F card chip.

For example, if a capacitor is formed on a Si single crystal substrate using a BST (BaTiO ₃ and SrTiO ₃ mixed crystal) dielectric thin film having a relative dielectric constant of about 300, the thickness of the Si single crystal substrate Although the warp of the wafer is small in a structure of about 200 μm, when the wafer is processed to a substrate thickness of about 50 μm, the warp of the wafer becomes extremely large due to the film formation layer on the Si single crystal substrate.

Therefore, when the wafer on which the multilayer capacitor for an IC card is formed as described above is made thin, the wafer is liable to be broken during the manufacturing process or processing into a chip, resulting in a low chip manufacturing yield. . Further, when the obtained chip is mounted on an IC card, there is a problem that it is difficult to handle the chip due to a large warpage of the chip, cracks and a low assembly yield.

A first object of the present invention is suitable for mass production,
An object of the present invention is to provide a semiconductor device having a thin substrate, which is easy to handle and has a good assembly yield. A second object of the present invention is to provide a method of manufacturing a semiconductor device that can easily manufacture such a semiconductor device. A third object of the present invention is to provide a flexible card having such a semiconductor device.

[0009]

In order to achieve the first object, a semiconductor device according to the present invention has a thickness of 1 μm to 1 μm.
A semiconductor substrate in the range of 00 μm, and an element disposed on the semiconductor substrate, at least one of the film forming layers constituting the element is divided, and the divided elements are connected in parallel. It was done.

Preferably, the semiconductor substrate is a Si single crystal substrate. 1 μm Si single crystal substrate with few crystal defects
This is because it is tough even at a thickness of from 100 μm to 100 μm and does not crack unless it is extremely bent. For a tougher semiconductor substrate, the thickness is more preferably in the range of 10 μm to 100 μm.

In order to achieve the second object,
In the method for manufacturing a semiconductor device according to the present invention, an element including a plurality of film layers is formed on a semiconductor substrate, at least one of the film layers forming the element is divided, and the divided elements are arranged in parallel. At least a part of a wiring layer for connection to the semiconductor substrate is formed, and the back surface of the semiconductor substrate is polished to a thickness in a range of 1 μm to 100 μm.

In the polishing of the back surface of the semiconductor substrate, it is preferable to perform mechanical polishing and then to perform chemical polishing.

Further, in order to achieve the third object,
A flexible card according to the present invention includes any one of the above-described semiconductor devices and a flexible structural member having the semiconductor device disposed therein.

The fact that the warpage of the wafer is reduced when the element is divided as described above will be described with reference to FIGS. FIG. 3 shows a metal-insulator-metal type (MIM; Meta) structure in which an element has a dielectric thin film sandwiched between metals.
FIG. 2 is a cross-sectional configuration view of a main part when the capacitor is an (l-insulator-metal type) capacitor, and FIG. 2 is a plan view thereof. On the SiO ₂ layer 2 on the Si single crystal substrate 1, there is provided a capacitor section 21 in which a lower electrode layer 3, a high dielectric layer 4 of BST, and an upper electrode layer 5 are laminated. A scribe region 29 is provided at a position between the chips 20, and an effective area (Lx × Ly) of the capacitor unit 21 is about 2
× 2 mm ² . The capacitor unit 21 is divided into four in both the vertical and horizontal directions, and includes 16 cells 26. The size of one divided cell 26 is about 500 × 500 μm ² .
The width of the division is 5 μm. The stress of the film formation layer on the Si single crystal substrate is divided, and even when the substrate thickness (Tsn) is made extremely thin (Tst), the stress on the wafer is dispersed, and the warpage is suppressed to be small.

Preferred division criteria corresponding to the substrate thickness are shown below. In general, the amount of wafer warpage R is given by the following equation (1).
Described by the relationship R = K · Sf · Tf · D ² / Ts ² (1) where, Sf: stress of film formation, Tf: thickness of film formation, D: diameter of wafer Ts: thickness of substrate, K: constant number, It is.

When the substrate having the conventional structure (Tsn) is finished to a thin thickness (Tst), the amount of warpage R of the wafer is calculated by the relation of the equation (1), and the square of the wafer diameter and 1 / th of the thickness is obtained. It increases by the square. When the wafer diameter is constant,
The larger the area of the element size, the greater the warpage. For this reason, in order to reduce the warpage with a thin wafer, it is preferable to divide the element formed of the film forming layer constituting the device into small pieces to disperse the stress. In order to reduce the amount of warpage of a wafer having a thin thickness (Tst) to be equal to or less than the amount of warpage of the substrate thickness (Tsn) of the conventional structure, the element is divided into several cells, and one side of the cell is arranged vertically and horizontally. Is preferably in the range of 1 to 20 times the thickness of the semiconductor substrate. The shape of the divided cells is not limited to a quadrangle, but may be a polygon or an ellipse. The size at this time may be smaller than the above-described maximum size and larger than the minimum size. Even if the length of one side is less than one time the thickness of the semiconductor substrate, there is no problem in the amount of warpage, but since the structure becomes more complicated, it is preferably one time or more.

For example, when the effective area of the capacitor (substantially the same as the chip area) is 2 mm × 2 mm, if the thickness of the semiconductor substrate is 50 μm, one side is 50 μm to 1000 μm.
m.

The divided film layers need not necessarily be all layers formed on the Si single crystal substrate, but may be only layers having a large stress. For the thin LSI chip and thin capacitor chip for F card, the pattern layout is performed based on the above criteria.
Since the device can be manufactured under the same manufacturing conditions as the conventional device having a substrate thickness, the process can be shared and the cost can be reduced.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

<Embodiment 1> FIGS. 2 and 3 are a plan view and a sectional structural view of a chip 20 of an MIM type capacitor according to an embodiment of the present invention. An SiO ₂ layer 2 of about 500 nm is formed on a Si single crystal substrate 1.
The lower electrode layer 3 of Ti-Pt, the high dielectric layer 4 of BST, and the upper electrode layer 5 of Ti-Pt-Au are sequentially formed thereon. These film thicknesses are about 2 in this order.
00, 300, and 300 nm. There is a scribe area 29 between the chips, and the effective area (L
x × Ly) is about 2 × 2 mm ² .

The capacitor section 21 is divided into four cells both vertically and horizontally, and is composed of 16 cells 26. The size of one divided cell 26 is about 500 × 500 μm ² . A division width of 5 μm or less is sufficient, and has little effect on changes in chip area. The SiO ₂ layer 2 does not have to be divided as cells. The extraction electrodes and the bonding pad portion of the capacitor are omitted from the illustration in FIG.

FIG. 4 shows the details of one divided cell.
The method of division will be described. SiO ₂ on Si single crystal substrate 1
Ti-Pt lower electrode layer 43 formed on layer 2, BS
T high dielectric layer 44, Ti-Pt-Au upper electrode layer 4
5 is divided by the following method to form a cell structure. After the MIM type structure is formed on the entire surface of the wafer, the upper electrode layer 45 is removed by ion milling using the photoresist layer as a mask and divided. At this time, the scribe area 29 is also removed. Further, the high dielectric layer 44 and the lower electrode layer 43 are sequentially removed by the same method.

Next, a SiO ₂ insulating film 46 is formed on the surface, and conduction holes reaching the upper electrode layer 45 and the lower electrode layer 43 are processed to form wiring layers 47 and 48. The divided cells are connected in parallel by a wiring layer 47 for the lower electrode and a wiring layer 48 for the upper electrode, and a large-capacity capacitor as a whole is obtained. On the surface, a protective film 49 made of a SiN film and a SiO ₂ film is formed for the purpose of protecting the BST high dielectric layer 44 from the external environment. The protective film 49 may be an insulating material made of AlN or Al ₂ O ₃ . The divided film layer is BS
Since the stress of the high dielectric layer of T is large, only the high dielectric layer and the upper electrode may be used.

Subsequently, Si is ground and removed to about 180 μm from the back side of the Si single crystal substrate 1 having a thickness of about 500 μm,
Further, Si is dissolved by a chemical etching solution containing HF and HNO ₃ as main components, so that the substrate thickness is about 40 μm.
Damage caused in the Si single crystal by grinding can be completely removed by chemical etching of about 40 μm or more. As a result, an MIM type thin capacitor is manufactured on a Si single crystal substrate having a thickness of about 40 μm.

In the case of the conventional capacitor having an undivided integral area, the substrate thickness (Tsn) is about 200 μm and the amount of warpage Rn of the wafer is 20 μm. If this is made as thin as 40 μm of the substrate thickness (Tst), the warpage Rt of the wafer becomes a large value of about 500 μm, which is a problem in handling. In this embodiment, the same capacitance value as that of the related art
Wafer warpage Rn of substrate thickness (Tst) of 20 μm
In order not to exceed the value of m, the maximum cell size (Lx, Ly) in the chip having the conventional structure is preferably divided into 20 times or less and 1 or more times the thickness (40 μm) of the substrate in both the vertical and horizontal directions. . In the present embodiment, the cell is divided into four in both the vertical and horizontal directions (the number of divisions; n = 4), and the size (Lx / n, L
y / n) was about 500 × 500 μm ² . The size of the cell 26 is the size of the largest layer among the divided layers (the size of the lower electrode layer 43 in this embodiment). Thereafter, chips are cut out from the wafer, and mass-produced MIM thin capacitors having uniform characteristics can be produced.

When the chip obtained in this embodiment is mounted on an F card, since the amount of warpage of the chip is small, a chip having a capacitor of a conventional structure and having an integral area which is not divided and having a substrate thickness of 40 μm is mounted on the F card. The assembly yield has been greatly improved compared to mounting.

<Embodiment 2> FIG. 5 is a sectional view showing the structure of a cell according to another embodiment of the present invention. This is intended to simplify the manufacturing process by reducing the number of photomasks, and the division of the cells is the same as the purpose described in the first embodiment. The only difference from FIG. 4 is that the high dielectric layer 54 and the lower electrode layer 5 are formed by ion milling using one photoresist layer as a mask.
Forming 3 means that the lower electrode wiring layer 57 is mainly in contact with the side surface of the lower electrode layer 53 to conduct electricity.

<Embodiment 3> FIG. 6 is a sectional view showing the structure of a cell according to still another embodiment of the present invention. This is for the purpose of simplifying the manufacturing process by reducing the number of upper electrode layers and photomasks, and the cell division is the same as the purpose described in the first embodiment. 5 except that the upper electrode layer is not formed on the high dielectric layer 64, and the wiring layer 68 directly in contact with the high dielectric layer 64 also serves as the upper electrode. Configuration.

<Embodiment 4> FIG. 7 is a sectional view showing the structure of a cell according to still another embodiment of the present invention. This is a further simplified structure of the cell described in the third embodiment, which is almost the same as FIG. 6 except for the difference. Only the difference is that the SiN film and the SiON film for protecting the high dielectric layer 44 of BST from the external environment are described. _Two
That is, the protective film made of the film also serves as the insulating film 76 of the wiring layer.

<Embodiment 5> Si as an embodiment of the present invention
A method for manufacturing a MIM type thin capacitor formed on a single crystal substrate 1 will be described with reference to FIGS. As shown in FIG. 1A, a SiO ₂ layer 2 is formed to a thickness of about 500 nm on a Si single crystal substrate 1 having a thickness of about 500 μm, and a lower electrode layer 3 is formed on the SiO ₂ layer 2 in the order of Ti—Pt. Is formed by sputtering. A high melting point metal such as Ta may be used instead of Ti, and its thickness is about 100 nm. Subsequently, a sol-gel-like BST was prepared as a solution, and this solution was spin-coated, and was applied for about 600
Sintering in an oxygen atmosphere at a temperature of about 3.degree.
It is formed to a thickness of 00 nm. The high dielectric layer 4 is not limited to BST, for example, STO (SrTi
O ₃ ), PZT (Pb, ZrTiO ₃ ), etc.
The formation method may be sputtering or CVD (chemical vapor deposition). Subsequently, the upper electrode layer 5 is formed in the order of Ti-Pt-Au. This metal material is not limited to this.

After the MIM type structure is formed on the entire surface of the wafer, a photoresist layer corresponding to the pattern designed for the thin capacitor is formed, and the upper electrode layer 45 is processed by ion milling using the photoresist layer as a mask. The high dielectric layer 44 and the lower electrode layer 43 are processed and divided. In this step, the MIM type capacitor is placed in the unit cell 8 at the dividing position 6.
Is divided into

Subsequently, as shown in FIG.
An O ₂ insulating film 46 is formed, a conduction hole reaching the upper electrode layer 45 and the lower electrode layer 43 is processed, a wiring metal formed in the order of Ti—Pt—Au is formed, and ion milling is performed using the photoresist layer as a mask. The wiring layers 47 and 48 are processed by this. As a result, the unit cells of the MIM type capacitor are connected in parallel by the wiring layer 47 for the lower electrode and the wiring layer 48 for the upper electrode, so that the capacitor as a whole has a large capacity.

Subsequently, a SiN film and a SiO ₂ film are sequentially formed on this surface with a thickness of 100 nm and 600 nm, respectively, to form a protective film 49, a window for taking out the outside is opened, and the process on the front side is completed. . The SiN film is a high dielectric layer 44
AlN or Al ₂ O ₃ which has the same effect and may be used for the purpose of protecting the AlN from the external environment.

Subsequently, as shown in FIG.
about 180 μm from the back side of the Si single crystal substrate 1 having a thickness of μm.
m, and the Si was dissolved by a chemical etching solution containing HF and HNO ₃ as main components, and about 50 μm
Substrate thickness. Damage caused in the Si single crystal by this grinding can be completely removed by chemical etching of about 50 μm or more. As a result, an MIM type thin capacitor was manufactured on a Si single crystal wafer substrate having a thickness of about 50 μm, and the warpage of the wafer was within 20 μm. FIG.
(B) shows only a portion corresponding to FIG. 1 (a), and the actual element is in the state shown in FIG. Thereafter, chips were cut out from the wafer, and mass-produced MIM type thin capacitors having uniform characteristics were able to be produced.

Embodiment 6 FIG. 9 shows a thin LSI chip 91.
FIG. 3 is a cross-sectional structural view showing a configuration of a main part in which the thin capacitor chip 92 formed in the above embodiment is mounted on an F card. Each electrode of the thin capacitor chip 92 having the same thickness as the thin LSI chip 91 having a thickness of about 20 μm is connected to the wiring layer 98 by a conductive resin 99, the space around these is filled with the resin 90, and a spacer having a thickness of 20 μm is further provided. 95
And, it is sandwiched and fixed between the upper and lower resin films 93 and 96 (thickness of about 100 μm) of the same thickness surrounded by the adhesive layers 94 and 96. Although the thickness of the F card is as thin as about 250 μm, the thin LSI chip 91 and the thin capacitor chip 92 are arranged at the center (neutral surface) in the thickness direction of the F card as shown in the figure, so that the card is bent. The strength against twisting and twisting is at least one digit greater than that of the conventional IC card (about 750 μm thick) in FIG.

FIG. 10 is an overall configuration diagram of an F card 100 which is a non-contact type IC card. The F card 100 includes a tuning coil 101, thin LSI chips 91 and 91 ', a thin capacitor chip 92, and a wiring layer 98. FIG. 11 is an electric circuit diagram. The thin capacitor chip is L
It was used for the Cm tuning circuit and the smoothing capacitor Cp for full-wave rectification, and confirmed the effects characteristic of the F card.

The use of the thin capacitor is not limited to the F card, and the thin capacitor is used to
It is applied to the mounting of a multi-chip module for the purpose of miniaturization and light weight of a portable terminal device or the like. Further, a new application field such as reducing the power supply noise by bonding and connecting this to the surface of a large LSI such as a DRAM can be developed. In the present invention, an example of a thin capacitor chip has been described, but it goes without saying that the same principle can be applied to a thin LSI chip.

[0037]

As described above, according to the semiconductor device of the present invention, the production yield is improved as compared with the conventional one, and it is suitable for mass production.
It was easy to handle and the assembly yield was good.
Further, such a semiconductor device could be easily manufactured. In addition, a flexible card that is strong against bending and torsion could be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of an example of a semiconductor device of the present invention.

FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional structural view of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional structural view of a unit cell of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional structural view of a unit cell of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional structural view of a unit cell of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a sectional structural view of a unit cell of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional structural view showing a configuration of a main part of a conventional IC card.

FIG. 9 is a sectional structural view showing a configuration of a main part of an F card shown in Embodiment 6 of the present invention.

FIG. 10 is an overall configuration diagram of an F card shown in Embodiment 6 of the present invention.

FIG. 11 is an electric circuit diagram of an F card according to a sixth embodiment of the present invention.

[Explanation of symbols]

1 ... Si single crystal substrate 2 ... SiO ₂ layer 3,43,53,63,73 ... lower electrode layer 4,44,54,64,74 ... high dielectric layer 5,45,55 ... upper electrode layer 6 ... divided position 8 ... unit cell 20 ... chip 21 ... condenser 26 ... cell 29 ... Sukuraipu regions 46, 56, 66 and 76 ... SiO ₂ insulating film 47,48,57,58,67,68,77,78,9
8 Wiring layer 49, 59 Protective film layer 76 Insulating film 81 LSI chip 82 Capacitor chip 83, 87, 93, 96 Resin film 84, 86, 94, 96 Adhesive layer 85 Core layer 88 Wire 91, 91 ': Thin LSI chip 92: Thin capacitor chip 95: Spacer 99: Conductive resin 100: F card 101: Tuning coil

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 25/18 (72) Inventor Hiroto Oda 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo (72) Inventor Hiroshi Ota 5-20-1, Josuihoncho, Kodaira-shi, Tokyo In-house Hitachi, Ltd. (72) Invention Mitsuo Usami 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] 1. A semiconductor device comprising a semiconductor substrate having a thickness in a range of 1 μm to 100 μm and an element arranged on the semiconductor substrate, wherein at least one of film formation layers constituting the element is divided, A semiconductor device, wherein each of the divided elements is connected in parallel. 2. The semiconductor device according to claim 1, wherein said element is a capacitor having a metal-insulator-metal structure. 3. The semiconductor device according to claim 1, wherein the divided layer is a layer having the largest stress among the film forming layers constituting the element. 4. The largest planar layer among the divided layers has a length of one side both in the vertical and horizontal directions in a range of 1 to 20 times the thickness of the semiconductor substrate. The semiconductor device according to claim 1, wherein: 5. The semiconductor device according to claim 1, wherein said semiconductor substrate is a silicon single crystal substrate. 6. A step of forming an element composed of a plurality of film layers on a semiconductor substrate, a step of dividing at least one of the film layers constituting the element, and connecting the divided elements in parallel. Forming at least a part of a wiring layer for the semiconductor device, and polishing the back surface of the semiconductor substrate to reduce the thickness thereof to a thickness in a range of 1 μm to 100 μm. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the polishing of the back surface of the semiconductor substrate is performed by performing mechanical polishing and then performing chemical polishing. 8. The method according to claim 6, wherein the element is a capacitor having a metal-insulator-metal structure. 9. A flexible card comprising: the semiconductor device according to claim 1; and a flexible structural member having the semiconductor device disposed therein. 10. The flexible card according to claim 9, wherein said flexible card is a contactless card.