JP2939096B2 - Semiconductor device sealing method - Google Patents

Semiconductor device sealing method

Info

Publication number
JP2939096B2
JP2939096B2 JP5217110A JP21711093A JP2939096B2 JP 2939096 B2 JP2939096 B2 JP 2939096B2 JP 5217110 A JP5217110 A JP 5217110A JP 21711093 A JP21711093 A JP 21711093A JP 2939096 B2 JP2939096 B2 JP 2939096B2
Authority
JP
Japan
Prior art keywords
mold
resin
lead frame
fluid pressure
flow path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5217110A
Other languages
Japanese (ja)
Other versions
JPH0774193A (en
Inventor
雄司 八代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Consejo Superior de Investigaciones Cientificas CSIC
Original Assignee
Consejo Superior de Investigaciones Cientificas CSIC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consejo Superior de Investigaciones Cientificas CSIC filed Critical Consejo Superior de Investigaciones Cientificas CSIC
Priority to JP5217110A priority Critical patent/JP2939096B2/en
Publication of JPH0774193A publication Critical patent/JPH0774193A/en
Application granted granted Critical
Publication of JP2939096B2 publication Critical patent/JP2939096B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B29WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29CSHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14639Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、フルモールドタイプの
半導体装置の封止方法に関し、特に放熱面側のモールド
樹脂内に発生するボイド欠陥を未然に阻止しうる半導体
装置の封止方法の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for sealing a full-mold type semiconductor device, and more particularly to an improvement in a method for sealing a semiconductor device which can prevent a void defect occurring in a mold resin on a heat radiation surface. It is about.

【0002】[0002]

【従来の技術】従来のフルモールドタイプの半導体装置
の製造方法について図3及び図4を用いて説明する。こ
こで図3はリードフレーム完成品の平面図、図4(a)
は封止樹脂が未硬化状態の場合の金型断面図、図4
(b)は封止樹脂が半硬化状態の場合を示している。図
3において半導体素子7はリードフレーム3上にダイボ
ンドされ、更にリードフレーム3のリード端子にボンデ
ィングワイヤー8により電気的に接続される。リードフ
レーム3は上面モールド金型1及び下面モールド金型2
にセットされトランスファーモールド法により成型され
る。
2. Description of the Related Art A conventional method of manufacturing a full-mold type semiconductor device will be described with reference to FIGS. Here, FIG. 3 is a plan view of a completed lead frame product, and FIG.
FIG. 4 is a cross-sectional view of a mold when the sealing resin is in an uncured state, FIG.
(B) shows a case where the sealing resin is in a semi-cured state. In FIG. 3, the semiconductor element 7 is die-bonded on the lead frame 3 and further electrically connected to the lead terminals of the lead frame 3 by bonding wires 8. The lead frame 3 includes an upper mold 1 and a lower mold 2.
And molded by the transfer molding method.

【0003】可動ピン4、5は液状の熱硬化性樹脂9が
樹脂注入口6より流入しモールド空間内に充填される状
態では図4(a)に示す様にリードフレーム3を支持
し、樹脂が半硬化状態では図4(b)に示す様に上面又
は下面モールド金型1,2表面まで移動し、樹脂硬化状
態では成型品と金型の離型時に成型品を取り出すエジェ
クトピンとして作用する。
The movable pins 4 and 5 support the lead frame 3 as shown in FIG. 4A when the liquid thermosetting resin 9 flows from the resin injection port 6 and fills the mold space. In the semi-cured state, as shown in FIG. 4 (b), it moves to the upper or lower mold dies 1 and 2, and in the resin-cured state, acts as an eject pin for taking out the molded product when the mold is released from the mold. .

【0004】[0004]

【発明が解決しようとする課題】フルモールドタイプの
半導体装置においては、半導体素子7よりの発熱を外部
に速やかに放熱する為、放熱面下部の樹脂厚d1を出来
るだけ薄くする必要があった。樹脂厚を薄くすると図4
(a)に示すd1/d2の比が非常に小さくなりリード
フレーム3に対してリードフレーム上部の流路を流れる
樹脂aと下部の流路を流れる樹脂bとの間に大きな流圧
差を生じ、その結果モールド樹脂内にボイド欠陥10が
発生し製品に外観不良が生じた。
In a full-mold type semiconductor device, it is necessary to reduce the resin thickness d1 below the heat radiation surface as much as possible in order to quickly radiate heat generated from the semiconductor element 7 to the outside. Fig. 4 when resin thickness is reduced
(A), the ratio of d1 / d2 becomes very small, and a large flow pressure difference occurs between the resin a flowing in the upper flow path of the lead frame and the resin b flowing in the lower flow path with respect to the lead frame 3; As a result, void defects 10 occurred in the mold resin, resulting in poor appearance of the product.

【0005】このボイド欠陥10の発生を防ぐ為に肉厚
の薄い樹脂部分d1を厚くすることが考えられるが、こ
れは半導体素子7と放熱板に接するモールド樹脂裏面間
の熱抵抗が大きくなり放熱効果が低下し適切でない。
In order to prevent the occurrence of the void defect 10, it is conceivable to increase the thickness of the thin resin portion d1. However, this increases the thermal resistance between the semiconductor element 7 and the back surface of the mold resin in contact with the heat radiating plate. The effect is reduced and is not appropriate.

【0006】また、熱抵抗を小さくするには樹脂自体の
熱伝導率を上げれば良く、熱伝導率を上げるには樹脂中
のフィラーの含有量を増加させる必要がある。しかし、
フィラーの含有量を増加させると金型の摩耗が激しくな
り、その結果金型更新期間が短縮され金型費のコストア
ップにつながるという欠点があった。
In order to reduce the thermal resistance, it is necessary to increase the thermal conductivity of the resin itself. To increase the thermal conductivity, it is necessary to increase the content of the filler in the resin. But,
When the content of the filler is increased, there is a drawback in that the mold becomes severely worn, and as a result, the mold renewal period is shortened and the cost of the mold is increased.

【0007】[0007]

【課題を解決するための手段】本発明は、上記問題点に
鑑み、モールド空間内のリードフレーム3を境界にして
流路面積を広く形成した第1流路に上下動可能な流圧調
整部材11を設け、第1流路と第2流路の流圧をほぼ等
しくしたことを特徴とする。
SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a fluid pressure adjusting member capable of moving up and down in a first channel having a large channel area with a lead frame 3 in a mold space as a boundary. 11 is provided, and the flow pressures of the first flow path and the second flow path are made substantially equal.

【0008】[0008]

【作用】流圧調整部材を設け、第1流路と第2流路の流
圧をほぼ等しくした結果、液状絶縁樹脂が第1流路と第
2流路において、ほぼ均等の速度で流れる為、ボイド欠
陥の発生がなく良好な半導体装置の封止方法を提供でき
る。
Since the flow pressure adjusting member is provided to make the flow pressures of the first and second flow paths substantially equal, the liquid insulating resin flows at substantially equal speeds in the first and second flow paths. In addition, it is possible to provide a good semiconductor device sealing method without generation of void defects.

【0009】[0009]

【実施例】本発明の一実施例を図面に従って説明する。
図1(a)は、本発明のフルモールドタイプで封止樹脂
が未硬化状態の金型断面図、図1(b)は、同フルモー
ルドタイプで封止樹脂が半硬化状態の金型断面図、図2
は、本発明の封止方法により得られた成型品の平面図を
示している。
An embodiment of the present invention will be described with reference to the drawings.
FIG. 1A is a cross-sectional view of a full-mold type of the present invention in which the sealing resin is in an uncured state, and FIG. 1B is a cross-sectional view of the same full-mold type in which the sealing resin is in a semi-cured state. FIG. 2
Shows a plan view of a molded product obtained by the sealing method of the present invention.

【0010】図1(a)において、半導体素子7はリー
ドフレーム3にダイボンドされリードフレーム3と半導
体素子7は、ボンディングワイヤー8により電気的に接
続され回路形成されている。リードフレーム3は、下面
モールド金型2にセットされ次に、プレス機によって上
面モールド金型1を降下させ液状の熱硬化性樹脂9を樹
脂注入口6より注入しトランスファーモールド法によっ
て成型する。尚、モールド時、可動ピン4,5は従来技
術と同様の働きを行う。
In FIG. 1A, a semiconductor element 7 is die-bonded to a lead frame 3, and the lead frame 3 and the semiconductor element 7 are electrically connected by bonding wires 8 to form a circuit. The lead frame 3 is set in the lower mold 2, and then the upper mold 1 is lowered by a press machine, and a liquid thermosetting resin 9 is injected from the resin injection port 6 and molded by transfer molding. At the time of molding, the movable pins 4 and 5 perform the same operation as in the prior art.

【0011】本発明のポイントである流圧調整部材11
は樹脂注入時、d1=d3の位置に設定しリードフレー
ム上部の流路断面積と下部の流路断面積を等しくするこ
とにより液状の熱硬化性樹脂9のリードフレーム3より
上部と下部の流速をほぼ均等にすることが出来る。従っ
て、従来の方法において発生したようなリードフレーム
下部のボイド欠陥を防止することが出来る。
The point of the present invention, the fluid pressure adjusting member 11
Is set at the position of d1 = d3 at the time of resin injection and the flow cross-sectional area of the upper part of the lead frame is made equal to the cross-sectional area of the lower part of the lead frame. Can be made substantially equal. Therefore, it is possible to prevent void defects at the lower portion of the lead frame as occurred in the conventional method.

【0012】また、放熱板下部の樹脂厚d1を更に薄く
することにより従来と同等の熱抵抗を保ちながら、フィ
ラーの含有量を少なくすることが出来、金型の長寿命化
が実現出来る。
Further, by further reducing the resin thickness d1 at the lower portion of the heat sink, the content of the filler can be reduced while maintaining the same thermal resistance as in the prior art, and the mold life can be extended.

【0013】図1(b)に示すように流圧調整部材11
は、液状の熱硬化性樹脂9の注入が終了した時点で成型
品の表面まで持ち上げられ流圧調整部材11の空間は更
に樹脂により充填され、樹脂が完全に硬化した時点で金
型より成型品を取り出す機能として作用し、リードフレ
ーム3をリード端子部を除き完全に樹脂封止した半導体
装置が完成する。
As shown in FIG. 1B, the fluid pressure adjusting member 11
When the injection of the liquid thermosetting resin 9 is completed, the space of the fluid pressure adjusting member 11 is lifted up to the surface of the molded product, and the space of the fluid pressure adjusting member 11 is further filled with the resin. The semiconductor device in which the lead frame 3 is completely sealed with a resin except for the lead terminal portion is completed.

【0014】また、流圧調整部材11の成型品での判別
方法は、樹脂注入終了時に、流圧調整部材11が成型品
表面まで上昇する時、流圧調整部材11の位置が成型品
表面より数十ミクロン下がった位置で停止する為、成型
品の形状としては図2に示すように成型品表面に数十ミ
クロンの凹部12が出来ることから判別出来る。
The method of determining the fluid pressure adjusting member 11 for a molded product is as follows. When the fluid pressure adjusting member 11 rises to the surface of the molded product at the end of the resin injection, the position of the fluid pressure adjusting member 11 is set higher than the surface of the molded product. Since it stops at a position lowered by several tens of microns, the shape of the molded product can be discriminated from the formation of a recess 12 of several tens of microns on the surface of the molded product as shown in FIG.

【0015】この凹部をつける理由は、成型品の実装時
成型品を放熱板にビスとワッシャーで取り付ける際、凸
部になるとワッシャーの浮きが発生し問題を生じるとい
うことからである。
The reason for providing the concave portion is that, when mounting the molded product to the heat sink with screws and washers when mounting the molded product, if the convex portion is formed, the washer floats and causes a problem.

【0016】[0016]

【発明の効果】以上説明したように本発明によればモー
ルド空間内の金型とリードフレーム間の大きく分けて2
つの流路の内、流路断面積の大きい第1流路に上下動可
能な流圧調整部材を設けることにより、半導体素子−モ
ールド樹脂裏面間の熱抵抗を小さくし、金型摩耗の原因
となるフィラー含有量を少なくすることが出来、成型性
の良好な金型寿命の長い封止方法を提供出来る効果があ
る。更に、流体絶縁樹脂の注入時から注入終了までの
間、前記流圧調整部材を第1流路の流圧と第2流路の流
圧がほぼ等しくなるモールド空間内の所望の位置に保持
し、前記流体絶縁樹脂注入終了後、前記流圧調整部材を
上昇させるので、第1流路への流体絶縁樹脂の注入量を
流圧調整部材により抑えることができ、第1流路内に存
在する半導体素子及びボンディングワイヤーの樹脂注入
圧によるダメージを軽減できる。特に、ボンディングワ
イヤーの樹脂注入圧による変形、倒れ、破断等を防止で
きる。
As described above, according to the present invention, there are roughly two parts between the mold and the lead frame in the mold space.
By providing a fluid pressure adjusting member that can move up and down in the first channel having a large channel cross-sectional area among the two channels, the thermal resistance between the semiconductor element and the back surface of the mold resin is reduced, which causes mold wear. Therefore, there is an effect that a sealing method with good moldability and a long mold life can be provided. Furthermore, from the time of injection of the fluid insulating resin to the end of the injection,
In the meantime, the flow pressure adjusting member is connected to the flow pressure of the first flow path and the flow pressure of the second flow path.
Holds at desired position in mold space where pressures are almost equal
After the completion of the fluid insulating resin injection, the fluid pressure adjusting member is
Since it is raised, the injection amount of the fluid insulating resin into the first flow path is
It can be suppressed by the fluid pressure adjusting member, and
Injection of existing semiconductor elements and bonding wires
Pressure damage can be reduced. In particular, bonding wires
Prevents deformation, fall, breakage, etc. due to the resin injection pressure of the ear
Wear.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のフルモールドタイプの金型断面図で、
図(a)は樹脂注入時の図であり、図(b)は樹脂注入
後から硬化状態までの図である。
FIG. 1 is a sectional view of a full mold type mold according to the present invention;
FIG. 7A is a diagram at the time of resin injection, and FIG. 7B is a diagram from the resin injection to the cured state.

【図2】本発明の成型品の平面図である。FIG. 2 is a plan view of a molded product of the present invention.

【図3】従来品のリードフレーム完成品を示す図であ
る。
FIG. 3 is a view showing a conventional lead frame completed product.

【図4】従来方式のフルモールドタイプの金型断面図
で、図(a)は樹脂が未硬化状態の図であり、図(b)
は樹脂が半硬化状態の図である。
FIG. 4 is a cross-sectional view of a conventional full-mold type mold, in which FIG. 4A is a view of a resin in an uncured state, and FIG.
FIG. 3 is a view of a resin in a semi-cured state.

【符号の説明】[Explanation of symbols]

1 上面モールド金型 2 下面モールド金型 3 リードフレーム 4,5 可動ピン 6 樹脂注入口 7 半導体素子 8 ボンディングワイヤー 9 熱硬化性樹脂 10 ボイド欠陥 11 流圧調整部材 12 成型品表面の凹部 DESCRIPTION OF SYMBOLS 1 Upper mold die 2 Lower mold die 3 Lead frame 4,5 Movable pin 6 Resin injection port 7 Semiconductor element 8 Bonding wire 9 Thermosetting resin 10 Void defect 11 Flow pressure adjusting member 12 Concave part on molded product surface

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子とこの半導体素子を上部に
置するリードフレームと、これらを電気的に接続するボ
ンデイングワイヤー部を備え、前記半導体素子とリード
フレームをモールド空間内に配置し、このモールド空間
内に流体絶縁樹脂を注入硬化する半導体装置の封止方法
において、 流体絶縁樹脂注入時、前記流体絶縁樹脂の流路となるモ
ールド空間内のリードフレームの上部に流路面積が広い
第1流路と下部に流路面積が狭い第2流路を形成すると
共に、前記第1流路に上下動可能な流圧調整部材を設
け、前記流体絶縁樹脂の注入時から注入終了までの間、
前記流圧調整部材を第1流路の流圧と第2流路の流圧
ほぼ等しくなるモールド空間内の所望の位置に保持し、
前記流体絶縁樹脂注入終了後、前記流圧調整部材を上昇
させることを特徴とする半導体装置の封止方法。
And 1. A semiconductor element and the lead frame for mounting a semiconductor device on top, comprise a bonding wire portion electrically connecting, placing the semiconductor element and the lead frame in the mold space, the mold A method for sealing a semiconductor device, in which a fluid insulating resin is injected into a space and hardened, the first flow having a large flow area above a lead frame in a mold space serving as a flow path of the fluid insulating resin when the fluid insulating resin is injected. A second flow path having a narrow flow path area is formed in the lower part of the flow path, and a fluid pressure adjusting member that can move up and down is provided in the first flow path .
Holding the fluid pressure adjusting member at a desired position in the mold space where the fluid pressure of the first channel and the fluid pressure of the second channel are substantially equal ;
After the completion of the fluid insulating resin injection, the fluid pressure adjusting member is raised.
A method for sealing a semiconductor device.
JP5217110A 1993-09-01 1993-09-01 Semiconductor device sealing method Expired - Fee Related JP2939096B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5217110A JP2939096B2 (en) 1993-09-01 1993-09-01 Semiconductor device sealing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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JP2939096B2 true JP2939096B2 (en) 1999-08-25

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