JP2933793B2 - Multi-chip module - Google Patents
Multi-chip moduleInfo
- Publication number
- JP2933793B2 JP2933793B2 JP5025422A JP2542293A JP2933793B2 JP 2933793 B2 JP2933793 B2 JP 2933793B2 JP 5025422 A JP5025422 A JP 5025422A JP 2542293 A JP2542293 A JP 2542293A JP 2933793 B2 JP2933793 B2 JP 2933793B2
- Authority
- JP
- Japan
- Prior art keywords
- motherboard
- substrate
- electrically connected
- mcm
- chip module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高放熱かつ高周波のマ
ルチチップモジュール（以下ＭＣＭと略す）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-heat and high-frequency multi-chip module (hereinafter abbreviated as MCM).
【０００２】[0002]
【従来の技術】図４はこの種のマルチチップモジュール
の従来例を示す上面図、図５は同側断面図である。図に
おいて、１はＩＣ、２は低温焼成基板（以下基板と略
す）であり、該基板２のＩＣランド２ａ上に前記ＩＣ１
をダイスボンディングし、基板２とＩＣ１をボンディン
グワイヤ３で電気的に接続したのち、基板２のＩ／Ｏパ
ッド４にリード端子５を接続、保護用のカバー６と放熱
用のヒートシンク７を接着し完成する構造であった。2. Description of the Related Art FIG. 4 is a top view showing a conventional example of this type of multichip module, and FIG. 5 is a sectional side view thereof. In the drawing, reference numeral 1 denotes an IC, and 2 denotes a low-temperature fired substrate (hereinafter abbreviated as a substrate).
After the board 2 and the IC 1 are electrically connected with the bonding wires 3, the lead terminals 5 are connected to the I / O pads 4 of the board 2, and the protective cover 6 and the heat sink 7 for heat dissipation are bonded. It was a completed structure.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記構
成の従来技術によればマザーボードとの接続にリード端
子を用いているので、基板の信号伝送ラインの特性イン
ピーダンス５０Ωがこのリード端子部において５０Ωで
はなくなる。このような特性インピーダンスのミスマッ
チにより信号ノイズが発生し、ＭＣＭとマザーボード間
の信号伝送特性が悪化する。したがって高周波領域での
信号伝送特性が悪化し、ＭＣＭの高速動作を妨げるとい
う問題があった。However, according to the prior art having the above structure, the lead terminal is used for connection to the motherboard, so that the characteristic impedance 50Ω of the signal transmission line on the substrate is not 50Ω at the lead terminal portion. . Such characteristic impedance mismatches cause signal noise, which degrades signal transmission characteristics between the MCM and the motherboard. Therefore, there has been a problem that signal transmission characteristics in a high frequency range are deteriorated, and high-speed operation of the MCM is hindered.
【０００４】本発明は、以上の問題点に鑑み、ＭＣＭと
マザーボード間の信号ノイズを低減する構成を得て、マ
ザーボードからＭＣＭ内のＩＣに信号と電源の安定供給
を行ってＭＣＭの動作の安定化と高速化を実現すること
を目的とする。SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a configuration for reducing signal noise between an MCM and a motherboard, stably supplies signals and power from the motherboard to ICs in the MCM, and stabilizes the operation of the MCM. The purpose is to realize high speed and high speed.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、インピーダンスコントロール可能な端子
構造によりマザーボードとの電気的接続を行うようにす
る。すなわち、本発明は、ＩＣと、該ＩＣを電気的に接
続して搭載する基板とより成り、前記基板をマザーボー
ドに電気的に接続して同マザーボード上に搭載するマル
チチップモジュールにおいて、前記基板の周囲端部に凸
部を設け、該凸部の内部に前記基板に電気的に接続した
Ｉ／Ｏ接続用ＶＩＡを設け、前記凸部の周囲にＧＮＤ層
を設け、前記Ｉ／Ｏ接続用ＶＩＡをマザーボードに電気
的に接続して同マザーボード上に搭載することを特徴と
する。In order to achieve the above object, the present invention provides an electrical connection to a motherboard by means of a terminal structure capable of controlling impedance. That is, the present invention provides a multi-chip module comprising an IC and a substrate on which the IC is electrically connected and mounted, wherein the substrate is electrically connected to a motherboard and mounted on the motherboard. A convex portion is provided at a peripheral end, an I / O connection VIA electrically connected to the substrate is provided inside the convex portion, a GND layer is provided around the convex portion, and the I / O connection VIA is provided. Is electrically connected to a motherboard and mounted on the motherboard.
【０００６】[0006]
【作用】以上の構成により本発明は、凸部の内部でのＩ
／Ｏ接続用ＶＩＡの断面積、および凸部の周囲のＧＮＤ
層の前記Ｉ／Ｏ接続用ＶＩＡに対する距離を変化させる
ことで、ＭＣＭの端子構造となるＩ／Ｏ接続用ＶＩＡの
インピーダンスコントロールを自在に行う。これにより
端子構造においても基板内と同様のインピーダンスを保
持することができる。According to the present invention, the present invention provides a semiconductor device having an I
Area of VIA for I / O connection and GND around convex part
By changing the distance of the layer from the I / O connection VIA, the impedance of the I / O connection VIA serving as the terminal structure of the MCM can be freely controlled. This allows the terminal structure to maintain the same impedance as in the substrate.
【０００７】[0007]
【実施例】以下図面に従って実施例を説明する。図１は
本発明の一実施例を示す上面図、図２は同側断面図であ
る。図において、１はＩＣ、１１は低温焼成基板（以下
基板と略す）、１１ｂは前記基板１１のＩＣランド、３
はボンディングワイヤ、６は保護用のカバー、７はヒー
トシンクである。BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a top view showing an embodiment of the present invention, and FIG. 2 is a sectional side view of the same. In the drawing, 1 is an IC, 11 is a low-temperature fired substrate (hereinafter abbreviated as a substrate), 11b is an IC land of the substrate 11, 3
Is a bonding wire, 6 is a protective cover, and 7 is a heat sink.
【０００８】図３は前記基板１１を示す側断面図であ
り、同図に示す如く、前記基板１１には周囲端部に基板
の積層により、前記ＩＣ１よりも厚く積層した凸部１１
ａを設けてある。この凸部１１ａは内部にマザーボード
接続用の端子としてＩ／Ｏ接続用ＶＩＡ１２が設けられ
ている。このＩ／Ｏ接続用ＶＩＡ１２は、通常、積層時
に所定位置に一定面積の穴を重ねて開けて行くことによ
り形成した長穴内に導体ペーストを流し込んで形成す
る。１３は前記凸部の周囲に印刷またはメッキ等で設け
たＧＮＤ層である。FIG. 3 is a side sectional view showing the substrate 11. As shown in FIG. 3, the substrate 11 has a convex portion 11 thicker than the IC 1 by laminating the substrate on the peripheral edge.
a is provided. The convex portion 11a has an I / O connection via 12 as a terminal for connecting a motherboard inside. The I / O connection VIA 12 is usually formed by pouring a conductive paste into a long hole formed by piercing a hole of a predetermined area at a predetermined position during lamination. Reference numeral 13 denotes a GND layer provided around the projection by printing or plating.
【０００９】以上の構成の本実施例の作用を以下に説明
する。まず、基板１１の形成時に、凸部１１ａ内のＩ／
Ｏ接続用ＶＩＡ１２の断面積、および凸部の周囲のＧＮ
Ｄ層１３の前記Ｉ／Ｏ接続用ＶＩＡ１２に対する距離を
設定することで、Ｉ／Ｏ接続用ＶＩＡ１２において基板
１１の信号伝送ラインと同様の特性インピーダンスが保
持できるようにインピーダンスコントロールを行う。こ
のようなインピーダンスコントロールにより、従来リー
ド端子部において発生していたＭＣＭとマザーボード間
のノイズは低減される。The operation of this embodiment having the above configuration will be described below. First, at the time of forming the substrate 11, the I /
Cross-sectional area of VIA 12 for O connection and GN around convex part
By setting the distance of the D layer 13 to the I / O connection VIA 12, impedance control is performed so that the I / O connection VIA 12 can maintain the same characteristic impedance as the signal transmission line of the substrate 11. By such impedance control, noise between the MCM and the motherboard, which has conventionally occurred at the lead terminal portion, is reduced.
【００１０】ＩＣ１の基板１１への搭載は図４，図５に
示すとおりに従来のＭＣＭと同様であり、該基板１１の
ＩＣランド１１ｂ上に前記ＩＣ１をダイスボンディング
し、基板１１とＩＣ１をボンディングワイヤ３で電気的
に接続したのち、保護用のカバー６および放熱用のヒー
トシンク７を接着する。ＭＣＭとマザーボードの電気的
接続は半田８等によって行う。The mounting of the IC1 on the substrate 11 is the same as that of the conventional MCM as shown in FIGS. 4 and 5. The IC1 is die-bonded on the IC land 11b of the substrate 11, and the substrate 11 and the IC1 are bonded. After being electrically connected by the wires 3, the cover 6 for protection and the heat sink 7 for heat dissipation are bonded. The electrical connection between the MCM and the motherboard is made by solder 8 or the like.
【００１１】[0011]
【発明の効果】以上詳細に説明した如く、本発明は、Ｉ
Ｃと、該ＩＣを電気的に接続して搭載する基板とより成
り、前記基板をマザーボードに電気的に接続して同マザ
ーボード上に搭載するマルチチップモジュールにおい
て、前記基板の周囲端部に凸部を設け、該凸部の内部に
前記基板に電気的に接続したＩ／Ｏ接続用ＶＩＡを設
け、前記凸部の周囲にＧＮＤ層を設け、前記Ｉ／Ｏ接続
用ＶＩＡをマザーボードに電気的に接続して同マザーボ
ード上に搭載するので、インピーダンスコントロール可
能な端子構造によりマザーボードとの電気的接続を行う
ことができる。As explained in detail above, the present invention provides
C, and a substrate on which the IC is electrically connected and mounted. The multi-chip module electrically connected to the motherboard and mounted on the motherboard. Is provided inside the projection, an I / O connection VIA electrically connected to the substrate is provided, a GND layer is provided around the projection, and the I / O connection VIA is electrically connected to the motherboard. Since they are connected and mounted on the motherboard, they can be electrically connected to the motherboard by a terminal structure capable of controlling impedance.
【００１２】これにより、ＭＣＭとマザーボード間の信
号ノイズを低減することが可能となり、マザーボードか
らＭＣＭ内のＩＣに信号と電源の安定供給を行ってＭＣ
Ｍの動作の安定化と高速化を実現するという効果があ
る。さらに、本発明ではＭＣＭとマザーボードの電気的
接続方法を従来のリード端子を介して半田接続する方法
から、ＭＣＭの周囲凸部部内のＶＩＡとマザーボードを
半田等により直接接続する方法に変更したことによりＭ
ＣＭとマザーボードの電気的接続信頼性が向上し、従来
リードの半田付けに要していた工数の削減もできる。This makes it possible to reduce signal noise between the MCM and the motherboard.
There is an effect that the operation of M is stabilized and speeded up. Further, in the present invention, the electrical connection method between the MCM and the motherboard is changed from a conventional method of soldering connection via lead terminals to a method of directly connecting the VIA in the peripheral convex portion of the MCM and the motherboard by soldering or the like. M
The reliability of the electrical connection between the CM and the motherboard is improved, and the man-hour required for soldering the lead can be reduced.
【００１３】またＩ／Ｏリードを使用しないためハンド
リングが容易になり、ＭＣＭとしての歩溜まりの向上も
期待できる。Further, since the I / O lead is not used, handling becomes easy, and improvement in yield as an MCM can be expected.
【図１】本発明の一実施例を示す上面図である。FIG. 1 is a top view showing one embodiment of the present invention.
【図２】本発明の一実施例を示す側断面図である。FIG. 2 is a side sectional view showing one embodiment of the present invention.
【図３】本発明の一実施例の基板の構成を示す側断面図
である。FIG. 3 is a side sectional view showing a configuration of a substrate according to one embodiment of the present invention.
【図４】従来例を示す上面図である。FIG. 4 is a top view showing a conventional example.
【図５】従来例を示す側断面図である。FIG. 5 is a side sectional view showing a conventional example.
１ ＩＣ １１ 基板 １１ａ 凸部 １２ Ｉ／Ｏ接続用ＶＩＡ １３ ＧＮＤ層 DESCRIPTION OF SYMBOLS 1 IC 11 board 11a convex part 12 VIA 13 I / O connection GND layer
Claims (1)
る基板とより成り、 前記基板をマザーボードに電気的に接続して同マザーボ
ード上に搭載するマルチチップモジュールにおいて、 前記基板の周囲端部に凸部を設け、 該凸部の内部に前記基板に電気的に接続したＩ／Ｏ接続
用ＶＩＡを設け、 前記凸部の周囲にＧＮＤ層を設け、 前記Ｉ／Ｏ接続用ＶＩＡをマザーボードに電気的に接続
して同マザーボード上に搭載することを特徴とするマル
チチップモジュール。1. A multi-chip module comprising an IC and a substrate on which the IC is electrically connected and mounted, wherein the substrate is electrically connected to a motherboard and mounted on the motherboard. A convex portion is provided at an end portion, an I / O connection VIA electrically connected to the substrate is provided inside the convex portion, a GND layer is provided around the convex portion, and the I / O connection VIA is provided. A multi-chip module electrically connected to a motherboard and mounted on the motherboard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5025422A JP2933793B2 (en) | 1993-02-15 | 1993-02-15 | Multi-chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5025422A JP2933793B2 (en) | 1993-02-15 | 1993-02-15 | Multi-chip module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06244356A JPH06244356A (en) | 1994-09-02 |
| JP2933793B2 true JP2933793B2 (en) | 1999-08-16 |
Family
ID=12165525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5025422A Expired - Lifetime JP2933793B2 (en) | 1993-02-15 | 1993-02-15 | Multi-chip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2933793B2 (en) |
-
1993
- 1993-02-15 JP JP5025422A patent/JP2933793B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06244356A (en) | 1994-09-02 |
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