JP2932820B2 - Phase detection circuit, delay detection demodulation device, and phase detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay detection and demodulation device in the field of wireless communication systems, and more particularly to a delay detection and demodulation device using a phase detection circuit and an improvement of a phase detection circuit used therefor.

[0002]

2. Description of the Related Art A conventional delay detection demodulation apparatus using a phase detection circuit is disclosed in, for example, the document "Digital Intermediate Frequency Demodulation System".
(Tomita, Kasai, Matsuki, 1990 IEICE Autumn National Convention, B-299). Hereinafter, the related art will be described with reference to the drawings.

FIG. 11 is a block diagram showing a configuration of a conventional delay detection demodulation device provided with a phase detection circuit.
100 is a limiter amplifier, 200 is a phase detection circuit, 201
Is a counter modulo K (K is a positive integer), 202 is D
A type flip-flop, 300 is a delay element having a delay time equal to one symbol period of the received signal, 301 is a subtractor modulo 2π, and 302 is a decision unit.

Next, the operation will be described. The received signal, which is a differential phase shift keying (hereinafter abbreviated as DPSK) modulation signal, is converted into a rectangular waveform signal having a constant amplitude by the limiter amplifier 100. That is, the limiter amplifier 100 functions as a quantizer that binarizes the received signal. Hereinafter, it is assumed that the received signal is quantized by the limiter amplifier 100 into binary values of logic “0” and logic “1”.

On the other hand, a counter 201 modulating K (K is a positive integer) in the phase detection circuit 200 has a clock signal having a frequency substantially equal to K times the received signal (hereinafter abbreviated as "driving clock"). Driven by The output of counter 201 modulo K is a D-type flip-flop 2
02 is input. The D-type flip-flop 202 is driven by a binary quantized reception signal output from the limiter amplifier 100. With such a configuration, the output signal of the D-type flip-flop 202, which is the output of the phase detection circuit 200, takes a value indicating the relative phase of the binary quantized reception signal.

This will be described with reference to the drawings. 12 and 13 show the phase detection circuit 200 when K = 16.
6 is a timing chart showing an example of the operation of FIG. FIG.
FIG. 13 shows a signal obtained by dividing the driving clock of the counter 201 by K (in this case, 16) by K (that is, dividing by 16) as a virtual phase reference signal. This virtual phase reference signal rises at the moment when the output of the counter 201 modulating K becomes “0” and “K /
2 ”(ie,“ 8 ”), where T is the period of the driving clock of the counter 201 modulo K and T _{r is} the period of the virtual phase reference signal.
Then, it is clear that the relationship given by the following equation holds.

[0007] _Tr = KT

Accordingly, the phase difference の between the virtual phase reference signal and the binary quantized received signal is calculated by
Assuming that the time difference between the rising edge of the received signal and the value
It is given by the following equation.

Ψ = 2πτ / T _r = 2πτ / (KT)

On the other hand, as is clear from FIG. 12, at the moment when the binary quantized reception signal rises, the output of the counter 201 modulating K is the difference between the virtual phase reference signal and the binary quantized reception signal. The value obtained by normalizing the rise time difference τ by the drive clock period T of the counter 201 modulo K is an integer value in which the fractional part is rounded down.

Therefore, the output of the counter 201 modulo K is used as an input to drive D by the binary quantized reception signal.
The output of the type flip-flop 202 always represents the fractional part of the value obtained by normalizing the rise time difference τ between the virtual phase reference signal and the binary quantized reception signal by the drive clock period T of the counter 201 modulo K. Take the truncated integer value. That is, if the output value of the D-type flip-flop 202 is μ (μ {0, 1,..., K−1}),
The following equation holds between μ, T, and τ.

Μ ≦ τ / T <(μ + 1)

From the above, it can be said that the relationship given by the following equation holds between the phase difference ψ between the virtual phase reference signal and the binary quantized received signal and the value μ of the output of the D-type flip-flop 202. it is obvious.

2πμ / K ≦ ψ <2π (μ + 1) / K

This relation is that the value μ of the output of the D-type flip-flop 202, which is the output of the phase detection circuit 200, is
This indicates that the binary quantized received signal can be handled as a relative phase based on a virtual phase reference signal.
For example, in FIG. 12, a virtual phase reference signal and 2
Since the relative phase of the value-quantized reception signal is always constant, the D-type flip-flop 202 always outputs a constant value “8”. FIG. 13 shows a virtual phase reference signal and 2
This is the case where the relative phase of the value-quantized received signal changes.
When the value-quantized reception signal A is input, the output of the D-type flip-flop 202 changes from “7” to “9”. When the binary quantized reception signal B is input, D
The output of the type flip-flop 202 changes from “9” to “7”. In either case, it is clear that the output of the D-type flip-flop 202 changes according to the relative phase between the virtual phase reference signal and the binary quantized received signal.

The relative phase signal output from the phase detection circuit 200 is delayed by a delay element 300 whose delay time is equal to one symbol period of the received signal. At the same time, the relative phase signal is also input to a subtractor 301 modulo 2π. A 1-symbol-delayed relative phase signal output from the delay element 300 is also input to the subtractor 301 modulo 2π.
A phase difference signal, which is a value obtained by subtracting the relative phase signal delayed by one symbol period from the relative phase signal by 2π, is output. This phase difference signal represents a phase transition during one symbol period of the received signal. Subtractor 30 modulo 2π
The phase difference signal output from 1 is input to the determiner 302. The determiner 302 outputs demodulated data corresponding to the value of the phase difference signal according to a predetermined rule for the correspondence between the phase difference signal and the demodulated data.

[0017]

As described above, the conventional phase detection circuit drives the D-type flip-flop only at the rise of the binary quantized reception signal. For this reason,
The relative phase signal output from the phase detection circuit is updated only for each cycle of the binary quantized reception signal. However, 2
The relative phase of the value-quantized received signal can be measured not only at the rise but also at the fall of the binary-quantized received signal. Therefore, in principle, although the relative phase value of the binary quantized received signal can be updated twice per cycle of the binary quantized received signal, the conventional phase detection circuit can only be updated once per cycle. There is a problem that the update is not performed, that is, the update speed of the relative phase signal is low.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and can update the relative phase value of a binary quantized received signal twice per cycle of the binary quantized received signal.
An object of the present invention is to provide a phase detection circuit and a phase detection method with a high update speed of a relative phase signal, and a delay detection and demodulation device including the same.

[0019]

A phase detection circuit according to the present invention comprises, for example, a delay element for delaying an input signal, and an exclusive OR signal of an output signal of the delay element and the input signal. An exclusive-OR element, a counter driven by a clock signal having a frequency approximately equal to 2N (N is a positive integer) times the input signal, and the counter according to a value of an output signal of the delay element Phase inverting means for outputting a value obtained by adding a numerical value "0" or "N" to the output signal of the above, and an exclusive OR which is an output of the exclusive OR element with the output signal of the inverting phase correcting means as an input. And a D-type flip-flop driven by a signal, and has the following elements. (A) An input signal having a predetermined cycle is input and the input signal is
A half-period detector that outputs a half-period detection signal for each half-period of the signal
With stages, the frequency of at least twice the frequency of the (b) said input signal
A reference signal that detects the phase based on the clock signal
(C) a phase generated by the phase reference signal generating means.
A reference signal and a half cycle output by the half cycle detecting means.
On the basis of the period detection signal, every half cycle of the input signal.
Outputs the phase difference between the reference signal and the input signal.
Difference output means.

Further, the differential detection and demodulation device according to the present invention
The phase detection circuit, a delay element that delays the output signal of the phase detection circuit by one symbol period of the received signal, and a subtractor that subtracts the output signal of the delay element from the output signal of the phase detection circuit. It is characterized by the following.

The phase detection method according to the present invention includes the following steps. (A) a half-period detection step of detecting a half-period timing of an input signal from an input signal, (b) a phase reference signal generation step of generating a reference signal for detecting a phase of the input signal, (c) a half-period A phase difference output step of outputting a phase difference between the reference signal generated in the reference signal generation step and the input signal at a half cycle timing detected in the detection step.

[0022]

In the phase detection circuit (or the phase detection method) according to the present invention, for example, the half-period detection means (process) using the delay element and the first exclusive-OR element detects the rising and falling of the input signal. Acts as a differentiating circuit that generates a pulse signal instantaneously, and detects a half cycle of the input signal. Also, a phase difference output means (step) including an inversion phase correction means
Corrects the phase reference signal with the input signal every half cycle by correcting the output of the counter by a numerical value “N” corresponding to the phase π at the moment of the falling of the input signal. Then, the phase difference between the corrected phase reference signal and the input signal is output every half cycle.

The delay detection and demodulation device according to the present invention can update the relative phase value of the binary quantized received signal twice per cycle of the binary quantized received signal by including the above-mentioned phase detection circuit. Therefore, the update speed of the relative phase signal is increased.

[0024]

[Embodiment 1] The first embodiment will be described below with reference to the drawings. FIG.
1 is a configuration diagram illustrating an example of a configuration of a differential detection and demodulation device including a phase detection circuit according to a first embodiment.
Is a phase detection circuit, 401 is a delay element, 402 is an exclusive OR element, 403 is a counter modulo 2N (N is a positive integer), 404 is a D-type flip-flop, and 500 is multipliers 501 and 2N to be described later. Inverting phase correcting means constituted by an adder 502 modulo 501, a multiplier 501,
02 is an adder modulo 2N. A half-period detection unit 901 receives an input signal having a predetermined period and outputs a half-period detection signal for each half period of the input signal, or a half-period that detects the timing of the input signal half-period from the input signal. The detecting step 902 is a phase reference signal generating means for generating a phase reference signal serving as a reference signal for detecting a phase based on a clock signal having a frequency of twice or more of the frequency of the input signal , or a phase of the input signal. A phase reference signal generating step of generating a reference signal for detection, 9
Numeral 03 denotes a phase reference signal generated by the phase reference generating means, which is corrected in units of a half cycle of the input signal, and the phase reference signal thus corrected and the half cycle output by the half cycle detecting means. A phase difference output means for outputting a phase difference between the phase reference signal and the input signal every half cycle of the input signal based on the detection signal, or a reference signal generation step at a half cycle timing detected by the half cycle detection step; This is a phase difference output step of outputting a phase difference between the generated reference signal and the input signal. In addition, the same or corresponding parts as those in FIG.

Next, the operation will be described. In FIG. 1, a received signal that is a DPSK modulated signal is a limiter amplifier 1
00 results in a rectangular waveform signal having a constant amplitude. That is, the limiter amplifier 100 functions as a quantizer that binarizes the received signal. Hereinafter, it is assumed that the received signal is quantized by the limiter amplifier 100 into binary values of logic “0” and logic “1”.

The binary quantized reception signal output from the limiter amplifier 100 is input to the phase detection circuit 400. In the phase detection circuit 400, the binary quantized reception signal is input to the delay element 401. It is assumed that the delay time of the delay element 401 is shorter than a half cycle of the binary quantized reception signal. The delayed reception signal output from the delay element 401 is input to the exclusive OR element 402. On the other hand, a binary quantized reception signal is also input to the exclusive OR element 402, and an exclusive OR operation with the delayed reception signal is performed. With such a configuration, the exclusive OR element 402 outputs 2
A pulse signal (hereinafter, referred to as a differential pulse signal) rising at the rising and falling moments of the value-quantized reception signal is output. This will be described with reference to the drawings. FIG.
6 is a timing chart illustrating an example of an operation of a delay element 401 and an exclusive OR element 402. As shown in FIG. 2, by setting the delay time of the delay element 401, that is, the delay time of the delayed received signal with respect to the binary quantized received signal to be shorter than a half cycle of the binary quantized received signal, exclusive processing is performed. Obviously, the differentiated pulse signal output from the OR element 402 has a rising edge at the rising and falling moments of the binary quantized received signal.

On the other hand, in the phase detection circuit 400,
The counter 403 modulo N (N is a positive integer) is driven by a clock signal (hereinafter abbreviated as “driving clock”) having a frequency approximately equal to 2N times the received signal. Here, similarly to the conventional example, when the output of the counter 403 modulo 2N, which is obtained by dividing the drive clock of the counter 403 modulo 2N by 2N, becomes “0”, the counter rises to “N”. Assuming that the signal falling at the moment becomes as a virtual phase reference signal, the output of the counter 403 modulo 2N indicates the phase of this virtual phase reference signal. That is, when the value of the output of the counter 403 modulo 2N is α (α {0, 1,..., 2N−1}) when the phase of the virtual phase reference signal is θ, θ And α have the relationship given by the following equation.

Πα / N ≦ θ <π (α + 1) / N

Therefore, the value of the output of the counter 403 modulo 2N at the moment when the differentiated pulse signal which is the output of the exclusive OR element 402 rises is the virtual value at the moment when the binary quantized reception signal rises and falls. This indicates the phase of the typical phase reference signal. At the moment when the binary quantized received signal falls, the absolute phase of the binary quantized received signal is π. Therefore, at the moment when the binary quantized reception signal falls, 2
If the value of the output of the counter 403 modulo N is corrected by the numerical value “N” corresponding to the phase π, a virtual value at the moment when the binary quantized reception signal falls, which cannot be obtained in the conventional example. Relative phase of the binary quantized received signal with reference to the standard phase reference signal.

This will be described with reference to the drawings. FIG.
When N = 8, the output of the counter 403 modulo 2N (16 in this case), a virtual phase reference signal,
6 is a timing chart illustrating an example of a relationship between a binary quantized reception signal and a differential pulse signal. Here, assuming that the period of the driving clock of the counter 403 modulo 2N is T and the period of the virtual phase reference signal is _Tr , it is clear that the relationship given by the following equation holds.

T _r = 2NT

From this, the phase difference の between the virtual phase reference signal and the binary quantized received signal is calculated as follows:
If the time difference between the rise and fall of the value-quantized received signal is τ, it is given by the following equation.

Ψ = 2πτ / T _r = πτ / (NT)

On the other hand, as is apparent from FIG. 3, at the moment when the binary quantized reception signal rises, the value of the output of the counter 403 modulo 2N is β ₁ (β ₁ ∈ ｛0, 1,..., 2
N−1}), β ₁ is the virtual phase reference signal and 2
The value obtained by normalizing the rise time difference τ from the value-quantized reception signal by the drive clock period T of the counter 403 modulo 2N is an integer value in which the fractional part is rounded down. That is,
The relationship given by the following equation is established between β ₁ , T, and τ.

Β ₁ ≦ τ / T <(β ₁ +1)

At the moment when the virtual phase reference signal falls, the output value of the counter 403 modulo 2N is "N" (8 in FIG. 3) corresponding to the phase π.
At the moment when the binary quantized reception signal falls, the value of the output of the counter 403 modulo 2N is represented by β ₂ (β ₂ ∈ ｛0,1,
.., 2N−1}), β ₂ is the time difference τ between the fall of the virtual phase reference signal and the binary quantized reception signal by 2N
Is a value obtained by adding a numerical value “N” modulo 2N to an integer value obtained by rounding down the decimal portion of the value normalized by the driving clock cycle T of the counter 403 modulo 2N. From this, β2,
The relationship given by the following equation holds between T and τ.

(Β ₂ −N) ≦ τ / T <(β ₂ −N + 1)

However, the subtraction in this case is a subtraction modulo 2N. However, subtracting N modulo 2N is equivalent to adding N modulo 2N. Therefore, the relationship given by the following equation holds between β ₂ , T, and τ.

(Β ₂ + N) ≦ τ / T <(β ₂ + N + 1)

From the above, the phase difference の between the virtual phase reference signal and the binary quantized received signal, the value β ₁ of the output of the counter 403 modulo 2N at the moment when the binary quantized received signal rises, and 2N at the moment when the binary quantized reception signal falls
Between the value beta ₂ of the output of counter 403 modulo It is clear that the relationship given by the following equation is established.

Πβ ₁ / N ≦ ψ <π (β ₁ +1) / N π (β ₂ + N) / N ≦ ψ <π (β ₂ + N + 1) / N

This relationship is based on the value β of the output of the counter 403 modulo 2N at the moment when the binary quantized reception signal rises.
₁ and the value obtained by adding the numerical value “N” modulo 2N to the value β ₂ of the output of the counter 403 modulo 2N at the moment when the binary quantized received signal falls is based on the virtual phase reference signal. It can be treated as a relative phase of the binary quantized received signal. In other words, the value of the output of the counter 403 modulo 2N is set to the value “0” at the moment when the binary quantized reception signal rises, and to the value “0” at the moment when the binary quantized reception signal falls. By adding N ″, the relative phase of the binary quantized received signal can be known.

The inverted phase correcting means 500 performs the above correction on the output value of the counter 403 modulo 2N. In other words, the inverted phase correction means 500 receives the output of the counter 403 modulo 2N as an input, and adds the numerical value “0” to the moment the binary quantized reception signal rises, and outputs the binary quantized reception signal. At the moment of falling, a value obtained by adding the numerical value “N” is output. Hereinafter, the inversion phase correcting means 50 will be described with reference to the drawings.
The operation principle of 0 will be described. FIGS. 4, 5 and 6 show the case where N = 8 (that is, 2N = 16), respectively.
6 is a timing chart illustrating an example of an operation of the phase detection circuit 400. As is apparent from these figures, the delay element 4
01 is always “0” at the moment when the binary quantized reception signal rises.
It is always "1" at the moment when the value-quantized reception signal falls. Therefore, the multiplier 501 in the inverted phase correction means 500
By multiplying the value of the delayed reception signal output from the delay element 401 by N times, the multiplier 501 always outputs “0” at the moment when the binary quantized reception signal rises,
At the moment when the binary quantized reception signal falls, a signal which is always "N" is output. Therefore, the counter 403 modulo 2N is added by the adder 502 modulo 2N.
Is added to the output of the multiplier 501, so that the output of the adder 502 modulo 2N, which is the output of the inversion phase correction means 500, modulates 2N at the moment when the binary quantized reception signal rises. The value of the output of the counter 403 which modulates 2N at the moment when the binary quantized reception signal falls, and the value of the output of the counter 403 modulo 2N at the moment when the binary quantized reception signal falls. And take the value added.

2N which is the output of the inversion phase correction means 500
The output of the adder 502 modulo is input to a D-type flip-flop 404. The D-type flip-flop 404 is driven by a differential pulse signal output from the exclusive OR element 402. As described above, since the differential pulse signal has a rise at the rising and falling moments of the binary quantized reception signal, the D-type flip-flop 4
04 is driven at the rising and falling moments of the binary quantized reception signal. From the above, assuming that the output value of the D-type flip-flop 404 is μ, μ and the output value β ₁ of the counter 403 modulo 2N at the moment when the binary quantized reception signal rises, and the binary quantization It is clear that the relationship given by the following equation holds between the value β ₂ of the output of the counter 403 modulo 2N at the moment when the received signal falls.

Μ = β ₁ or μ = β ₂ + N

Therefore, the phase difference の between the virtual phase reference signal and the binary quantized received signal is calculated by using the D type flip-flop 4
A relationship given by the following equation is established between the value of the output signal 04 and the value μ of the output signal.

Πμ / N ≦ ψ <π (μ + 1) / N

This relationship indicates that the value μ of the output of the D-type flip-flop 404, which is the output of the phase comparison circuit 400, is
This indicates that the binary quantized received signal can be handled as a relative phase based on a virtual phase reference signal.
This is evident with reference to FIGS. 4, 5 and 6. In the conventional example, the output of the D-type flip-flop 202 indicating the relative phase of the binary quantized received signal is updated only once per one cycle of the binary quantized received signal. Since the D-type flip-flop 404 is driven by the differential pulse signal having a rise at the rising and falling moments of the value-quantized reception signal, the output of the D-type flip-flop 404 indicating the relative phase of the binary-quantization reception signal. Are updated twice per cycle of the binary quantized received signal. That is, in the present embodiment, the update speed of the relative phase signal output from the phase detection circuit is doubled as compared with the conventional example. This is apparent from a comparison between FIGS. 4 and 12, and FIGS. 5 and 6 and FIG.

Further, the binary quantized reception signal shown in FIG.
Is the same signal as the binary quantized reception signal A of FIG.
Is the output of the conventional phase detection circuit 200 shown in FIG.
The output A of the type flip-flop 202 becomes “7” →
The output of the D-type flip-flop 404, which is the output of the phase detection circuit 400 of the present embodiment shown in FIG. 5 while changing to “9”, is “7” → “8” → “9”. Is changing. Similarly, the binary quantized received signal of FIG.
Is the same signal as the binary quantized reception signal B of FIG.
The output B of the D-type flip-flop 202 shown in FIG. 6 changes from “9” to “7”, whereas the output of the D-type flip-flop 404 shown in FIG.
It changes from “8” to “7”. That is, in the present embodiment, the update speed of the relative phase signal, which is the output of the phase detection circuit, is doubled as compared with the conventional example, so that the change in the value of the relative phase signal becomes smoother.

The relative phase signal output from phase comparison circuit 400 is delayed by delay element 300 whose delay time is equal to one symbol period of the received signal. At the same time, the relative phase signal is also input to a subtractor 301 modulo 2π. A 1-symbol-delayed relative phase signal output from the delay element 300 is also input to the subtractor 301 modulo 2π.
A phase difference signal, which is a value obtained by subtracting the relative phase signal delayed by one symbol period from the relative phase signal by 2π, is output. This phase difference signal represents a phase transition during one symbol period of the received signal. Subtractor 30 modulo 2π
The phase difference signal output from 1 is input to the determiner 302. The determiner 302 outputs demodulated data corresponding to the value of the phase difference signal according to a predetermined rule for the correspondence between the phase difference signal and the demodulated data.

Embodiment 2 FIG. In the above embodiment, a case was described in which a multiplier was provided as a component of the inversion phase correction means. However, this is because a numerical value “0” is input when a numerical value “0” is input, and a numerical value “1” is input. Is input as long as it outputs a numerical value "N". For example, when a numerical value "0" is input as a data selection signal, a numerical value "0" is output.
And a data selector for selecting and outputting a numerical value “N” when a numerical value “1” is input, and a logical AND element for obtaining a logical product of an input signal and each bit of the numerical value “N”. Is also good.

Embodiment 3 FIG. Further, in the above embodiment, the case where the modulation scheme of the received signal is the DPSK modulation scheme has been described, but other modulation schemes such as the MSK modulation scheme and G
The MSK modulation method may be used. Further, in the above embodiment, the case where the constant N, which is the operation parameter of the phase detection circuit 400, is N = 8 has been described.
May be a positive integer, for example, N = 16 or N = 32.
It may be.

Embodiment 4 FIG. Next, a fourth embodiment will be described with reference to the drawings. FIG.
FIG. 14 is a configuration diagram illustrating an example of a configuration of a differential detection and demodulation device including a phase detection circuit according to a fourth embodiment .
a is a phase detection circuit, 403a is a counter modulo 2 ^M (M is a positive integer), 404a is a D-type flip-flop, 500a is an inverted phase correcting means constituted by an exclusive OR element 503 described later, 503 Is an exclusive OR element. 1 and 11 are denoted by the same reference numerals, and description thereof is omitted.

Next, the operation will be described. In FIG. 7, the received signal which is a DPSK modulated signal is converted into a rectangular waveform signal having a constant amplitude by the limiter amplifier 100 as in the first embodiment. That is, the limiter amplifier 100 functions as a quantizer that binarizes the received signal. Hereinafter, it is assumed that the received signal is quantized by the limiter amplifier 100 into binary values of logic “0” and logic “1”.

The binary quantized reception signal output from the limiter amplifier 100 is input to the phase detection circuit 400a. In the phase detection circuit 400a, the binary quantized reception signal is input to the delay element 401. The delay time of the delay element 401 is shorter than a half cycle of the binary quantized received signal. The delayed reception signal output from the delay element 401 is input to the exclusive OR element 402. On the other hand, a binary quantized reception signal is also input to the exclusive OR element 402, and an exclusive OR operation with the delayed reception signal is performed. As in the first embodiment, by adopting such a configuration, a pulse signal (hereinafter, referred to as a differential pulse signal) rising from the exclusive OR element 402 at the rising and falling moments of the binary quantized reception signal. Is output.

On the other hand, in the phase detection circuit 400a,
The counter 403a modulo 2 ^M (M is a positive integer) is
It is driven by a clock signal (hereinafter, abbreviated as “driving clock”) having a frequency approximately equal to 2 ^M times the received signal. Here, in the same manner as in Example 1, 2 ^M obtained by 2 ^M division drive clock of the counter 403a modulo, the output of the counter 403a which of 2 ^M modulo rises the moment becomes "0" , “2 ^M−1 ”, a signal falling at the moment becomes a virtual phase reference signal.
The output of the counter 403a modulo ^M indicates the phase of this virtual phase reference signal. That is, when the phase of the virtual phase reference signal is θ, the value of the output of the counter 403a modulo 2 ^M is α (α∈ ｛0, 1,
.., 2 ^M -1}), the relationship given by the following equation is established between θ and α.

2πα / 2 ^M ≦ ψ <2π (α + 1) / 2 ^M

Therefore, the value of the output of the counter 403a modulo ^2M at the moment when the differentiated pulse signal, which is the output of the exclusive OR element 402, rises is determined at the moment when the binary quantized reception signal rises and falls. This indicates the phase of the virtual phase reference signal. The absolute phase of the binary quantized received signal at the moment when the binary quantized received signal falls is π
It is. Therefore, if the value of the output of the counter 403 a modulo 2 ^M at the moment when the binary quantized reception signal falls is corrected by a numerical value “2 ^M−1 ” corresponding to the phase π, the first embodiment is achieved.
Similarly to the above, it is possible to obtain the relative phase of the binary quantized received signal with respect to the virtual phase reference signal at the moment when the binary quantized received signal falls.

The inverted phase correction means 500a performs the above correction on the output value of the counter 403a modulo ^2M .
That is, like the inverted phase correcting means 500 of the first embodiment, the inverted phase correcting means 500a receives the output of the counter 403a modulo ^2M as an input, and outputs the numerical value at the moment when the binary quantized reception signal rises. At the moment when the binary quantized reception signal falls, a value obtained by adding the numerical value “2 ^M−1 ” is output. Hereinafter, the operation principle of the inversion phase correction means 500a will be described with reference to the drawings.

FIGS. 8, 9 and 10 show that M =
4 is a timing chart showing an example of the operation of the phase detection circuit 400a when the value is 4 (that is, 2 ^M = 16). The number of bits of the output of the counter 403a modulo ^2M is clearly M bits, and the most significant bit (hereinafter, abbreviated as MSB) represents the digit of the numerical value " ^2M-1 ". . Therefore, the counter 403a modulo ^2M
The output of the numerical adding "2 ^M-1" a of 2 ^M modulo is the output of the counter 403a which of 2 ^M modulo MSB
Is logically inverted. That is, the output of the counter 403a which of 2 ^M modulo, the numerical value "0" is the moment the binary quantizing the received signal rises, also figures the moment the binary quantizing the received signal falls "2 ^{M- The} value obtained by adding ¹ "is the MS of the output of the counter 403a modulo ^2M.
B is not logically inverted at the moment when the binary quantized received signal rises, and is logically inverted at the moment when the binary quantized received signal falls.

On the other hand, as is clear from FIGS. 8, 9 and 10, the value of the delayed received signal output from the delay element 401 is always "0" at the moment when the binary quantized received signal rises. Yes, and is always "1" at the moment when the binary quantized reception signal falls. Therefore, the exclusive OR element 503 in the inverted phase correction means 500a generates an exclusive OR signal of the MSB of the output of the counter 403a modulo 2 ^M and the delayed reception signal output from the delay element 401, A signal obtained by combining this with the lower bit (first bit to the (M-1) th bit) of the counter 403a modulo ^2M as a new MSB is a counter 403 modulo ^2M.
The MSB of the output of a is not logically inverted at the moment when the binary quantized received signal rises, and is logically inverted at the moment when the binary quantized received signal falls. That is,
The counter 40 modulating 2 ^M using the exclusive OR element 503 as the MSB, which is the output of the inversion phase correction means 500a.
The signal synthesized with the lower bit of 3a has a value “0” at the moment when the binary quantized reception signal rises, and the binary quantization reception signal falls at the output of the counter 403a modulo 2 ^M. At the moment, it becomes a value obtained by adding the numerical value “2 ^M−1 ”.

As described above, the phase detection circuit of this embodiment is
By limiting the value of the constant 2N, which is the operation parameter in the first embodiment, to 2 ^M (that is, limiting to N = 2 ^{M −1} ), the inversion phase correction unit 500 a includes only the exclusive OR element 503. Has the advantage of being extremely simple.

The output of the inverted phase correction means 500a is input to a D-type flip-flop 404a, and the D-type flip-flop 404a is driven by a differential pulse signal output from the exclusive OR element 402. As described above, since the differential pulse signal has a rising edge at the rising and falling moments of the binary quantized received signal, the D-type flip-flop 404a is driven at the rising and falling moments of the binary quantized received signal. Will be. From the above, the output value of the D-type flip-flop 404a is set to μ (μ {0, 1,..., 2 ^M -1}), and the two at the moment when the binary quantized reception signal rises and the moment when it falls. The output values of the counter 403a modulo ^M are represented by β ₁ and β ₂ (β ₁ , β ₂ ∈ ｛0, 1,..., 2 ^M −
1｝), it is clear that the relationship given by the following equation holds between μ and β ₁ and β ₂ .

Μ = β ₁ or μ = β ₂ +2 ^M-1

Therefore, the phase difference の between the virtual phase reference signal and the binary quantized received signal is calculated by using the D type flip-flop 4
Similarly to the first embodiment, a relationship given by the following equation holds between the value μ of the output of 04a and the value μ of the output.

2πμ / 2 ^M ≤ψ <2π (μ + 1) / 2 ^M

This relationship is based on the value μ of the output of the D-type flip-flop 404a, which is the output of the phase comparison circuit 400a.
Indicates that the binary quantized received signal can be handled as a relative phase with reference to a virtual phase reference signal. This is evident with reference to FIGS. 8, 9 and 10. In this embodiment, similarly to the first embodiment,
Since the D-type flip-flop 404a is driven by the differentiated pulse signal having a rise at the rising and falling moments of the binary quantized reception signal, the relative phase signal which is the output of the phase detection circuit is compared with the conventional example. Update speed is doubled. This is illustrated in FIGS. 8 and 12, FIGS.
It is clear from comparing FIG. 13 with FIG.

Further, the binary quantized reception signal shown in FIG.
Is the same signal as the binary quantized reception signal A of FIG.
Is the output of the conventional phase detection circuit 200 shown in FIG.
The output A of the type flip-flop 202 becomes “7” →
In contrast to "9", the output of the D-type flip-flop 404a, which is the output of the phase detection circuit 400a of this embodiment shown in FIG. 9, is "7" → "8" → "9". Is changing. Similarly, the binary quantized received signal in FIG. 10 and the binary quantized received signal B in FIG. 13 are the same signal,
While output B of D-type flip-flop 202 shown in FIG. 13 changes from “9” to “7”, FIG.
The output of the D-type flip-flop 404a shown in FIG. 7 changes from “9” → “8” → “7”. That is, also in the present embodiment, as in the first embodiment, since the update speed of the relative phase signal output from the phase detection circuit is doubled as compared with the conventional example, the change in the value of the relative phase signal also changes more smoothly. Become.

The relative phase signal output from phase comparison circuit 400a is delayed by delay element 300 whose delay time is equal to one symbol period of the received signal. At the same time, the relative phase signal is also input to a subtractor 301 modulo 2π. 2π
Is subtracted from the relative phase signal by subtracting the relative phase signal delayed by one symbol period from the relative phase signal modulo 2π. Is output. This phase difference signal represents a phase transition during one symbol period of the received signal. The phase difference signal output from the subtractor 301 modulo 2π is input to the determiner 302. The determiner 302 outputs demodulated data corresponding to the value of the phase difference signal according to a predetermined rule for the correspondence between the phase difference signal and the demodulated data.

Embodiment 5 FIG. In the above embodiment, the case has been described where the modulation scheme of the received signal is the DPSK modulation scheme. However, other modulation schemes, for example, the MSK modulation scheme and the G
The MSK modulation method may be used. Further, in the above embodiment, the case where the constant M, which is the operation parameter of the phase detection circuit 400a, is M = 4 has been described.
May be a positive integer, for example, M = 5 or M = 6.

[0071]

As described above, the phase detection circuit according to the present invention
According to the path and phase detection method and the differential detection and demodulation apparatus including the same, the relative phase value of the binary quantized received signal can be updated twice per cycle of the binary quantized received signal. A phase detection circuit and a phase detection method with a high update speed, and a delay detection and demodulation device including the same can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an example of a configuration of a delay detection and demodulation device including a phase detection circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating an example of an operation of a delay element 401 and an exclusive OR element 402 according to the first embodiment of the present invention.

FIG. 3 is a timing chart illustrating an example of a relationship among an output of a counter 403, a virtual phase reference signal, a binary quantized reception signal, and a differential pulse signal according to the first embodiment of the present invention.

FIG. 4 is a timing chart illustrating an example of an operation of the phase detection circuit 400 according to the first embodiment of the present invention.

FIG. 5 is a timing chart illustrating an example of an operation of the phase detection circuit 400 according to the first embodiment of the present invention.

FIG. 6 is a timing chart illustrating an example of an operation of the phase detection circuit 400 according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating an example of a configuration of a delay detection and demodulation device including a phase detection circuit according to a fourth embodiment of the present invention.

FIG. 8 shows a phase detection circuit 400a according to a fourth embodiment of the present invention.
FIG. 5 is a timing chart showing an example of the operation of FIG.

FIG. 9 shows a phase detection circuit 400a according to a fourth embodiment of the present invention.
FIG. 5 is a timing chart showing an example of the operation of FIG.

FIG. 10 shows a phase detection circuit 400 according to a fourth embodiment of the present invention.
It is a timing chart figure which shows an example of operation | movement of a.

FIG. 11 is a configuration diagram illustrating a configuration of a differential detection and demodulation device including a phase detection circuit according to a conventional example.

FIG. 12 is a timing chart showing an example of the operation of the phase detection circuit 200 according to the conventional example.

FIG. 13 is a timing chart showing an example of the operation of the phase detection circuit 200 according to the conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 limiter amplifier 200 phase detector 201 counter 202 D-type flip-flop 300 delay element 301 subtractor 302 determiner 400, 400a phase detector 401 delay element 402 exclusive OR element 403, 403a counter 404, 404a D-type flip-flop 500 , 500a Inverting phase correcting means 501 Multiplier 502 Adder 503 Exclusive OR element 901 Half period detecting means (Step) 902 Phase reference signal generating means (Step) 903 Phase difference output means (Step)

Continuation of the front page (56) References JP-A-62-196921 (JP, A) JP-A-61-240706 (JP, A) JP-A-3-132907 (JP, A) JP-A-4-77153 (JP) , A) JP-A-3-188737 (JP, A) Proceedings of the Annual Conference of the Institute of Electronics, Information and Communication Engineers, 1990, Volume 2, p. 2-299 (1990-9-15) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 27/00-27/38

Claims (10)

(57) [Claims] 1. A phase detection circuit having the following elements: (a) a half-period detection means for inputting an input signal having a predetermined period and outputting a half-period detection signal every half period of the input signal; Phase reference signal generating means for generating a phase reference signal serving as a reference signal for detecting a phase based on a clock signal having a frequency of twice or more the frequency of the input signal; (c) generated by the phase reference signal generating means The phase reference signal to be input
At the time of change, the phase of the above phase reference signal is equivalent to the phase of a half cycle.
Is shifted, based on the half-cycle detection signal outputted by the half-cycle detection means, the every half cycle of the input signal
Phase difference output means for outputting a phase difference between the shifted phase reference signal and the input signal. 2. A delay element for delaying an input signal, a first exclusive OR element for generating an exclusive OR signal of an output signal of the delay element and the input signal,
A counter driven by a clock signal having a frequency substantially equal to N times (N is a positive integer), and a numerical value “0” or “N” in an output signal of the counter according to a value of an output signal of the delay element. Inverted phase correction means for outputting the added value, and a D-type flip-flop driven by an exclusive OR signal output from the exclusive OR element with an output signal of the inverted phase correction means as an input A phase detection circuit. 3. The inverting phase correcting means includes a multiplier for multiplying an output signal of the delay element by N times, and an adder for adding an output signal of the multiplier and an output signal of the counter. 3. The phase detection circuit according to claim 2, wherein: 4. The inverted phase correction means selects and outputs a numerical value “0” when the output signal of the delay element is a numerical value “0” and a numerical value “N” when the output signal is a numerical value “1”. 3. The phase detection circuit according to claim 2, further comprising a data selector, and an adder for adding an output signal of the data selector and an output signal of the counter. 5. An AND element for generating an AND signal of an output signal of the delay element and each bit of a numerical value “N”, an output signal of the AND element and the counter. 3. The phase detection circuit according to claim 2, further comprising an adder for adding the output signals of (1) and (2). 6. The counter according to claim 2, wherein the input signal comprises 2 ^M
Driven by a clock signal having a frequency substantially equal to (M is a positive integer) times, the inversion phase correcting means outputs an exclusive OR signal of the output signal of the delay element and the most significant bit of the output signal of the counter And a second exclusive-OR element that generates a signal obtained by removing a most significant bit from an output signal of the second exclusive-OR element and an output signal of the counter. 3. The phase detection circuit according to claim 2, wherein: 7. A quantizer for binary-quantizing a received signal,
7. The phase detection circuit according to claim 1, wherein the output signal of said quantizer is used as an input signal, and the output signal of said phase detection circuit is one of the received signals. A delay detection demodulator comprising: a delay element for delaying a symbol period; and a subtractor for subtracting an output signal of the delay element from an output signal of the phase detection circuit. 8. The following steps half period detection step of detecting a timing of a half cycle of the input signal from the phase detection method (a) an input signal having a reference signal for detecting the phase of (b) input signal Become
A phase reference signal generating step of generating a phase reference signal; (c) a phase reference generated in the phase reference signal generating step
A signal is input and a predetermined change is made for each cycle of the input signal.
Sometimes the phase of the phase reference signal is shifted by a half cycle
At the timing of the half cycle detected by the half cycle detection step , the input signal is shifted every half cycle.
A phase difference output step of outputting a phase difference between the phase reference signal and the input signal. 9. A phase detection circuit having the following elements : (a) An input signal having a predetermined period is input, and
A half-period detector that outputs a half-period detection signal for each half-period of the signal
With stages, the frequency of at least twice the frequency of the (b) said input signal
A reference signal that detects the phase based on the clock signal
2N (N is a positive integer, 2N is equivalent to one period of phase 2π
To generate a phase reference signal with a value modulo
Phase reference signal generating means, the phase generated by (c) the phase reference signal generating means
Input the reference signal and change the value of the above phase reference signal every cycle
Is corrected by adding a value N corresponding to a phase π of a half cycle to
The half-period detection signal output by the half-period detection means
Based on the corrected position every half cycle of the input signal.
Outputs the phase difference between the phase reference signal and the input signal.
Power means. 10. A phase detection method comprising the following steps: (a) timing of a half cycle of an input signal from an input signal;
Half period detection step of detecting a as a reference signal for detecting the phase of (b) input signal
2N (N is a positive integer, 2N is equivalent to one period of phase 2π)
To generate a phase reference signal with a value modulo
A reference signal generation step, (c) a phase reference generated in the phase reference signal generation step
Input a signal, and add the value of the phase reference signal
Correction to add the value N corresponding to the phase π of the cycle
At the timing of the half cycle detected by the
The corrected phase reference signal for each half cycle of the input signal.
A phase difference output step of outputting a phase difference of the input signal.