JPH05259742A - Phase detection circuit, delay detection demodulator and phase detection method - Google Patents

Abstract

PURPOSE:To obtain a phase detection circuit with a fast revision speed of a relative phase signal in which a relative phase of a binary quantized reception signal is revised twice per one period of the binary quantized reception signal. CONSTITUTION:A reception signal is binarized and quantized by a limiter amplifier 100 and becomes a differentiation pulse signal by a delay element 401 and an exclusive OR element 402 in a phase detection circuit 400. Simultaneously a delayed reception signal is inputted to a multiplier 501 in an inverted phase correction means 500 and added to an output of a counter 403 by an adder 502. A DFF 404 receiving a sum output is driven by a differentiation pulse signal being an output of the exclusive OR element 402 and a relative phase signal representing the relative phase of the binary quantized reception signal being an output of the phase detection circuit 400 is outputted. A delay element 300 delays the relative phase signal, and a subtractor 301 subtracts an output of the delay element 300 from the relative phase signal. A discriminator 302 decides demodulation data from the output of the subtractor 301 and outputs them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection demodulator in the field of wireless communication systems, and more particularly to a differential detection demodulator using a phase detection circuit and an improvement of the phase detection circuit used therein.

[0002]

2. Description of the Related Art A conventional differential detection demodulator using a phase detection circuit is described in, for example, the document "Digital intermediate frequency demodulation system".
(Tomita, Kasai, Matsuki, 1990 Annual Conference of the Institute of Electronics, Information and Communication Engineers, B-299). The prior art will be described below with reference to the drawings.

FIG. 11 is a block diagram showing the structure of a conventional differential detection demodulator having a phase detection circuit.
100 is a limiter amplifier, 200 is a phase detection circuit, 201
Is a counter modulo K (K is a positive integer), 202 is D
A type flip-flop, 300 is a delay element whose delay time is equal to one symbol period of the received signal, 301 is a subtractor modulo 2π, and 302 is a determiner.

Next, the operation will be described. The received signal, which is a differential phase shift keying (hereinafter abbreviated as DPSK) modulated signal, becomes a rectangular waveform signal of constant amplitude by the limiter amplifier 100. That is, the limiter amplifier 100 acts as a quantizer that binary-quantizes the received signal. Hereinafter, it is assumed that the received signal is quantized by the limiter amplifier 100 into binary values of logic “0” and logic “1”.

On the other hand, a counter 201 modulo K (K is a positive integer) in the phase detection circuit 200 has a clock signal (hereinafter abbreviated as "driving clock") having a frequency approximately equal to K times the received signal. Driven by. The output of the counter 201 modulo K is the D-type flip-flop 2
It is input to 02. The D type flip-flop 202 is driven by the binary quantized received signal output from the limiter amplifier 100. With such a configuration, the output signal of the D-type flip-flop 202, which is the output of the phase detection circuit 200, takes a value indicating the relative phase of the binary quantized reception signal.

This will be described with reference to the drawings. 12 and 13 show the phase detection circuit 200 when K = 16.
5 is a timing chart showing an example of the operation of FIG. 12
Also, in FIG. 13, a signal obtained by dividing the drive clock of the counter 201 modulo K (16 in this case) by K (that is, by 16) is shown as a virtual phase reference signal. This virtual phase reference signal rises at the moment when the output of the counter 201 modulo K becomes "0", and "K /
It is a signal that falls at the moment when it becomes 2 "(that is," 8 "). Here, the period of the drive clock of the counter 201 modulo K is T, and the period of the virtual phase reference signal is T _r.
Then, it is clear that the relation given by the following equation holds.

T _r = KT

From this, the phase difference ψ between the virtual phase reference signal and the binary quantized received signal is 2
If the rising time difference from the value-quantized received signal is τ,
It is given by the following formula.

Ψ = 2πτ / T _r = 2πτ / (KT)

On the other hand, as is clear from FIG. 12, the output of the counter 201 modulo K at the moment when the binary quantized received signal rises is the virtual phase reference signal and the binary quantized received signal. The rising time difference τ is an integer value obtained by rounding down the fractional part of the value normalized by the driving clock cycle T of the counter 201 whose modulus is K.

Therefore, D driven by the binary quantized received signal with the output of the counter 201 modulo K as input
The output of the type flip-flop 202 is always below the decimal point of the value obtained by normalizing the rising time difference τ between the virtual phase reference signal and the binary quantized received signal with the drive clock cycle T of the counter 201 whose modulus is K. Takes a rounded down integer value. That is, if the value of the output of the D-type flip-flop 202 is μ (με {0, 1, ..., K−1}),
The relationship represented by the following equation is established between μ, T, and τ.

Μ ≦ τ / T <(μ + 1)

From the above, the relationship given by the following equation is not established between the phase difference ψ between the virtual phase reference signal and the binary quantized received signal and the value μ of the output of the D type flip-flop 202. it is obvious.

2πμ / K ≦ ψ <2π (μ + 1) / K

In this relationship, the value μ of the output of the D type flip-flop 202, which is the output of the phase detection circuit 200, is
It is shown that it can be treated as the relative phase of the binary quantized received signal with reference to the virtual phase reference signal.
For example, in FIG. 12, a virtual phase reference signal and 2
Since the relative phase of the value-quantized reception signal is always constant, the D-type flip-flop 202 always outputs a constant value "8". Further, FIG. 13 shows a virtual phase reference signal and
When the relative phase of the value-quantized received signal changes, 2
When the value-quantized received signal A is input, the output of the D-type flip-flop 202 changes from "7" to "9". When the binary quantized received signal B is input, D
The output of the type flip-flop 202 changes from "9" to "7". In either case, it is clear that the output of the D type flip-flop 202 changes according to the relative phase of the virtual phase reference signal and the binary quantized received signal.

The relative phase signal output from the phase detection circuit 200 is delayed by the delay element 300 whose delay time is equal to one symbol period of the received signal. At the same time, the relative phase signal is also input to the subtractor 301 modulo 2π. The relative phase signal delayed by one symbol period output from the delay element 300 is also input to the subtractor 301 modulo 2π,
A phase difference signal, which is a value obtained by subtracting the relative phase signal delayed by one symbol period from the relative phase signal by 2 mod, is output. This phase difference signal represents a phase transition during one symbol period of the received signal. Subtractor 30 modulo 2π
The phase difference signal output from 1 is input to the determiner 302. The determiner 302 outputs the demodulation data according to the value of the phase difference signal according to a predetermined correspondence rule between the phase difference signal and the demodulation data.

[0017]

As described above, the conventional phase detection circuit drives the D type flip-flop only at the rising edge of the binary quantized received signal. For this reason,
The relative phase signal output from the phase detection circuit is updated only every one cycle of the binary quantized received signal. However, 2
The relative phase of the value-quantized reception signal can be measured not only at the rising edge of the binary-quantized reception signal but also at the falling edge. Therefore, in principle, although the value of the relative phase of the binary quantized received signal can be updated twice per cycle of the binary quantized received signal, the conventional phase detection circuit can only update once per cycle. There is a problem that the update is not performed, that is, the update rate of the relative phase signal is slow.

The present invention has been made to solve the above problems, and the value of the relative phase of a binary quantized received signal can be updated twice per cycle of the binary quantized received signal.
An object of the present invention is to obtain a phase detection circuit having a high update rate of a relative phase signal, a phase detection method, and a differential detection demodulation device including the same.

[0019]

A phase detection circuit according to the present invention is, for example, a delay element for delaying an input signal, and an exclusive OR signal of an output signal of the delay element and the input signal. One exclusive OR element, a counter driven by a clock signal having a frequency approximately equal to 2N (N is a positive integer) times the input signal, and the counter according to the value of the output signal of the delay element Of the exclusive OR which is an output of the exclusive OR element with the output signal of the inverted phase correction means as an input. A D-type flip-flop driven by a signal, and has the following elements. (A) A half cycle detecting means for inputting an input signal having a predetermined cycle and outputting a half cycle detection signal for each half cycle of the input signal, (b) having a frequency which is at least twice the frequency of the input signal. Phase reference signal generating means for generating a phase reference signal which is a reference signal for detecting a phase based on a clock signal,
(C) The phase reference signal generated by the phase reference generating means is corrected in half cycle units of the input signal, and the corrected phase reference signal and the half cycle output by the half cycle detecting means. Phase difference output means for outputting the phase difference between the phase reference signal and the half cycle detection signal for each half cycle of the input signal based on the cycle detection signal.

Further, the differential detection demodulator according to the present invention is
The phase detection circuit, the delay element for delaying the output signal of the phase detection circuit by one symbol period of the received signal, and the subtractor for subtracting the output signal of the delay element from the output signal of the phase detection circuit. It is characterized by.

The phase detection method according to the present invention has the following steps. (A) Half-cycle detection step of detecting the half-cycle timing of the input signal from the input signal, (b) Phase reference signal generation step of generating a reference signal for detecting the phase of the input signal, (c) Half-cycle A phase difference output step of outputting the phase difference between the reference signal generated in the reference signal generation step and the input signal at the half cycle timing detected in the detection step.

[0022]

In the phase detection circuit (or phase detection method) according to the present invention, for example, the half-cycle detecting means (process) using the delay element and the first exclusive OR element detects the rise and fall of the input signal. It acts as a differentiating circuit that generates a pulse signal at an instant and detects a half cycle of the input signal. Also, a phase difference output means (process) including an inverted phase correction means
The inverting phase correction means corrects the output of the counter by the numerical value "N" corresponding to the phase π at the moment when the input signal falls so that the phase reference signal can be compared with the input signal every half cycle. Then, the phase difference between the corrected phase reference signal and the input signal is output every half cycle.

Since the differential detection demodulator according to the present invention is provided with the phase detection circuit described above, the relative phase value of the binary quantized received signal can be updated twice per cycle of the binary quantized received signal. Therefore, the update speed of the relative phase signal becomes faster.

[0024]

EXAMPLES Example 1. Example 1 will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an example of the configuration of a differential detection demodulator including a phase detection circuit according to the first embodiment. In the figure, 400 is a phase detection circuit, 401 is a delay element, and 402 is an exclusive OR element. , 403 is a counter modulo 2N (N is a positive integer), 404 is a D-type flip-flop, 500 is an inversion phase correction means constituted by a multiplier 501 and an adder 502 modulo 2N, which will be described later, 501 Is a multiplier and 502 is an adder modulo 2N. Reference numeral 901 denotes a half cycle detecting means for inputting an input signal having a predetermined cycle and outputting a half cycle detection signal for each half cycle of the input signal, or a half cycle for detecting the timing of the half cycle of the input signal from the input signal. In a detecting step 902, phase reference signal generating means for generating a phase reference signal serving as a reference signal for detecting a phase based on a clock signal having a frequency not less than twice the frequency of the input signal, or detecting the input signal. A phase reference signal generating step for generating a reference signal for generating a phase reference signal for correcting the phase reference signal generated by the phase reference generating means in units of half cycle of the input signal, and the phase reference signal thus corrected. The phase difference between the phase reference signal and the half cycle detection signal is output for each half cycle of the input signal based on the signal and the half cycle detection signal output by the half cycle detection means. Quadrature means or,
It is a phase difference output step of outputting a phase difference between the reference signal generated in the reference signal generation step and the input signal at the timing of the half cycle detected in the half cycle detection step. Further, the same or corresponding portions as those in FIG. 11 are designated by the same reference numerals and the description thereof will be omitted.

Next, the operation will be described. In FIG. 1, a received signal which is a DPSK modulated signal is a limiter amplifier 1
00, a rectangular waveform signal having a constant amplitude is obtained. That is, the limiter amplifier 100 acts as a quantizer that binary-quantizes the received signal. Hereinafter, it is assumed that the received signal is quantized by the limiter amplifier 100 into binary values of logic “0” and logic “1”.

The binary quantized received signal output from the limiter amplifier 100 is input to the phase detection circuit 400. In the phase detection circuit 400, the binary quantized received signal is input to the delay element 401. The delay time of the delay element 401 is shorter than 1/2 cycle of the binary quantized received signal. The delayed reception signal output from the delay element 401 is input to the exclusive OR element 402. On the other hand, the binary quantized reception signal is also input to the exclusive OR element 402, and the exclusive OR operation with the delayed reception signal is performed. With such a configuration, 2
A pulse signal (hereinafter referred to as a differential pulse signal) that rises at the instants of rising and falling of the value-quantized reception signal is output. This will be described with reference to the drawings. Figure 2
6 is a timing chart showing an example of operations of the delay element 401 and the exclusive OR element 402. As shown in FIG. 2, by setting the delay time of the delay element 401, that is, the delay time of the delayed reception signal with respect to the binary quantized reception signal to be shorter than 1/2 cycle of the binary quantized reception signal, exclusive It is clear that the differential pulse signal output from the OR element 402 has a rising edge at the rising and falling moments of the binary quantized received signal.

On the other hand, in the phase detection circuit 400, 2
The counter 403 whose modulus is N (N is a positive integer) is driven by a clock signal (hereinafter, abbreviated as “driving clock”) having a frequency approximately equal to 2N times the received signal. Here, as in the conventional example, when the output of the counter 403 modulo 2N, which is obtained by dividing the driving clock of the counter 403 modulo 2N by 2N, rises to "N", the output rises to "N". When the signal falling at the moment when is considered as a virtual phase reference signal, the output of the counter 403 modulo 2N indicates the phase of this virtual phase reference signal. That is, if the value of the output of the counter 403 modulo 2N is α (αε {0, 1, ..., 2N−1}) when the phase of the virtual phase reference signal is θ, then θ The relationship given by the following equation is established between and α.

Πα / N ≦ ψ <π (α + 1) / N

Therefore, the value of the output of the counter 403 modulo 2N at the moment when the differential pulse signal which is the output of the exclusive OR element 402 rises is a virtual value at the moment when the binary quantized received signal rises and falls. The phase of the phase reference signal is indicated. The absolute phase of the binary quantized received signal at the moment when the binary quantized received signal falls is π. Therefore, it is 2 at the moment when the binary quantized received signal falls.
If the value of the output of the counter 403 modulo N is corrected by the numerical value “N” corresponding to the phase π, the virtual quantization at the moment when the binary quantized received signal falls, which cannot be obtained in the conventional example. It is possible to obtain the relative phase of the binary quantized received signal with reference to the conventional phase reference signal.

This will be described with reference to the drawings. Figure 3
When N = 8, the output of the counter 403 modulo 2N (16 in this case), a virtual phase reference signal,
7 is a timing chart showing an example of the relationship between a binary quantized received signal and a differential pulse signal. Here, when the cycle of the drive clock of the counter 403 modulo 2N is T and the cycle of the virtual phase reference signal is T _r , it is clear that the relationship given by the following equation holds.

T _r = 2NT

From this, the phase difference ψ between the virtual phase reference signal and the binary quantized received signal is 2
When the time difference between the rising edge and the falling edge of the quantized received signal is τ, it is given by the following equation.

Ψ = 2πτ / T _r = πτ / (NT)

On the other hand, as is apparent from FIG. 3, the value of the output of the counter 403 modulo 2N is β ₁ (β ₁ ε {0, 1, ..., 2 at the moment when the binary quantized received signal rises.
N-1}), β ₁ is a virtual phase reference signal and 2
The rising time difference τ from the value quantized received signal is an integer value obtained by rounding down the fractional part of the value normalized by the driving clock cycle T of the counter 403 whose modulus is 2N. That is,
The relationship given by the following equation holds between β ₁ , T, and τ.

Β ₁ ≤τ / T <(β ₁ +1)

Further, the value of the output of the counter 403 modulo 2N is "N" (8 in the case of FIG. 3) corresponding to the phase π at the instant when the virtual phase reference signal falls.
The value of the output of the counter 403 modulo 2N at the moment when the binary quantized received signal falls is β ₂ (β ₂ ε {0, 1,
, 2N-1}), β ₂ is the fall time difference τ between the virtual phase reference signal and the binary quantized received signal, which is 2N.
Is a value obtained by adding a numerical value “N” modulo 2N to an integer value obtained by rounding down the fractional part of the value normalized by the driving clock cycle T of the counter 403 modulo. From this, β 2,
The relationship given by the following equation is established between T and τ.

(Β ₂ −N) ≦ τ / T <(β ₂ −N + 1)

However, the subtraction in this case is a subtraction modulo 2N. However, reducing N modulo 2N is equivalent to adding N modulo 2N. Therefore, the relationship given by the following equation is established between β ₂ , T, and τ.

(Β ₂ + N) ≦ τ / T <(β ₂ + N + 1)

From the above, the phase difference ψ between the virtual phase reference signal and the binary quantized received signal, the output value β ₁ of the counter 403 modulo 2N at the moment when the binary quantized received signal rises, and 2N at the moment when the binary quantized received signal falls
It is clear that the relationship given by the following equation holds between the values β ₂ of the output of the counter 403 modulo.

Πβ ₁ / N ≦ ψ <π (β ₁ +1) / N π (β ₂ + N) / N ≦ ψ <π (β ₂ + N + 1) / N

This relationship is represented by the value β of the output of the counter 403 modulo 2N at the moment when the binary quantized received signal rises.
₁ and the value obtained by adding the numerical value “N” to the output value β ₂ of the counter 403 modulo 2N at the moment when the binary quantized received signal falls, modulo 2N, and the numerical value “N” It can be treated as a relative phase of the binary quantized received signal. In other words, the value of the output of the counter 403 modulo 2N is a numerical value “0” at the moment when the binary quantized received signal rises, and a numerical value “0” at the moment when the binary quantized received signal falls. By adding N ″, the relative phase of the binary quantized received signal can be known.

The inverted phase correction means 500 performs the above correction on the output value of the counter 403 modulo 2N. That is, the inverting phase correction means 500 receives the output of the counter 403 modulo 2N as an input, and inputs a numerical value "0" at the moment when the binary quantized received signal rises and the binary quantized received signal At the moment of falling, a value obtained by adding the numerical value "N" is output. Inversion phase correction means 50 will be described below with reference to the drawings.
The operating principle of 0 will be described. 4, FIG. 5, and FIG. 6 respectively show N = 8 (that is, 2N = 16),
6 is a timing chart showing an example of the operation of the phase detection circuit 400. As is clear from these figures, the delay element 4
The value of the delayed reception signal that is the output of 01 is always "0" at the moment when the binary quantized reception signal rises, and
It is always "1" at the moment when the value-quantized received signal falls. Therefore, the multiplier 501 in the inverted phase correction means 500
Thus, by multiplying the value of the delayed reception signal output from the delay element 401 by N, the multiplier 501 always outputs “0” at the moment when the binary quantized reception signal rises,
Further, at the moment when the binary quantized received signal falls, a signal which is always "N" is output. Therefore, the counter 403 modulo 2N is added by the adder 502 modulo 2N.
The output of the adder 502 modulo 2N, which is the output of the inverting phase correction means 500, is modulo 2N at the moment when the binary quantized received signal rises, by adding the output of 1 to the output of the multiplier 501. The value of the output of the counter 403 is set to a numerical value “0”, and at the moment when the binary quantized received signal falls, the value of the output of the counter 403 is set to a value of 2N. Takes the value added.

The output of the inverted phase correction means 500 is 2N.
The output of the adder 502 modulo is input to the D-type flip-flop 404. The D type flip-flop 404 is driven by the differential pulse signal which is the output of the exclusive OR element 402. As described above, since the differential pulse signal has a rising edge at the rising and falling moments of the binary quantized received signal, the D type flip-flop 4
04 is driven at the rising and falling moments of the binary quantized received signal. From the above, assuming that the output value of the D-type flip-flop 404 is μ, the output value β ₁ of the counter 403 modulo 2N at the moment when the binary quantized received signal rises, and the binary quantization It is clear that the relationship given by the following equation is established between the output values β ₂ of the counter 403 modulo 2N at the moment when the received signal falls.

Μ = β ₁ or μ = β ₂ + N

Therefore, the phase difference ψ between the virtual phase reference signal and the binary quantized received signal, and the D type flip-flop 4
The relation given by the following equation is established between the output value of 04 and μ.

Πμ / N ≦ ψ <π (μ + 1) / N

In this relationship, the value μ of the output of the D type flip-flop 404, which is the output of the phase comparison circuit 400, is
It is shown that it can be treated as the relative phase of the binary quantized received signal with reference to the virtual phase reference signal.
This is apparent with reference to FIGS. 4, 5 and 6. In the conventional example, the output of the D-type flip-flop 202 indicating the relative phase of the binary quantized received signal is updated only once per cycle of the binary quantized received signal. Since the D type flip-flop 404 is driven by the differential pulse signal having the rising at the rising and falling moments of the value-quantized received signal, the output of the D-type flip-flop 404 indicating the relative phase of the binary quantized received signal. Is updated twice per cycle of the binary quantized received signal. That is, in this embodiment, the update rate of the relative phase signal, which is the output of the phase detection circuit, is doubled as compared with the conventional example. This is clear by comparing FIG. 4 with FIG. 12, FIG. 5 and FIG. 6 with FIG.

Further, the binary quantized received signal of FIG.
Although the binary quantized received signal A in FIG.
The output D of the conventional phase detection circuit 200 shown in FIG.
The output A of the type flip-flop 202 is “7” →
While changing from “9”, the output of the D-type flip-flop 404, which is the output of the phase detection circuit 400 of the present embodiment shown in FIG. 5, is “7” → “8” → “9”. Is changing. Similarly, the binary quantized received signal of FIG.
Although the binary quantized received signal B in FIG.
The output B of the D-type flip-flop 202 shown in FIG. 6 changes from “9” to “7”, while the output of the D-type flip-flop 404 shown in FIG.
It has changed from "8" to "7". That is, in this embodiment, the update rate of the relative phase signal output from the phase detection circuit is doubled as compared with the conventional example, so that the change in the value of the relative phase signal becomes smoother.

The relative phase signal output from the phase comparison circuit 400 is delayed by the delay element 300 whose delay time is equal to one symbol period of the received signal. At the same time, the relative phase signal is also input to the subtractor 301 modulo 2π. The relative phase signal delayed by one symbol period output from the delay element 300 is also input to the subtractor 301 modulo 2π,
A phase difference signal, which is a value obtained by subtracting the relative phase signal delayed by one symbol period from the relative phase signal by 2 mod, is output. This phase difference signal represents a phase transition during one symbol period of the received signal. Subtractor 30 modulo 2π
The phase difference signal output from 1 is input to the determiner 302. The determiner 302 outputs the demodulation data according to the value of the phase difference signal according to a predetermined correspondence rule between the phase difference signal and the demodulation data.

Example 2. In the above embodiment, the case where the multiplier is provided as a constituent element of the inverting phase correction means has been described. However, when a numerical value "0" is input, the numerical value "0" and the numerical value "1" are input. If the input is, it outputs any numerical value "N". For example, if the numerical value "0" is input as the data selection signal, the numerical value "0" is input.
And a data selector that selects and outputs the numerical value “N” when the numerical value “1” is input, and a logical product element that logically ANDs the input signal and each bit of the numerical value “N”. Good.

Example 3. Further, in the above embodiment, the case where the modulation system of the received signal is the DPSK modulation system has been described, but other modulation systems such as the MSK modulation system and the G modulation system are used.
The MSK modulation method or the like may be used. Furthermore, in the above embodiment, the case where the constant N, which is an operation parameter of the phase detection circuit 400, is N = 8 has been described.
May be a positive integer, for example N = 16 or N = 32.
May be

Example 4. Next, a second embodiment will be described with reference to the drawings. FIG. 7 is a configuration diagram showing an example of the configuration of the differential detection demodulator including the phase detection circuit according to the second embodiment. In the figure, 400a is a phase detection circuit and 403a is 2 ^M (M is a positive integer). Modulo counter, 404a is a D-type flip-flop, 500a is an inverting phase correction means constituted by an exclusive OR element 503 described later, 5
03 is an exclusive OR element. 1 and 11
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

Next, the operation will be described. In FIG. 7, the received signal, which is a DPSK modulated signal, becomes a signal having a rectangular waveform with a constant amplitude by the limiter amplifier 100, as in the first embodiment. That is, the limiter amplifier 100 acts as a quantizer that binary-quantizes the received signal. Hereinafter, it is assumed that the received signal is quantized by the limiter amplifier 100 into binary values of logic “0” and logic “1”.

The binary quantized received signal output from the limiter amplifier 100 is input to the phase detection circuit 400a. The binary quantized received signal is input to the delay element 401 in the phase detection circuit 400a. The delay time of the delay element 401 is shorter than 1/2 cycle of the binary quantized received signal. The delayed reception signal output from the delay element 401 is input to the exclusive OR element 402. On the other hand, the binary quantized reception signal is also input to the exclusive OR element 402, and the exclusive OR operation with the delayed reception signal is performed. Similar to the first embodiment, with such a configuration, a pulse signal (hereinafter referred to as a differential pulse signal) rising from the exclusive OR element 402 at the rising and falling moments of the binary quantized reception signal. Is output.

On the other hand, in the phase detection circuit 400a,
The counter 403a modulo 2 ^M (M is a positive integer) is
It is driven by a clock signal (hereinafter abbreviated as “driving clock”) having a frequency approximately equal to 2 ^M times the received signal. Here, in the same manner as in Example 1, 2 ^M obtained by 2 ^M division drive clock of the counter 403a modulo, the output of the counter 403a which of 2 ^M modulo rises the moment becomes "0" , If the signal falling at the moment when it becomes "2 ^M-1 " is considered as a virtual phase reference signal, 2
The output of the counter 403a modulo ^M indicates the phase of this virtual phase reference signal. That is, when the phase of the virtual phase reference signal is θ, the output value of the counter 403a modulo 2 ^M is α (α∈ {0, 1,
, 2 ^M -1}), the relationship given by the following equation holds between θ and α.

2πα / 2 ^M ≤ψ <2π (α + 1) / 2 ^M

Therefore, the value of the output of the counter 403a modulo 2 ^M at the moment when the differential pulse signal which is the output of the exclusive OR element 402 rises is the value at the moment when the binary quantized received signal rises and falls. It indicates the phase of the virtual phase reference signal. The absolute phase of the binary quantized received signal at the moment when the binary quantized received signal falls is π
Is. Therefore, if the value of the output of the counter 403a modulo 2 ^M at the moment when the binary quantized received signal falls is corrected by the numerical value “2 ^M−1 ” corresponding to the phase π, the first embodiment
Similarly to, the relative phase of the binary quantized received signal can be obtained at the moment when the binary quantized received signal falls with reference to the virtual phase reference signal.

The inverted phase correction means 500a performs the above correction on the output value of the counter 403a modulo 2 ^M.
That is, the inverting phase correcting means 500a receives the output of the counter 403a modulo 2 ^M as an input, similarly to the inverting phase correcting means 500 of the first embodiment, and receives a numerical value at the moment when the binary quantized received signal rises. A value obtained by adding "0" and a numerical value "2 ^M-1 " at the moment when the binary quantized received signal falls is output. Hereinafter, the operation principle of the inverted phase correction means 500a will be described with reference to the drawings.

In FIGS. 8, 9 and 10, M =
4 is a timing chart showing an example of the operation of the phase detection circuit 400a when 4 (that is, 2 ^M = 16). Now, the number of bits of the output of the counter 403a modulo 2 ^M is obviously M bits, and the most significant bit (hereinafter, abbreviated as MSB) represents the digit of the numerical value “2 ^M-1 ”. .. Therefore, the counter 403a modulo 2 ^M
The output of the numerical adding "2 ^M-1" a of 2 ^M modulo is the output of the counter 403a which of 2 ^M modulo MSB
Is equivalent to logically inverting. That is, at the output of the counter 403a modulo 2 ^M , the numerical value "0" is set at the moment when the binary quantized received signal rises, and the numerical value "2 ^M- " is set at the moment when the binary quantized received signal falls. ^The value obtained by adding ¹ "is the MS of the output of the counter 403a modulo 2 ^M.
The logic of B is not logically inverted at the moment when the binary quantized received signal rises, and is logically inverted at the moment when the binary quantized received signal falls.

On the other hand, as is clear from FIGS. 8, 9 and 10, the value of the delayed reception signal which is the output of the delay element 401 is always "0" at the moment when the binary quantized reception signal rises. It is always "1" at the moment when the binary quantized received signal falls. Therefore, the exclusive OR element 503 in the inverting phase correction means 500a generates an exclusive OR signal of the delayed reception signal output from the delay element 401 and the MSB of the output of the counter 403a modulo 2 ^M , A signal obtained by synthesizing this with a lower bit (1st bit to M−1th bit) of the counter 403a modulo 2 ^M as a new MSB is a counter 403 modulo 2 ^M.
The MSB of the output of a is not logically inverted at the moment when the binary quantized received signal rises, and is logically inverted at the moment when the binary quantized received signal falls. That is,
The counter 40 modulo 2 ^M with the exclusive OR element 503 being the output of the inverting phase correction means 500a as the MSB.
The signal combined with the lower bit of 3a has a numerical value "0" at the output of the counter 403a modulo 2 ^M and the binary quantized received signal falls at the moment when the binary quantized received signal rises. At the moment, the value is the sum of the numerical values "2 ^M-1 ".

As described above, the phase detection circuit of this embodiment is
By limiting the value of the constant 2N, which is the operation parameter in the first embodiment, to 2 ^M (that is, N = 2 ^{M −1} ), the inverting phase correction means 500 a configures only the exclusive OR element 503 as a constituent element. It has the advantage of being extremely simple.

The output of the inverting phase correction means 500a is input to the D type flip-flop 404a, and the D type flip-flop 404a is driven by the differential pulse signal which is the output of the exclusive OR element 402. As described above, since the differential pulse signal has the rising edges at the rising and falling moments of the binary quantized received signal, the D type flip-flop 404a is driven at the rising and falling instants of the binary quantized received signal. Will be. From the above, it is assumed that the value of the output of the D type flip-flop 404a is μ (με {0, 1, ..., 2 ^M −1}), and the binary quantized received signal rises and falls at 2 times. The output values of the counter 403a modulo ^M are β ₁ and β ₂ (β ₁ , β ₂ ε {0, 1, ..., 2 ^M −
1}), it is clear that the relationship given by the following equation holds between μ and β ₁ and β ₂ .

Μ = β ₁ or μ = β ₂ +2 ^M-1

Therefore, the phase difference ψ between the virtual phase reference signal and the binary quantized received signal, and the D type flip-flop 4
Similar to the first embodiment, the relationship given by the following equation is established between the output value μ of 04a and the output value μ.

2πμ / 2 ^M ≤ψ <2π (μ + 1) / 2 ^M

This relationship is based on the value μ of the output of the D type flip-flop 404a which is the output of the phase comparison circuit 400a.
Indicates that it can be treated as the relative phase of the binary quantized received signal with reference to the virtual phase reference signal. This is clear with reference to FIGS. 8, 9 and 10. In addition, in the present embodiment, as in the first embodiment,
Since the D-type flip-flop 404a is driven by the differential pulse signal having the rising edges at the rising and falling moments of the binary quantized received signal, the relative phase signal output from the phase detection circuit is different from that of the conventional example. Update speed doubles. This is shown in FIGS. 8 and 12, 9 and 10.
It is clear by comparing FIG.

Further, the binary quantized received signal of FIG.
Although the binary quantized received signal A in FIG.
The output D of the conventional phase detection circuit 200 shown in FIG.
The output A of the type flip-flop 202 is “7” →
The output of the D-type flip-flop 404a, which is the output of the phase detection circuit 400a of the present embodiment shown in FIG. 9, changes from “7” → “8” → “9”, while it changes to “9”. Is changing. Similarly, the binary quantized received signal of FIG. 10 and the binary quantized received signal B of FIG. 13 are the same signal,
While the output B of the D-type flip-flop 202 shown in FIG. 13 changes from “9” to “7”, FIG.
The output of the D type flip-flop 404a shown in FIG. 4 changes from "9" to "8" to "7". That is, also in the present embodiment, as in the first embodiment, the relative phase signal output from the phase detection circuit is doubled as compared with the conventional example, so that the change in the value of the relative phase signal is smoother. Become.

The relative phase signal output from the phase comparison circuit 400a is delayed by the delay element 300 whose delay time is equal to one symbol period of the received signal. At the same time, the relative phase signal is also input to the subtractor 301 modulo 2π. 2π
The relative phase signal delayed by one symbol period output from the delay element 300 is also input to the subtractor 301 modulo the value obtained by subtracting the relative phase signal delayed by one symbol period from the relative phase signal by 2π. , The phase difference signal is output. This phase difference signal represents a phase transition during one symbol period of the received signal. The phase difference signal output from the subtractor modulo 2π is input to the determiner 302. The determiner 302 outputs the demodulation data according to the value of the phase difference signal according to a predetermined correspondence rule between the phase difference signal and the demodulation data.

Example 5. In the above embodiment, the case where the modulation system of the received signal is the DPSK modulation system has been described, but another modulation system, for example, the MSK modulation system or G
The MSK modulation method or the like may be used. In the above embodiment, the case where the constant M, which is an operation parameter of the phase detection circuit 400a, is M = 4 has been described.
Is a positive integer, and may be M = 5 or M = 6, for example.

[0071]

As described above, according to the phase detection circuit and the differential detection demodulator provided with the phase detection circuit according to the present invention, the value of the relative phase of the binary quantized received signal is converted into the binary quantized received signal. It is possible to obtain a phase detection circuit and a phase detection method that can update the relative phase signal at a high update rate that can be updated twice per cycle, and a delay detection demodulation device including the same.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a configuration of a differential detection demodulation device including a phase detection circuit according to a first exemplary embodiment of the present invention.

FIG. 2 is a timing chart showing an example of operations of the delay element 401 and the exclusive OR element 402 according to the first exemplary embodiment of the present invention.

FIG. 3 is a timing chart showing an example of the relationship between the output of the counter 403, the virtual phase reference signal, the binary quantized received signal, and the differential pulse signal according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing an example of the operation of the phase detection circuit 400 according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing an example of the operation of the phase detection circuit 400 according to the first embodiment of the present invention.

FIG. 6 is a timing chart showing an example of the operation of the phase detection circuit 400 according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram showing an example of a configuration of a differential detection demodulation device including a phase detection circuit according to a second embodiment of the present invention.

FIG. 8 is a phase detection circuit 400a according to a second embodiment of the present invention.
6 is a timing chart showing an example of the operation of FIG.

FIG. 9 is a phase detection circuit 400a according to a second embodiment of the present invention.
6 is a timing chart showing an example of the operation of FIG.

FIG. 10 is a phase detection circuit 400 according to a second embodiment of the present invention.
It is a timing chart figure which shows an example of operation | movement of a.

FIG. 11 is a configuration diagram showing a configuration of a differential detection demodulation device including a phase detection circuit according to a conventional example.

FIG. 12 is a timing chart showing an example of the operation of the conventional phase detection circuit 200.

FIG. 13 is a timing chart showing an example of the operation of the conventional phase detection circuit 200.

[Explanation of symbols]

 100 Limiter amplifier 200 Phase detection circuit 201 Counter 202 D type flip-flop 300 Delay element 301 Subtractor 302 Judgment device 400, 400a Phase detection circuit 401 Delay element 402 Exclusive OR element 403, 403a Counter 404, 404a D type flip-flop 500 , 500a Inverted phase correction means 501 Multiplier 502 Adder 503 Exclusive OR element 901 Half cycle detection means (step) 902 Phase reference signal generation means (step) 903 Phase difference output means (step)

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[Procedure amendment]

[Submission date] May 27, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0019

[Correction method] Change

[Correction content]

[0019]

A phase detection circuit according to the present invention is, for example, a delay element for delaying an input signal, and an exclusive OR signal of an output signal of the delay element and the input signal. One exclusive OR element, a counter driven by a clock signal having a frequency approximately equal to 2N (N is a positive integer) times the input signal, and the counter according to the value of the output signal of the delay element Of the exclusive OR which is an output of the exclusive OR element with the output signal of the inverted phase correction means as an input. A D-type flip-flop driven by a signal, and has the following elements. (A) A half cycle detecting means for inputting an input signal having a predetermined cycle and outputting a half cycle detection signal for each half cycle of the input signal, (b) having a frequency which is at least twice the frequency of the input signal. Phase reference signal generating means for generating a phase reference signal which is a reference signal for detecting a phase based on a clock signal,
(C) The phase reference signal generated by the phase reference generating means is corrected in half cycle units of the input signal, and the corrected phase reference signal and the half cycle output by the half cycle detecting means. Phase difference output means for outputting the phase difference between the phase reference signal and the input signal for each half cycle of the input signal based on the cycle detection signal.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction content]

[0024]

EXAMPLES Example 1. Example 1 will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an example of the configuration of a differential detection demodulator including a phase detection circuit according to the first embodiment. In the figure, 400 is a phase detection circuit, 401 is a delay element, and 402 is an exclusive OR element. , 403 is a counter modulo 2N (N is a positive integer), 404 is a D-type flip-flop, 500 is an inversion phase correction means constituted by a multiplier 501 and an adder 502 modulo 2N, which will be described later, 501 Is a multiplier and 502 is an adder modulo 2N. Reference numeral 901 denotes a half cycle detecting means for inputting an input signal having a predetermined cycle and outputting a half cycle detection signal for each half cycle of the input signal, or a half cycle for detecting the timing of the half cycle of the input signal from the input signal. The detecting step 902 is a phase reference signal generating means for generating a phase reference signal serving as a reference signal for detecting a phase based on a clock signal having a frequency not less than twice the frequency of the input signal, or an input signal.
A phase reference signal generating step of generating a reference signal for detecting the phase of the force signal , 903, correcting the phase reference signal generated by the phase reference generating means in half cycle units of the input signal, Based on the corrected phase reference signal and the half cycle detection signal output by the half cycle detection means, the phase reference signal and the phase reference signal are input for each half cycle of the input signal.
Phase difference output means for outputting the phase difference of the force signal , or
It is a phase difference output step of outputting a phase difference between the reference signal generated in the reference signal generation step and the input signal at the timing of the half cycle detected in the half cycle detection step. Further, the same or corresponding parts as those in FIG.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction content]

Example 4. Next, referring to FIG.
And explain. FIG. 7 is a block diagram showing an example of the configuration of a differential detection demodulator having a phase detection circuit according to the fourth embodiment . In the figure, 400a is a phase detection circuit and 403a is 2 ^M (M is a positive integer). Modulo counter, 404a is a D-type flip-flop, 500a is an inverting phase correction means constituted by an exclusive OR element 503 described later, 5
03 is an exclusive OR element. 1 and 11
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0071

[Correction method] Change

[Correction content]

[0071]

As described above, the phase detection circuit according to the present invention is
According to the path and phase detection method, and the differential detection demodulator provided with the same, the value of the relative phase of the binary quantized received signal can be updated twice per cycle of the binary quantized received signal. It is possible to obtain a phase detection circuit and a phase detection method having a high update speed, and a differential detection demodulation device including the same.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

FIG. 7 is a configuration diagram showing an example of a configuration of a differential detection demodulation device including a phase detection circuit according to a fourth exemplary embodiment of the present invention.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

FIG. 8 is a phase detection circuit 400a according to a fourth embodiment of the present invention.
6 is a timing chart showing an example of the operation of FIG.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] Figure 9

[Correction method] Change

[Correction content]

FIG. 9 is a phase detection circuit 400a according to a fourth embodiment of the present invention.
6 is a timing chart showing an example of the operation of FIG.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

FIG. 10 is a phase detection circuit 400 according to a fourth embodiment of the present invention.
It is a timing chart figure which shows an example of operation | movement of a. ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 15, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

Claims (8)

[Claims] 1. A phase detection circuit having the following elements: (a) a half cycle detecting means for inputting an input signal having a predetermined cycle and outputting a half cycle detection signal for each half cycle of the input signal, (b) Phase reference signal generating means for generating a phase reference signal which is a reference signal for detecting a phase based on a clock signal having a frequency which is twice or more the frequency of the input signal, (c) generated by the phase reference generating means. A half cycle of the input signal is corrected based on the corrected phase reference signal and the half cycle detection signal output by the half cycle detecting means. Phase difference output means for outputting the phase difference between the phase reference signal and the half-cycle detection signal for each. 2. A delay element for delaying an input signal, a first exclusive OR element for generating an exclusive OR signal of the output signal of the delay element and the input signal, and 2 of the input signals.
A counter driven by a clock signal having a frequency substantially equal to N (N is a positive integer) times, and a numerical value "0" or "N" in the output signal of the counter according to the value of the output signal of the delay element. An inverted phase correction means for outputting the added value and a D type flip-flop driven by an exclusive OR signal which is an output of the exclusive OR element with an output signal of the inverted phase correction means as an input are provided. Phase detection circuit characterized by. 3. The inverting phase correction means includes a multiplier that multiplies the output signal of the delay element by N, and an adder that adds the output signal of the multiplier and the output signal of the counter. The phase detection circuit according to claim 2. 4. The inverting phase correcting means selects and outputs a numerical value “0” when the output signal of the delay element is a numerical value “0” and a numerical value “N” when the numerical value is “1”. 3. The phase detection circuit according to claim 2, further comprising a data selector and an adder that adds an output signal of the data selector and an output signal of the counter. 5. The inversion phase correction means, a logical product element for generating a logical product signal of the output signal of the delay element and each bit of the numerical value “N”, the output signal of the logical product element and the counter. The phase detection circuit according to claim 2, further comprising an adder for adding the output signals of the above. 6. The counter is 2 ^{M of the} input signal.
Driven by a clock signal having a frequency approximately equal to (M is a positive integer) times, the inverting phase correction means is an exclusive OR signal of the output signal of the delay element and the most significant bit of the output signal of the counter. A second exclusive OR element for generating a signal, and is configured to output a signal obtained by removing the most significant bit from the output signal of the second exclusive OR element and the output signal of the counter. The phase detection circuit according to claim 2, wherein 7. A quantizer for binary-quantizing a received signal,
The phase detection circuit according to claim 1, 2, 3, 4, 5, or 6, wherein the output signal of the quantizer is used as an input signal, and the output signal of the phase detection circuit is used as a reception signal. A differential detection demodulator comprising: a delay element for delaying a symbol period; and a subtractor for subtracting the output signal of the delay element from the output signal of the phase detection circuit. 8. A phase detection method comprising the steps of: (a) a half cycle detection step of detecting a half cycle timing of the input signal from the input signal; and (b) a reference signal for detecting the phase of the input signal. A phase reference signal generation step of generating, (c) a phase difference output step of outputting a phase difference between the reference signal generated in the reference signal generation step and the input signal at the half cycle timing detected by the half cycle detection step.