JPH06274316A - Processing system for control signal - Google Patents

Abstract

PURPOSE:To provide the processing system of a control signal, by which precise, speedy and stable output can be obtained based on the expression of the complement of '2' or '1'. CONSTITUTION:In the system obtaining desired output by inputting the control signal by the expression of the complement of '2', the value of the lowest bit of a signal showing at least positive zero is set to be '1', and a signal which is set to be zero by digital quantization is converted into the control signal of a minimum +1 unit. In the case of the expression of the complement of '2', the control balance of a dynamic range is considerably improved and the state of the control signal=0 is removed. In the expression of the complement at least of '1', the value of the lowest bit of the signal showing at least positive zero among the control signals is set to be one, and the value of the lowest bit of the control signal showing at least negative zero is set to be zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal processing system, and more particularly to a control signal of a system for inputting a control signal represented by 2's or 1's complement to a control unit to obtain a desired control output from the control unit. Regarding the processing method of. The control signal represented by 2's or 1's complement is controlled based on the open control when the control signal is input to the input of the control unit to obtain the corresponding output signal from the output, or based on the error signal detected from the output signal of the control unit. Feedback control in the case of forming a signal and feeding it back to the control unit, or parameter control in the case where a parameter signal is input to the control unit as a control signal separately from the input and the control corresponding to the control unit is performed , Etc. are used.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram of a conventional QAM demodulation circuit, which circuit includes feedback control for reference carrier recovery. In the figure, 1 is 16
Demodulation circuit (DEM) of value QAM, 2 is A / D converter (A
/ D), 3 is a received signal identification circuit, 4 is a carrier recovery control circuit (DCR), 5 is a multiplier, 6 is a low-pass filter (LPF), 6 ₁ is a cumulative addition circuit (ADD), 7 is D /
A converter (D / A), 8 is a voltage controlled oscillator (VCO),
Reference numeral 9 is a clock recovery circuit (BTR).

The demodulation circuit 1 quadrature-detects the received signal IF with the carrier reproduction signal R _EF , and demodulates the baseband signals I and Q.
Is output. The clock recovery circuit 9 detects the transition point of the demodulated baseband signal I (or Q) that has been A / D converted, and is generated at the center of the eye of the sampling clock signal SCK and the demodulated baseband signals I and Q synchronized with this. Such a bit timing clock signal BTC and other necessary clock signals CK are generated. Then, the discrimination circuit 3 similarly demodulates the demodulated baseband signal I, which is A / D converted,
The received signal is identified and reproduced based on Q, and the received data RD is output.

On the other hand, the carrier wave reproduction control circuit 4 is the identification circuit 3
Z representing the code area (zone) from the above and said A / D
Reception based on the converted demodulated baseband signals I and Q
Signal IF and carrier reproduction signal R_EFDetect the phase difference between
And the corresponding phase error signal Eφ ₁Is output. This phase
Error signal Eφ₁Is weighted by g in the multiplier 5
It is output to the pass filter 6. With the low pass filter 6,
Cumulative addition circuit 6₁Weighted past multiple phases
Error signal gEφ₁Is added cumulatively to smooth the phase error
Then, the control signal V of the voltage controlled oscillator 8 is formed. This system
The control signal V is converted into an analog control voltage V by the D / A converter 7.
It is converted and output to the voltage controlled oscillator 8. And the voltage
The controlled oscillator 8 receives the received signal IF according to the control voltage V.
Carrier wave reproduction signal R_EFTo reduce the phase difference between
Control the oscillation frequency.

FIG. 9 is a diagram for explaining the problems of the prior art. In QAM demodulation, the orthogonal axes I and Q are divided into zones Z ₀₀ , Z _01, etc., and the center point of each zone is defined as code points H ₀₀ , H _01, etc. The actual received signal is reproduced offset from these code point by various disturbances, finally identified the code H ₀₀ if the received signal reproduced, for example, the zone Z _00. The same applies to zone Z ₀₁ . On the other hand, such identification In order to be accurate and code point H ₀₀ on the transmitting side and receiving side code point H ₀₀ is must always match. Therefore, the carrier recovery control circuit 4 detects the deviation of the received signals I and Q from the code point H ₀₀ , forms the phase error signal Eφ ₁ based on the deviation, and feeds this back to the voltage controlled oscillator 8 for feedback. The code points are matched by control. Therefore, in order to properly perform such feedback control, first, the error signal E
Accurate (precision) expression of the amount of error by _Q and E _I is essential.

Generally, a digital error signal represented by two's complement is used as the error signals E _Q and E _I. This is because an ordinary adder circuit and other arithmetic circuits are configured to be suitable for the two's complement representation. Conventionally, the phase error signal Eφ ₁ is formed directly from the error signals E _Q and E _I in the two's complement representation. However, the display of the error amount by the two's complement representation includes the following problems.

That is, for example, the Q-axis error signal E _Q is obtained by quantizing the Q-axis of the zone Z ₀₀ with a finite number of bits N (N = 4 for simplification of description) as shown in the figure. So, for example, even if E _Q = 0, this is zone Z ₀₀
It has a width of (1/2 ^N ) on one side.
Moreover, the error direction (sign) is S and the magnitude is A _{2 (MS B)}
If the error signal E _Q is expressed in the order of “S, A ₂ A ₁ A ₀ ” as ˜A _{0 (LSB)} , then in the two's complement representation, the error 0 = on the boundary of the code point H ₀₀ as shown in the figure. "10,000", error 1 = "0.001", error -1 = "1,111",
The error is expanded to −2 = “1,110”. That is, the symmetry of the positive and negative error signals is broken.

Therefore, for example, the carrier signal R_EFThe phase of
Eφ₁When the received signal is reproduced at point a by proceeding,
E_Q= -1, which is the code point H₀₀Toward the border of
Generate a unit feedback amount. But the carrier
Signal R_EFPhase is Eφ₁Due to the delay, the received signal is b
When played to a point, E_Q= 0, which is about the Q axis
Does not generate any feedback amount. And
Further carrier wave signal R_EFIs delayed and the received signal returns to point c.
When born, E_Q= 1, and only at this point
Code point H₀₀Toward the boundary of -1 unit feedback amount
Generate. As a result, the equilibrium of this feedback system
The point (convergence point) is the code point H₀₀From the border of _OF= 1/2 unit
Just offset. Similarly for the I axis
I_OF= Offset by 1/2 unit
The equilibrium point of the feedback system is the code point H₀₀To the position of ´
You will be fuset. Moreover, H₀₀Centered on ´
Error signal E within the rectangular area A_Q, E_ITogether
Since it will be 0, even if the equilibrium point is not determined in this range
Become.

The carrier reproduction control circuit 4 does not directly output the error signals E _Q and E _I as feedback signals, but further performs predetermined logic and arithmetic operations based on the error signals E _Q and E _I. The phase error signal Eφ ₁ is obtained and this is output as a feedback signal. However, even in this case, since the phase error signal Eφ ₁ is represented by the two's complement expression, if this phase error signal Eφ ₁ is directly used for the feedback control, the same problem as described above will be included.

Although not shown, in the one's complement representation, error 0 = “0000”, error 1 = “0,001”, error −0 = “1,111”, error −1 = “1,”. 110 "
And expand. Therefore, although there is symmetry between the positive and negative error signals in the 1's complement representation, the error amount is 0 for both the error 0 = “0000” and the error −0 = “1,111”. The convergence characteristic of such a feedback system becomes extremely slow, and its equilibrium point is around A ₀₀ with A 4
It becomes uncertain over the size of double.

[0011]

As described above, in the conventional control signal processing method, the control signal represented by 2's complement is used as it is as the feedback control signal. Therefore, the equilibrium point of the feedback control is not only offset. Or, the equilibrium point itself has a spread, which makes the feedback control inaccurate, slow, and unstable. Such a problem may occur in other open control, parameter control, etc.

It is an object of the present invention to provide a control signal processing system which can obtain a precise, quick and stable control output from a control unit on the basis of a control signal represented by 2 or 1's complement.

[0013]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the error signal processing method of the present invention (1) is the control signal processing method of a system in which a control signal represented by two's complement is input to a control unit to obtain a desired control output from the control unit. It is configured such that the value of the least significant bit of the control signal that represents at least positive zero among the signals is 1.

The error signal processing system of the present invention (4) is a system for processing a control signal of a system in which a control signal represented by 1's complement is input to a control unit to obtain a desired control output from the control unit. Of the control signals, the value of the least significant bit of the control signal representing at least positive zero is 1, and the value of the least significant bit of the control signal representing at least negative zero is 0.
It is configured to.

[0015]

FIG. 1A shows a typical feedback control system, and 20 is a control unit for converting an input signal IN into a desired (target) output signal OUT according to a control signal C.
Reference numeral 0 is a feedback control unit that compares the output signal OUT with the target value REF to form an error signal E, and 40 is an error signal E
Is a bit conversion unit that forms a control signal C by performing a predetermined bit conversion process on.

In the present invention (1), the feedback control section 30 forms the error signal E by the two's complement representation as shown in FIG. 1 (B). Then, the bit converter 40 converts the value of the least significant bit of the error signal E, which represents at least positive zero, of the error signal E into 1 to form the control signal C. By doing so, even if E = 0, it is converted to C = 1, and the feedback control in this case works downward so as to bring the output signal OUT closer to the target value REF. On the other hand, E
When −1, C = −1 as it is, and the feedback control in this case works upward so that the output signal OUT approaches the target value REF. Thus, in the vicinity of the equilibrium point REF, C = 1 and C = −1 are considered to occur with a probability of 1/2, respectively, so the actual equilibrium point is REF itself, which is an exact equilibrium point that does not have spread. Is. Moreover, since the control signal C never becomes 0, the target value RE
Quick and stable feedback control to F can be performed.

Preferably, the bit converter 40 is constructed so that the value of each least significant bit of the error signal E of the positive group of the control signal (however, the error signal E in this example) is set to 1. In this way, E = 0, 2, 4, and 6 are C = 1 and
Converted to 3, 5, 7. As a result, the sum of the positive dynamic range of E is 28, but the sum of the positive dynamic range of C after conversion is 32, which is the sum of the negative dynamic range of E (= the negative dynamic range of C). Approaching 36). Therefore, the imbalance between the positive and negative feedback amounts in the dynamic range is significantly eased.

Further, preferably, the bit conversion unit 40 is configured so that the value of each least significant bit of the control signal (however, the error signal E in this example) is set to 1. By doing this, E = 0,
2, 4, 6 are converted to C = 1, 3, 5, 7, and E = -2, -4, -6, -8 are C = -1, -3,-, respectively.
5, -7. As a result, the sum of the positive and negative dynamic ranges of C is ± 32, respectively, so that the imbalance between the positive and negative feedback amounts in the dynamic range is completely eliminated. Moreover, the bit conversion unit 40 in this case can be realized with an extremely simple configuration.

In the present invention (4), the feedback control section 30 forms the error signal E by the one's complement representation as shown in FIG. 1 (B). Then, the bit conversion unit 40 converts the value of the least significant bit of the error signal E representing at least positive zero of the error signal E into 1, and the value of the least significant bit of the error signal E representing at least negative zero. Is converted to 0 to form a control signal C.

In this way, even if E = 0, it is converted into C = 1, and the feedback control in this case is controlled by the output signal OU.
It works downward so that T approaches the target value REF. Further, even if E = −0, it is converted to C = −1, and the feedback control in this case works upward so as to bring the output signal OUT closer to the target value REF. Thus, in the vicinity of the equilibrium point REF, C = 1 and C = −1 are considered to occur with a probability of 1/2, respectively, so the actual equilibrium point is REF itself, which is an exact equilibrium point that does not have spread. Is.
Moreover, since the control signal C does not become ± 0, quick and stable feedback control to the target value REF can be performed.

Preferably, the bit converter 40 is set to have the least significant bit value of the error signal E of the positive group among the control signals (however, the error signal E in this example) being 1, and the error signal of the negative group. The value of the least significant bit of E is set to 0. In this way, E = 0, 2, 4, 6 is converted into C = 1, 3, 5, 7, and E = −0, −2,
-4 and -6 are converted into C = -1, -3, -5 and -7, respectively. As a result, the sum of the positive and negative dynamic ranges of C is ± 32, respectively, so that the imbalance between the positive and negative feedback amounts in the dynamic range is completely eliminated. Moreover, the bit conversion unit 40 in this case can be realized with a simple configuration.

[0022]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 2 shows the QAM of the embodiment.
FIG. 3 is a block diagram of a demodulation circuit, which includes feedback control for reproducing a reference carrier wave and feedback control for correcting the demodulation baseband signals I and Q. In the figure, 10 is a demodulated baseband signal I, Q.
A correction circuit for correcting the phase error and the drift component included in the phase error correction control circuit (DPR) 11
2 low-pass filter (LPF), 12 ₁ are cumulative addition circuit (ADD), 13 is a carrier recovery control circuit (DCR).

The flow of carrier wave reproduction control is the same as that described with reference to FIG. However, since the carrier wave reproduction control circuit 13 of the present embodiment is internally provided with the bit converting section 40 (not shown) as described in FIG. 1, the characteristics of the feedback control are greatly improved as described below. . FIG. 3 is a diagram for explaining carrier wave reproduction control of the embodiment.

In this example, the bit conversion section 40 converts the value of the least significant bit of the error signal E, which represents positive zero, of the error signal E represented by 2's complement formed by the operation to 1 to convert the error signal E to 1. Forming a ´. Regarding the Q-axis error signal E _Q ′, for example, when the received signal is reproduced at point a by advancing the phase of the carrier signal R _EF by Eφ ₁ , E _Q ′ =
-1, which produces a feedback amount of 1 unit towards the boundary of code point H ₀₀ . When the received signal is reproduced at the point b due to the delay of the phase of the carrier signal R _EF by Eφ ₁ , E _Q ′ = 1, which causes a feedback amount of −1 unit toward the boundary of the code point H ₀₀ . . The same applies to the I-axis error signal E _I ′. Therefore, the substantial equilibrium point of this feedback system is the code point H ₀₀ itself and has no spread. Therefore, such feedback control quickly converges to the code point H ₀₀ , and thereafter, transitions stably.

The carrier reproduction control circuit 13 of the present embodiment.
In the error signal E _I ', E _Q' rather than printing directly as a feedback signal, the error signal E _I ', E
Obtaining a phase error signal E? ₁ further performs predetermined logical and arithmetic operations based on _Q 'or the like, and outputs it as a feedback signal. Therefore, this phase error signal Eφ ₁ will be represented by the two's complement representation, and it may happen that Eφ ₁ = 0. In such a case, the bit converter 40 may be provided at the position shown in FIG. 2 if necessary. For the same reason, the bit conversion unit 40 may be provided at the position shown in FIG.

FIG. 4 is a block diagram of the bit conversion unit of the embodiment, showing a plurality of types of bit conversion circuits applied to the control signal (error signal) in the two's complement representation. In the figure, 40
Is a bit conversion unit, 40 ₁ is an OR gate circuit, and 40 ₂ is N
An OR gate circuit, 40 ₃ is an inverter circuit. Figure 4
The circuit (A) in FIG. ₂ has an input “S, A ₂ A ₁ A ₀ ” = “0,
000 ”, the output“ S ′, A ₂ ′ A ₁ ′ A ₀ ′ ”=
It is configured to output "0,001". Figure 4
The circuit of (B) is output when the input is “0, ×××” =
It is configured to output "0, XX1". However, the cross indicates that the input signal is followed. The circuit of FIG. 4C is configured to output the output “×, xx1” when the input is “x, xxx”.

FIG. 5 is a block diagram of a bit conversion section of another embodiment, showing a plurality of types of bit conversion circuits applied to a control signal (error signal) represented by 1's complement. In the figure,
40 is a bit converter, 40 ₄ is an AND gate circuit, 40
₅ is an EXOR gate circuit. The circuit of FIG. 5A outputs the output "0.001" when the input is "0000" and outputs the output "1,1" when the input is "1,111".
10 "is output. And FIG.
The circuit of (B) is output when the input is “0, ×××” =
"0, XX1" is output, and when the input is "1, XXX", the output "1, XX0" is output.

FIG. 6 is a diagram for explaining the operation of the correction circuit of the embodiment. By the feedback control for reproducing the carrier wave, the demodulated baseband signals I and Q maintain a certain degree of phase accuracy. However, in the case where the input signal IF is disturbed, the time constant of the feedback system may delay the follow-up of carrier wave reproduction, resulting in a phase error φ. Even in such a case, since the component of this phase error φ is corrected by the correction circuit 10, the demodulated baseband signals I ′, Q
With respect to ′, a predetermined phase accuracy can always be maintained, so that the identification circuit 3 can always correctly identify the received signal.

More specifically, referring to FIG. 2, the correction control circuit 11 has a corrected demodulated baseband signal I.
The deviation from the code point of the received signal reproduced in the specific zone is detected based on ′, Q ′, etc., and the corresponding phase error signal Eφ ₂ is output. If necessary, the phase error signal Eφ ₂ may be weighted. The low-pass filter 12 cumulatively adds a plurality of past phase error signals Eφ ₂ to smooth the phase errors and forms a phase control signal φ for the correction circuit 10.

Returning to FIG. 6, assuming that the phase angles of the I and Q axes have advanced by, for example, φ at this point, the correction circuit 1
The demodulated baseband signals I and Q delayed by the phase φ from the code point H ₀₀ are input to 0. On the other hand, since the lead angle control signal φ is fed back to the correction circuit 10 at this time point, the correction circuit 10 delays the phase angle of the I and Q axes by the control signal φ as follows: I ′ = Icosφ The corrected demodulated baseband signals I ′ and Q ′ are calculated by −Qsinφ Q ′ = Isinφ + Qcosφ. Therefore, the obtained demodulated baseband signal I
′ And Q ′ correctly indicate the code point H ₀₀ .

However, even when the above-described rotation calculation is performed, since φ, I, Q, sin φ, and cos φ are each represented by the two's complement expression, originally, the spread (value) is constant. ), Which should have) = 0, I = 0,
All are 0 even if Q = 0, sin φ = 0, and cos φ = 0
Will be treated as. Therefore, if these are used as they are for the calculation of the feedback amount for the feedback control, the feedback control cannot be sufficiently accurate, speedy and stable for the same reason as above.

Therefore, if necessary, the bit conversion unit 40 according to the present invention may be provided at the positions of and in FIG. Of course, it may be provided inside the correction control circuit 11 for the same reason as the case of the carrier wave reproduction control circuit 13 described above. In the present embodiment, the case where it is applied inside the correction circuit 10 is shown. FIG. 7 is a block diagram of a correction circuit of the embodiment. In the figure, 10 is a correction circuit, 40 is a bit conversion unit (BC), 5 is a multiplication circuit,
10 ₁ and 10 ₂ are adder circuits (ADD), 10 ₃ are 2's complement circuits (2's CMP), and 10 ₄ are phase angle control signals φ.
This is a ROM for reading each data of sin φ and cos φ by using as an address input. Although not shown, the correction circuit 10 also includes a circuit for correcting drift components of the I and Q axes.

The correction circuit 10 shown in FIG. 7 realizes the above rotation calculation, I '= Icosφ-Qsinφ Q' = Isinφ + Qcosφ. In this case, each bit conversion unit 4
0 is at least 2's complement representation I = 0, Q = 0, s
inφ = 0 and cosφ = 0 are I = 1, Q = 1, and si, respectively.
nφ = 1, cosφ = 1 (however, I = 1 and the like are converted into the minimum positive one unit in the two's complement representation).
With such a configuration, the accuracy of the correction control, the convergence of the feedback control, the stability, and the like are significantly improved.

Although the above embodiment has shown the example of application to the QAM demodulation circuit, the present invention is not limited to this. The present invention can be applied to all open control systems, feedback control systems, parameter control systems, etc., which are controlled by a control signal of 2 or 1's complement format.

[0035]

As described above, according to the present invention, a control signal which is set to 0 at least by digital quantization is converted into a control signal in the minimum +1 unit.
Especially in the feedback control system, the equilibrium point of control becomes accurate. In the case of the two's complement representation, the offset of the equilibrium point is corrected and the control balance of the dynamic range is improved, so that the control balance is significantly improved. Further, since the state where the control signal = 0 is excluded, the centripetal force at the control equilibrium point becomes stronger, and the blurring becomes smaller.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a QAM demodulation circuit according to an embodiment.

FIG. 3 is a diagram illustrating carrier reproduction control according to the embodiment.

FIG. 4 is a block diagram of a bit conversion unit according to the embodiment.

FIG. 5 is a block diagram of a bit conversion unit according to another embodiment.

FIG. 6 is a diagram for explaining the operation of the correction circuit according to the embodiment.

FIG. 7 is a block diagram of a correction circuit according to an embodiment.

FIG. 8 is a block diagram of a conventional QAM demodulation circuit.

FIG. 9 is a diagram illustrating a problem of the conventional technique.

[Explanation of symbols]

 20 control unit 30 feedback control unit 40 bit conversion unit

Claims (5)

[Claims] 1. A control signal processing method for a system, wherein a control signal represented by two's complement is input to a control unit to obtain a desired control output from the control unit, wherein at least positive zero of the control signals is represented. A method of processing a control signal, wherein the value of the least significant bit of the signal is set to 1. 2. The control signal processing method according to claim 1, wherein the least significant bit of the control signals of the positive group of the control signals has a value of 1. 3. The value of each least significant bit of the control signal is set to 1
The control signal processing system according to claim 1, wherein the control signal processing system is configured as follows. 4. A control signal processing method for a system, wherein a control signal represented by 1's complement is input to a control unit to obtain a desired control output from the control unit, wherein the control signal represents at least positive zero. A control signal processing method, wherein the least significant bit value of the signal is set to 1 and the least significant bit value of the control signal representing at least negative zero is set to 0. 5. The control signal is configured so that each least significant bit of the control signals of the positive group has a value of 1 and each least significant bit of the control signals of the negative group has a value of 0. 5. The control signal processing method according to claim 4, wherein.