JPH01158854A - Demodulator for digital radio communication system - Google Patents

Abstract

PURPOSE:To attain stable operation by providing an automatic phase control circuit detecting a phase difference between a digital data and a fixed frequency signal and applying coordinate conversion corresponding to the phase difference thereby improving the temperature stability. CONSTITUTION:An IF signal is branched and converted into a base band signal by orthogonal detectors 1a, 1b respectively and converted into a digital signal via filters 4a, 4b and an identification device 5. The phase of the IF signal is normally deviated from the phase of an oscillated frequency signal from a crystal oscillator 2. The automatic phase control circuit 6 detects the phase difference and applies the coordinate conversion with respect to the phase difference (concretely, the two inputs are corrected by control information sin thetaand costheta, where theta is the phase difference) to obtain correct I and Q channel signals. The fixed frequency is used for the detection to correct the phase difference. Thus, the temperature stability is improved and the synchronizing lock range is widened.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a demodulator for digital wireless communication systems such as 64QAM and 256QAM, which improves temperature stability and performs stable operation. An oscillator that provides a fixed frequency to a quadrature detector that orthogonally detects an intermediate frequency signal and converts it to a baseband signal, a filter that passes only the baseband signal of the low frequency component, and a converter that converts the baseband signal from the filter into digital data. and an automatic phase control circuit that detects a phase difference between digital data and a fixed frequency and performs coordinate transformation corresponding to this phase difference.

[Industrial application field]

The present invention relates to demodulators for digital wireless communication systems such as 64QAM and 256QAM.

Digital wireless communication systems such as 64QAM and 256QAM have been widely researched as high-efficiency wireless communication systems.
It has been put into practical use.

In such multi-value QAM, as the number of multi-values increases, the jitter of the reproduced carrier greatly affects demodulation. That is, this jitter degrades the bit error rate. Therefore, when designing a demodulator, it is necessary to reduce this jitter to obtain a reproduced carrier.

[Conventional technology]

Various carrier recovery means performed by demodulators of digital wireless communication systems such as 64QAM and 245QAM have been proposed and put into practical use. For example, using a voltage controlled oscillator, P l-L (phase 1 ock loop)
Identification of the baseband signal obtained by detection (A/D conversion), which consists of a circuit, a pilot carrier insertion type that inserts a reference pilot carrier on the transmitting side and achieves phase synchronization, or a baseband signal obtained by detection without inserting a carrier. Costas type carrier regeneration, which achieves phase synchronization using later data, is known.

[Problem that the invention seeks to solve]

However, all of the above conventional configurations have problems due to the temperature characteristics of the voltage controlled oscillator. That is, in boat fishing, a voltage controlled oscillator has poorer temperature characteristics than a crystal oscillator, and if an attempt is made to increase the frequency control sensitivity (synchronization pull-in range), the temperature characteristics deteriorate. This is especially true when the number of modulation levels is increased (for example, 64QAM
256QAM). As described above, it has been difficult to set a wide pull-in range while maintaining good temperature stability.

Therefore, it is an object of the present invention to solve the above problems and provide a demodulator that maintains good temperature stability and performs stable operation.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, orthogonal detectors 1a and 1b receive an intermediate frequency signal (IF multiplied signal) obtained by converting a received high frequency signal into an intermediate frequency.An oscillator 2 is a crystal oscillator and oscillates at a fixed frequency.

This fixed frequency is applied to the quadrature detector 1a on the one hand, and is phase-shifted by 90° by the phase shifter 3 and applied to the quadrature detector 1b on the other hand. Low pass filters 4a and 4b
pass only the low frequency components of the baseband signals, which are the output signals of the quadrature detectors 1a and 1b, respectively. Discriminator 5 converts the baseband signals from low-pass filters 4a and 4b into digital data. The automatic phase control circuit 6 detects a phase shift difference with the IF multiplied signal fixed frequency, and performs coordinate transformation corresponding to this phase difference.

[Effect]

The IF multiplied signal is branched and converted into baseband signals by quadrature detectors 1a and 1b, respectively, and filters 4a and 4b.
Then, it is converted into a digital signal via the discriminator 5. This IF multiplied signal is normally out of phase with respect to the oscillation frequency of the crystal oscillator 2, that is, the local oscillation frequency on the transmitting side. Therefore, the automatic phase control circuit 6 detects this phase difference, performs coordinate transformation on this phase difference, and specifically corrects the two inputs using control information sinθ and COSθ (θ is this phase difference) to correct the I channel and Q channel signals (hereinafter referred to as ① data and Q data) are obtained.

In this way, since the fixed frequency is used for detection and the phase difference is corrected, the temperature stability is good and the synchronization pull-in range can be widened.

〔Example〕

Examples of the present invention will be described in detail below.

FIG. 2 is a diagram explaining the principle of the automatic phase control circuit 6 shown in FIG. 1. The illustrated example is a case of 64QAM method. In the figure, the orthogonal coordinates (i, (+) are the coordinates of the input signal of the automatic phase control circuit 6, and the orthogonal coordinates (1, Q) are the correct coordinates, that is, the coordinates of the fixed oscillation frequency of the oscillator 2. The point (x, y) on (i, q) is the orthogonal coordinate (1
, 0) When viewed above, it becomes (X, Y).

The relationship between (x, y) and (X, Y) is the rotation angle of the coordinate system θ
Then, it becomes as shown in the following formula.

Therefore, the automatic phase control circuit 6 has a signal X on its output side,
The phase difference θ between (x, V) and (X, -Y) is detected using Y, and control information sin θ, C corresponding to the phase difference θ is detected.
By using OS θ, coordinate transformation based on the phase difference θ is performed.

The circuit shown in FIG. 3 shows the relationship shown in equation (1) above using a circuit configuration. In the figure, the control unit 6a controls the output coordinates (X) of data and Q data.

Y) and outputs the sin θ and COS θ.

sin θ is multiplied by the input coordinates X and y in multipliers 6b and 6C, respectively, and output to adders 6g and 6f. C
OSθ is multiplied by the input coordinates X and y in multipliers 6d and 6e, respectively, and output to adders 6f and 6g. The adder 6f adds the output x-cos θ of the multiplier 6d and the output y-sin θ of the multiplier 6c, and obtains X-・x-cos θ+y
- Outputs sin θ.

On the other hand, the adder 6q adds the output y-cos θ of the multiplier 6e and the inverted output of the multiplier 6b, x-cos θ,
Output Y=-X-sin θ+y-cos θ.

FIG. 4 is a circuit diagram of one embodiment of the present invention.

The automatic phase control circuit 6 has the circuit configuration shown in FIG. Moreover, the discriminator 5 is composed of A/D converters 5a and 5b, as shown in the figure.

Next, the configuration of the control section 6a of the automatic phase control circuit 6 will be explained.

As mentioned above, the control section 6a uses the output of the automatic phase control circuit 6, that is, the I data and the Q data, to generate the control information s.
Generate inθ and COSθ.

FIG. 5 is a block diagram of a first configuration example of the control section 6a when the present invention is applied to the 64QAM system. The illustrated control unit 6a includes an up/down counter (hereinafter simply referred to as a counter) 7 and ROMs 8a and 8b.

The counter 7 receives, at its U/D control terminal (which receives instructions for up-counting or down-counting), the 11 data of the (2) data and the sequential output of the Q4 data.

, 11 data is data that divides the area shown by the coordinate axis ■ in FIG. 2 into two, and indicates the rotation direction of the coordinates, that is, the polarity of the data after identification. Also, Q4 data is Q1
It is a pit immediately below the signal point data (in the case of 64QAM) consisting of ~Q3, and indicates the direction of deviation of the identified data from the corresponding predetermined signal point (indicated by the "x" mark in Figure 2). It shows. As a result, the exclusive OR output 11*04 of the 11 data and the Q4 data indicates the direction of the coordinates (X, V) to be rotated by the automatic phase control circuit 6.

This direction corresponds to up-counting and down-counting of the counter 7. ■1■Q4 is “OII” and “1”
'', the counter 7 counts down and counts up, respectively.The output of the counter 7 becomes the address signal for the ROMs 8a and 8b.The ROM 8a stores a table of sin θ corresponding to the address, and the ROM 8b stores the table of sin θ corresponding to the address. Memorizes the table.R
Control information si read from OM8a and 8b, respectively
nθ and COSθ are output to corresponding multipliers as shown in Figure 18-4.

In this way, the automatic phase control circuit 6 always has the correct
Channel and Q channel data are reproduced and output.

FIG. 6 is a block diagram of a second configuration example of the control section 6a. This configuration is characterized in that the pit error rate is detected in a pseudo manner and the control information sin θ and COS θ are controlled at a higher speed. This is because the phase rotation speed differs depending on the frequency difference between the IF input signal and the fixed oscillator.

In FIG. 6, a pseudo error detector 9 detects the bit error rate in a pseudo manner from the output data of the automatic phase control circuit 6. - For example, in 64QAM, I4 data and I5 data are exclusively ORed. I4 data is ■1 to I3
This is the lower bit of data of a signal point (64QAM) consisting of data, and indicates the direction of deviation of data after identification with respect to a predetermined signal point. I5 data is the lower bit of I4 data, and indicates whether the deviation indicated by 14 bits deviates from a given signal point in a direction close to the signal point or in a direction far from the signal point. It is. Therefore, the exclusive OR of I4 and 15■4■I5 is 'O'' (
When the signal point is "low", the identified signal point is pseudo-regarded as having no error, and when it is "1" (high), it is pseudo-regarded as an error. The pseudo error detector 9 takes this exclusive OR output,
Output to ROHloa and 10b. Note that the exclusive OR output is held (integrated) by a predetermined number of bits (for example, 8 bits), the ratio of cases with errors to cases without errors is detected, and a control signal C0NT1 corresponding to this ratio is stored in the ROM 10.
It is also possible to output the data to ports a and 10b.

Each of the ROMs 10a and 10b includes two tables (for the ratio of non-integration), or a number of tables corresponding to the ratio specified by this control information C0NT1 (for the case of integration). sin θ and C stored in each page
OSθ has different amounts of change per step. For example, sin θ and COS θ when there are no errors in all 8 bits.
The amount of change per step is small. ROM10a and 1
0b outputs sin θ and COS θ corresponding to the address specified by the counter 7 from the table specified by the control information C0NT1. In this case, at the time of synchronous pull-in, sin θ and COS per step
By selecting a table with a large amount of change in θ and increasing the amount of phase change, it is possible to quickly converge the phase difference.

FIG. 7 is a block diagram of a third configuration example of the control section 6a. This configuration also controls sin θ and COS θ at high speed. This configuration includes a frequency multiplier 11 in addition to the counter 7, ROMs 8a and 8b (FIG. 5), and pseudo error detector 9 (FIG. 6) described above.

This frequency multiplier 11 multiplies the clock CLK, and the multiplication amount×n is switched according to the value of the control information C0NT1 of the pseudo error detector 9. For example, control information CON T 1
When the error is small, the amount of multiplication is small, and when the error is large, the amount of multiplication is large.

FIG. 8 is a block diagram of a fourth example of the configuration of the control unit 6a.1 The feature of this configuration is that the output of the counter 7 is connected appropriately to change the amount of change in the address value. The selector 12 inputs the input to and the B input to the pseudo error detector 9.
Either the ? input or the B input is selected according to the control information CON T 1 and output to the ROMs 8a and 8b.

FIG. 9 is a block diagram of a fifth configuration example of the control section 6a. A feature of this configuration is that a plurality of clocks to be applied to the counter 7 are generated using a BTR circuit. The voltage controlled oscillator 13 with a frequency n times that of the recovered clock is 1/
2 frequency divider 15a.

..., 15b, '15c, and selector 1
6 is given. The output of the frequency divider 15C is the phase comparator 1
5, the phase is compared with the identified baseband signal, and a voltage corresponding to the phase difference is applied to the voltage controlled oscillator 13 via the loop filter 14.

The selector 16 receives the control information C0NT1 of the pseudo error detector 9.
One of the frequencies is selected according to the selected frequency and given to the counter 7.

FIG. 10 is a block diagram of a sixth configuration example of the controller. The feature of this configuration is that in the second configuration example described above, when the tables of ROMs 10a and 10b are switched, the phase θ output from ROMs 9a and 9b becomes discontinuous. The goal is to keep it.

This will be explained with reference to FIG. Figure 6 (a) shows the change in sin θ in a steady state (sin θ when the control information CON T 1 outputted by the circuit shown in Figure 6 is low without error), and Figure 6 (b) shows the change in sin θ. indicates a change in sin θ (sin θ when the control information C0NT1 outputs an error (high)) when the control speed of sin θ is doubled. Now, when the control information C0NT1 has an error (high) and sinθ is being controlled at twice the control speed as shown in FIG. 11(b), the control information C0NT1 changes from high to low (no error). Suppose it has changed. Assume that the address of the ROM 10a at this time is A1 (the position of θ-π). Since the table in the ROM 10a changes with this address, the phase of sin .theta. jumps to the position A2 (the .theta.-.pi./2 position) shown in FIG. 11(a) according to the contents of this table. Therefore, the phase of reproduction 4: Yaria becomes equivalent to that of S;, and the digital data becomes discontinuous and an error occurs. The circuit shown in FIG. 10 solves this problem, and in the above case, in order to maintain the continuity of the contents of the table in the ROM 10a, the circuit shown in FIG.
By doubling the address (a) and initializing the counter 7, the address is changed to the position A3 (the position θ-π) to maintain phase continuity.

The above explanation was regarding sin θ, but the same is true for COS θ.

Next, the circuit of FIG. 10 will be explained with reference to the operating waveform diagram of FIG. 12.

Control information C0NT1 for the pseudo error detector 9 (in this example, it has a 1-bit configuration) (FIG. 12(a) shows a delay circuit 17 that delays by Q bits, an exclusive OR circuit 20,
It is applied to M10a and M10b and selector 19.

The exclusive OR circuit 20 performs an exclusive OR of the control information CONT1 of the pseudo error detector 9 shown in FIG. 12(C) and C0NT1 delayed by Q bits (FIG. 12(C)). Then, the signal shown in FIG. 12(d) is output to the LOAD terminal of the counter 7.

Now, at time t+ in FIG. 12, control information C0I4T1
changes from high to low, the counter 7 is loaded and the selector 19 selects the address multiplier 18a that multiplies the output (address) of the counter 7 by P (in the example of FIG. 11, P-2). .

At this time, the 10 AD terminal of the counter 7 is high. As a result, an address obtained by multiplying the address from the counter 7 by P is loaded into the data IN terminal of the counter 7. From then on, the counter 7 counts from this P times address to 11 (E
Count up or down according to IQ4 signal, RO
Give addresses to M10a and 10b. The above operation corresponds to the case where the address at the position A1, which was explained with reference to FIG. 11, is doubled and moved to the position A2.

Furthermore, at time t2, the control information CON T 1 changes from low to high. At this point, the selector 19 selects the address multiplier 18b which multiplies the address output from the counter 7 by 1/P. At this time, l OAD of counter 7
@Chi is high. Therefore, the data IN of counter 7
An address obtained by multiplying the address from the counter 7 by 1/P is loaded into the terminal. From now on, counter 7 will be this 1/P.
From the double address, it counts up or down according to the 11*Q4 signal and gives the address to the ROMs 10a and 10b.

As described above, phase continuity is maintained when switching the tables in the ROMs 10a and 10b.

Various configurations and functions of the control section 6a have been described above.

In the above configuration, the input signal of the control unit 6a is ■1■04
It is not limited to Q1, ■, and Q4, and may be used by switching as necessary. Also, the input signal of the pseudo error detector 9 is Q4
It may be +05. Furthermore, in the above explanation, mainly 64
Although the explanation has been given using QAM as an example, it can be implemented similarly with 256QAM or the like. Furthermore, in addition to the above configuration, FIG. 13 (a>
Alternatively, as shown in (b), it is preferable to provide an automatic equalizer 21. This automatic equalizer 21 can be configured with, for example, a transversal digital filter.

〔Effect of the invention〕

As described above, according to the present invention, since the detection is performed using a fixed frequency and the phase difference is corrected, a demodulator with good temperature stability and a wide period pull-in range can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a diagram explaining the principle of the automatic phase control circuit in Figure 1, Figure 3 is a circuit diagram of the automatic phase control circuit in Figure 1, and Figure 4 is a diagram of the principle of the automatic phase control circuit in Figure 1. A circuit diagram of an embodiment of the present invention; FIG. 5 is a block diagram of a first configuration example of the control section in FIG. 3; FIG. 6 is a block diagram of a second configuration example of the control section; FIG. is a block diagram of a third configuration example of the control unit, FIG. 8 is a block diagram of a fourth configuration example of the control unit, FIG. 9 is a block diagram of a fifth configuration example of the control unit, and FIG. 10 is a block diagram of a fourth configuration example of the control unit. 11 is a diagram explaining the principle of the configuration shown in FIG. 10, FIG. 12 is an operation waveform diagram of the configuration shown in FIG. 10, and FIG.
FIG. 3 is a block diagram of another embodiment of the present invention. In the figure, 1a and 1b are quadrature detectors, 2 is an oscillator, 3 is a phase shifter, 4a and 4b are low-pass filters, 5 is a discriminator, 6 is an automatic phase control circuit, 6a is a control unit, and 7 is a counter , 8a, ab, 10a, and 10b are ROMs. 9 indicates a pseudo error detector. Fig. 1 Fig. 2 The procedure of the Cha Daga Keyaki μ bite j Fig. 119 Fig. 11

Claims (1)

[Scope of Claims] In a demodulator of a digital wireless communication system, an oscillator (2) that provides a fixed frequency to a quadrature detector (1a, 1b) that orthogonally detects a branched intermediate frequency signal and converts it into a baseband signal; A filter (4a, 4b) that passes only the baseband signal of the low frequency component; a discriminator (5) that converts the baseband signal from the filter (4a, 4b) into digital data; and a discriminator (5) that converts the baseband signal from the filter (4a, 4b) into digital data. A demodulator for a digital wireless communication system, comprising an automatic phase control circuit (6) that detects a phase difference and performs coordinate transformation corresponding to this phase difference.