JPS62206950A - Phase synchronization detecting circuit - Google Patents

Abstract

PURPOSE:To suppress the deterioration in detection linearity of an analog phase modulation signal by providing additionally a phase shift quantity control means and a 90 deg. variable phase shifter, detecting the orthogonal phase state of a recovered carrier, controlling the phase shift of the 90 deg. variable phase shifter by the detection result to stabilize the orthogonal phase state of the recovered carrier. CONSTITUTION:A direct output of a voltage controlled oscillator 18 is used as the recovered carrier (I-CW) and a signal shifted by 90 deg. by the 90 deg. variable phase shifter 25 is used as a recovered carrier (Q-CW). A phase shift control means 40 adjusting finely the phase shift is connected to the 90 deg. variable phase shifter 25. A control means 40 detects the quantity of the detected outputs whose phases differ but whose detection level is equal to each other to detect the recovered carriers (I-CW), (Q-CW) to be in the orthogonal phase whether or not they are shifted from 90 deg.. Based on the detection result, the phase shift quantity of the variable phase shifter 25 is detected to correct the said recovered carriers to be in the orthogonal phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a synchronous phase detection circuit used for detecting multilevel information in a transmission system.

(Prior Art) There is a four-phase phase modulation method as a method for transmitting multilevel information. FIG. 5 shows the phase vector of the phase modulation signal,
Fig. 6 shows a synchronous detection circuit for this phase modulation signal. In Fig. 5, A, B, C, and D indicate four phases in the four-phase phase modulation system. ,C,D
The circumference containing the curve shows the locus of values obtained with analog phase modulation. Further, the first axis indicates a carrier wave phase that is in phase with the reference phase, and the Q axis indicates a carrier wave phase that is orthogonal to the first axis.

FIG. 6 shows a synchronous detection circuit for the time-division signals of the four-phase phase modulation and analog modulation. The above-mentioned time-division modulated signal inputted from input terminal 1 is passed through a bandpass filter (BP in the figure).
After being band-limited by (denoted as F') 2), it is supplied to phase detection circuits 3 and 4. The phase detection circuits 3 and 4 detect a regenerated carrier wave (I
-cw) (q-CW) to perform synchronous detection of the time-division modulated signals input to each. The outputs of each phase detection circuit 3.4 are supplied to analog-to-digital converters (indicated by "") 5 and 6, and quantized into m-bit digital signals. MSB of each analog-digital converter 5, 6
Output (5M5B) (6M5B) is 4-phase detector 1
is supplied to. This MSB output (5M, SB) (
6MSB) is exactly the same as the binarized output obtained using a normal comparator. The four-phase detector 11 has two human-powered 0″
, 11'', the phase information is transmitted to its output terminal 13.
Derived as follows.

On the other hand, the output 5D of analog differential converters 5 and 6
, 6D is the part θ with respect to the analog phase θ.

Since the value is the ratio θ, if these are supplied to the 111 circuit (denoted as TAN 1 in the figure) 12 having a 1m-' characteristic, the above value of θ can be obtained, and this is sent to the output terminal 14.
Derived as follows. Regeneration of the carrier wave occurs like an arrow. For example, by using the fact that the values obtained from the 4-phase phase signal and 9 are fixed at an interval of 90', at the time of 4-phase phase modulation, the jan
This is accomplished by operating the phase-locked q-7 (PLL) so that the output of the circuit 12 has the phase that the four-phase phase modulation signal should take. That is, tan″″′1 circuit 1
2 is supplied to the date circuit 15, and this r-t circuit 1
At step 5, the output is sampled using a four-phase phase modulation timing signal (TCK) to obtain an error between the phase that the four-phase phase modulation signal should take and the phase actually obtained by synchronous detection. By supplying this error to the voltage control oscillator 18 via a 7J digital analog converter (denoted as D/A in the figure) 17, a regenerated carrier wave (I-CW) is generated.
(Q-CW) can be adjusted to a desired phase. Note that 19 is a 90° phase shifter, which is used to obtain a recovered carrier wave (Q - CW) of the Q-axis phase.

(Problem to be Solved by the Invention) Now, considering the case where the phase difference between the 1st axis and the Q axis shown in Fig. 5 is not exactly 90°, the reproduced carrier wave is The r' and q axes of FIG. 3 shows a case where the phase difference between the 1' axis and the q axis is 900 or less. Regarding the detection of a four-phase phase modulation signal, the bit error will increase, but if the phase difference between the engineering axis and the Q' axis is about 5 degrees, the equivalent C deterioration amount is about 0.5 dB, which is a large amount. Not a problem. However, even if there is a slight orthogonality difference n as shown in FIG.
To eliminate this, an accurate and stable 900 phase shifter is required.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a synchronous phase detection circuit which can completely suppress the deterioration of the detection linearity of an analog phase modulation signal as a time-division signal as described above.

(Means for Solving the Problems) In the present invention, detection outputs that are different in phase but should have the same detection level are compared to detect a magnitude relationship, and reproduced carrier waves (I-CW) that should be in orthogonal phase to each other are detected. ), (Q
-CW) is deviated from the angular interval of 90' by the phase shift amount control means 40. Based on the information obtained in this detection process, the amount of phase shift of the 90' variable phase shifter 25 is controlled, and the reproduced carrier waves (I-CW) and (Q-CW) are corrected to have orthogonal phases. It is something.

(Function) As described above, by providing the phase shift amount control means 4θ and the 900 variable phase shifter 25, the reproduced carrier wave (I = cw),
The orthogonal phase state of (q-cw) is detected, and based on this detection result, the phase shift amount of the 90° variable phase shifter 25 is controlled, and the orthogonal phase state of the reproduced carrier waves (I-cw) and (Q-CW) is controlled. The condition will always remain stable.

(Example) Examples of the present invention will be described below with reference to the drawings. 1st
The figure shows one embodiment of this invention, and the basic configuration is the sixth embodiment.
Although there is no difference from the conventional system explained in the figure, in the case of the present invention, the regenerated carrier wave (I-
It is characterized in that a phase shift amount control means 40 is connected to a 90' variable phase shifter 25 which shifts the phase of the carrier wave (Q - CW) by 90' to obtain a recovered carrier wave (Q - CW). The circuit shown in FIG. 1 will be explained below.

A time-division modulated signal inputted from an input terminal 1 is band-limited by a bandpass filter 2 and then supplied to phase detection circuits 3 and 4. The phase detection circuit 3.4 basically consists of the third
Regenerated carrier wave (
I-CW) and (Q-CW) are used to perform fully synchronous detection of the time-division modulated signals input to each. The output of each phase detection circuit 3.4 is then sent to an analog-to-digital converter 5.
6 and is quantized into an m-bit digital signal. MSB output of each analog-to-digital converter 5.6 (
5M5B) (61M5B) is exactly the same as the output obtained by binarizing a 4-phase signal using a normal comparator.

Therefore, the MSB output (5MSB) of the analog-digital converter 5 (7) is distinguished by a code of 0.1 between the upper and lower sides of the ■ axis in FIG. Further, the MS 8 output (6MSB) of the analog-to-digital converter 6 distinguishes left or right in FIG. 3 with a 0°1 signal with the Q axis as the boundary. These MSB outputs are supplied to a four-phase detector 11. In the four-phase detector 11, by combining the signs of the MSB outputs from the analog-to-digital converters 5 and 6,
Identification of the four phases is performed, and the output is output from the output terminal 13.
is derived.

On the other hand, the output 5D of the analog-digital converters 5 and 6,
60 is a mouse θ regarding the analog phase θ.

Therefore, if these are supplied to the m-1 circuit I2 having the jan' characteristic, the above value of θ can be obtained. This value θ is led to the output terminal 14. Thereby, the transmitted information can be grasped by the quadrant information of the output terminal 13 and the angle information of the output terminal 14.

Next, the recovered carrier wave (
r-cw) and (Q-CW) are created as follows.

The output (value of θ) of the tlIll-1 circuit 12 is supplied to the r-t circuit 15. This date circuit 15 receives a timing signal (
TCK) is supplied. This method focuses on the fact that the values obtained by the four-phase phase signal are fixed at intervals of 90'', and at the time of four-phase phase modulation, the output of the tu-' circuit 12 is a predetermined value (phase θ ).Therefore, the Dart circuit 15 samples the output of the C-1 circuit 12 according to the timing signal, and uses the phase actually obtained by synchronous detection and the four-phase phase modulation. An error with respect to a predetermined phase that the signal should take is obtained.This error is converted into a DC control voltage by the digital-to-analog converter 17 and supplied to the frequency control terminal of the voltage-controlled oscillator 18.

Thereby, the oscillation output frequency of the voltage controlled oscillator I8 is controlled such that the output of the tu' circuit 12 becomes a predetermined value around the four-phase phase modulation signal.

Here, the direct output of the voltage controlled oscillator 18 is used as a regenerated carrier wave (I-GW), which is transferred to the 90° phase shifter 25.
The phase shifted by 90° at is the regenerated carrier wave (Q-CW
) is used as

By the way, in this invention, the 90° variable phase shifter 25
A phase shift amount control means 40 is connected to which can finely adjust the phase shift amount.

The phase shift amount control means 40 includes a comparison circuit 22 . Low pass filter 2
3. It is composed of a digital-to-analog converter 24. The operation will be explained below with reference to FIG.

Now, as shown in Figure 3, the phase difference between the 1st axis and the Q axis is 900.
If it deviates from this, a carrier wave for synchronous detection is obtained by the action of the phase-locked loop, as shown in the I'-axis and Q'-axis in the figure.

Carrier waves I/ and Q/ are reproduced so that the four phases of A, B, C, and D are always 450 in each phase quadrant. At this time, for example, A projected onto the Il axis.

If B, C, and D are respectively a, b, c, and d, the result will be as shown in the figure, but when a=d and b==c, 1'
It can be seen that the and Q' axes coincide with the mechanical and Q axes.

Therefore, the 90° phase shifter 2
If the phase shift amount of 5 is controlled, the I' axis and Ql axis will be 90
', and together with the phase-locked loop, it coincides with the l-axis and the Q-axis. For this purpose, the comparator circuit 2
In 2, 11 axis detection output 5DK included A, B,
Value a corresponding to C and D.

b, e, and d are taken in, and a and d and c and d are compared. From the terminal 38, a latch/mother loop for inputting a, b, c, and d is provided. The comparison result of the comparison circuit 22 is supplied to the digital-to-analog converter 24 via the low-pass filter 23.

This becomes an analog control signal and is supplied to the phase shift amount control terminal of the 90' phase shifter 25. This makes the Q′ axis Qiil
1, and the I' axis also coincides with the 1 axis.

FIG. 2 shows a part of the phase shift amount control means 40 in more detail. Of the m-bit output of the analog-to-digital converter 5, the lower (m-1) bits 51] are supplied to the input terminal 26. The latch circuit 28 latches the value a, and the latch circuit 29 latches the value d. Similarly, the lower (m-1) bits 5D are inverted in sign by the inverter 27 and then supplied to the latch circuits 30 and 31, which latch circuits 3θ
latches the value of C, and the latch circuit 31 latches the value of b. The values of a and d are compared in magnitude by a comparator 32, and the values of C and b are compared in magnitude by a comparator 33. The comparison results are input to the selector 34, where only the necessary ones are taken out, and after being smoothed by being supplied with a low-pass filter 23 (C) consisting of an adder 35 and a delay circuit 36, they are output to an output terminal 37. be done.

In the above embodiment, in order to detect the orthogonal phase state of the ■-axis and the Q-axis, which are the reference phases, 45° and 315° or 135°
A phase shift amount control signal for the 90' variable phase shifter 25 was created by comparing the magnitude relationship between the Q and 225° phase detection output levels. However, it is not limited to this, 40', 1350 or 22
The phase shift amount control signal may be generated by comparing the phase detection output levels of 50° and 315°.

〔Effect of the invention〕

According to the invention described above, it is possible to obtain an analog phase detection output with extremely good linearity by detecting the orthogonal phase shift of the regenerated carrier wave for synchronous detection using a simple means and adjusting the amount of 90° phase shift. can. And conventionally 9
High precision as a 0' phase shifter.

Although a highly stable and expensive material was required, an inexpensive material may be used according to the present invention. Furthermore, even if an inexpensive 90° variable phase shifter is used, there is a means to automatically control the amount of phase shift, so it operates so that accurate detection output can be obtained even with changes in ambient temperature, etc. be able to.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of the circuit in FIG. 1 in more detail, and FIG. 3 is a circuit diagram shown to explain the circuit operation of this invention. An explanatory diagram of the phase axis, Fig. 4 is a diagram showing an example of the characteristics of the analog phase detection output, Fig. 5 is an explanatory diagram showing the vector of the four-phase phase modulation method, and Fig. 6 is an explanatory diagram showing the vector of the four-phase phase modulation method.
The figure shows a conventional synchronous Tateyama detection circuit. 3.4... Phase detection circuit, 5, 6... Analog-to-digital converter, 11... 4-phase detection circuit, 12...
tu' circuit, 15... Dart circuit, 17... Digital analog converter, 18... Voltage controlled oscillator, 2
5...90' variable phase shifter, 4θ...phase shift amount control means. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 ma Output a phase (degree) Figure 4

Claims (1)

[Claims] First and second phase detection circuits are supplied with signals including four-phase phase modulation and analog phase modulation in a time-division manner, and perform synchronous detection using mutually orthogonal regenerated carrier waves; an analog-to-digital converter that quantizes the output of the detection circuit, a means for obtaining quadrant information of the input signal using the upper bits of the output of the analog-to-digital converter, and a tan^-^ using the output of the analog-to-digital converter. means for obtaining angle information by performing the processing in step 1, extracting detection information present at the timing of the four-phase phase modulation from the angle information, obtaining an error between this detection information and predetermined reference information, and based on this; means for controlling the oscillation frequency of a voltage controlled oscillator that generates the first regenerated carrier wave, and a 90° variable phase shifter that shifts the phase of the first regenerated carrier wave to derive the second regenerated carrier wave. Of the outputs of the first analog-to-digital converter, the outputs that are different in phase but should have the same detection level are latched, compared in magnitude, and the difference is used to make the outputs that should be equal become equal to each other. A synchronous phase detection circuit comprising means for controlling the amount of phase shift of the 90° variable phase shifter.