JP2932707B2 - Stencil mask forming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam lithography technique for microfabrication of a semiconductor device, and more particularly to a method of forming a stencil mask in reduction transfer type electron beam lithography using a stencil mask. is there.

[0002]

2. Description of the Related Art Electron beam lithography technology is used as a tool for advanced development of LSIs because it does not require the use of a reticle and can form a fine pattern. Conventionally, a widely used electron beam drawing method is a method in which patterns are sequentially drawn one by one by a Gaussian beam or a variable shaped beam using a field emission type or a thermionic electron gun.
This is called the one-stroke writing method. That is, an electron beam generated from an electron gun can be focused on a resist surface by a focusing lens into a narrow beam spot, and the position of the beam spot can be controlled by a deflection system to draw an arbitrary figure on the resist. It is.
This method has the merit that distortion and aberration inside the deflection field can be electrically corrected and the accuracy can be increased depending on the control technique, and many methods have been developed and put to practical use. On the other hand, however, in this method, since the spot diameter of the electron beam is about 0.1 to 2 μm, the size of the drawing pattern is reduced, and the number of spots to be drawn becomes enormous. There is a drawback in that the spot movement speed is limited due to the limitation of the operating frequency, and the time required for drawing becomes extremely long, and the throughput is reduced.

In order to solve these drawbacks, a reduction transfer method has recently been proposed in which the entire pattern of an LSI chip is not drawn as a single stroke, but a partial pattern is transferred using a mask. Figured out. In other words, there is a method in which a repetitive area of the LSI pattern is decomposed into small area partial patterns, this pattern is formed on a stencil mask, and the pattern is sequentially transferred using this mask. However, this method is expected to have a very high throughput, but it is very difficult to form a stencil mask to be used. For example, an example of a stencil mask forming method currently considered is shown in FIG.

An acceleration voltage of 50 K is applied to the semiconductor silicon substrate 11.
V, boron ions 42 are implanted at a dose of 1 × 10 ²⁰ cm ⁻² to form an ion implanted layer 41 (FIG. 4).
(A)). An epitaxial layer 43 of silicon is formed thereon, and a nitride film is deposited as a protective film 44 on the epitaxial layer and on the back surface of the silicon substrate (FIG. 4B). Then, the silicon oxide film on the backside of the semiconductor silicon substrate is selectively removed using lithography and dry etching techniques, and the backside of the semiconductor silicon substrate is etched to a boron injection layer with an ethylenediamine / pyrocatechol solution using the silicon oxide film as a mask. Etching is performed to remove the protective film (FIG. 4C).
A resist pattern 45 is formed on the epi layer by using an electron beam lithography technique (FIG. 4D). Using the resist pattern 45 as a mask, the epi layer and the ion-implanted layer are etched to form a mask pattern (FIG. 4E).

[0005] By the above method, a stencil mask used in electron beam reduction transfer lithography can be formed. However, in this method, a protective film must be deposited, and a mask for blocking an electron beam only by a silicon ion-implanted layer and an epilayer must be used. Becomes
Etching is not easy either.

[0006]

As described above, in a stencil mask used for electron beam reduction transfer lithography, if only a silicon material is used, a film thickness of several tens μm or more is required. FIG. 3 shows the range of electrons in silicon with respect to the acceleration voltage of the electron beam. Usually, the acceleration voltage used in electron beam lithography is 20 to 50 KV, so that a silicon film as a mask requires a film thickness of about 20 μm. It is very difficult to etch silicon having a film thickness of several tens of μm or more, and many steps such as ion implantation, epitaxial technology, lithography, and etching are required, which complicates the process of forming a stencil mask. There are drawbacks. In addition, silicon itself is fragile and has a disadvantage that it is easily broken. Undoped silicon has poor electron conductivity, and there is also a problem that the electron beam irradiation causes charge-up and beam deviation. That is, it is desired that the stencil mask be as thin as possible, have mechanical strength, good electron conductivity, and good dimensional stability and thermal stability due to temperature change.

Therefore, it is conceivable to deposit a metal on the surface of the silicon mask to prevent charge-up or to reduce the film thickness. (FIG. 3) shows that, like silicon,
The range of electrons for gold is also shown. Since gold cannot be etched, it can only be deposited on the mask surface and is very difficult to handle as an impurity in silicon semiconductor processes. In addition, heat is generated by irradiating the mask with the electron beam,
The mask is deformed. At this time, the thermal expansion coefficient is 2.5 × 10 ⁻⁶ / deg for silicon and 14.2 × 10 ⁶ for gold.
^-6 / deg, and the thermal conductivity of silicon is 1.7cm.de
g and gold are 3.1 cm.deg., and it is considered that the mask is distorted by depositing gold on the surface of the silicon mask. The present inventors have completed a method for forming a stencil mask for electron beam reduction transfer lithography in order to solve these problems.

[0008]

According to the present invention, there is provided a stencil mask forming method comprising the steps of: depositing an inorganic film on a surface of a semiconductor silicon substrate; forming a resist pattern on the inorganic film by using a lithography technique; Using the pattern as a mask, etching the inorganic film to transfer the pattern, exposing the semiconductor silicon substrate,
Selectively depositing metal tungsten on the semiconductor silicon substrate; and selectively removing a silicon portion of the semiconductor silicon substrate from a back surface after removing the inorganic film. Things. Preferably, the inorganic film deposited on the semiconductor silicon substrate is a silicon oxide film, and the metal tungsten deposited on the semiconductor silicon substrate is 3 μm or more in thickness.

Further, the present invention provides a step of depositing an inorganic film on the surface of a semiconductor silicon substrate, forming a resist pattern on the inorganic film by using lithography, and using the resist pattern as a mask, Etching a film and the semiconductor silicon substrate to transfer a pattern; selectively depositing metal tungsten on the semiconductor silicon substrate; removing the inorganic film; Selectively removing from the water. Preferably, the inorganic film deposited on the semiconductor silicon substrate is a silicon oxide film, and the metal tungsten deposited on the semiconductor silicon substrate is 3 μm or more in thickness.

That is, the atomic mass of gold and tungsten is close to each other, and the range of electrons in tungsten is almost the same as that of gold as shown in FIG. Tungsten is deposited on the silicon surface to make it thinner. This tungsten has a thermal expansion coefficient and a thermal conductivity of 4.5 × 10 ^{−6 /} deg and 1.7, respectively.
cm.deg, which is very close to that of silicon. In addition, it has a high electronic conductivity, excellent mechanical strength, and can be used in a silicon semiconductor process.

[0011]

According to the present invention, it is possible to easily form a stencil mask for electron beam reduction transfer lithography, which has a small thickness and does not cause beam distortion due to charge-up, by the stencil mask forming process described above.
In particular, by using a silicon material and tungsten having a value close to both the coefficient of thermal expansion and the coefficient of thermal conductivity, there is no generation of thermal strain, and there is no need to deposit gold, so that it can be formed in a semiconductor silicon process. Can be. That is, by using tungsten-silicon, excellent mechanical strength, and dimensional stability due to temperature change,
A stencil mask with good thermal stability can be formed. Therefore, by using the present invention, it is possible to effectively form a thin stencil mask which is accurate and excellent in thermal stability.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the present invention will be described. According to the present invention, a thin and practical stencil mask having no thermal distortion can be formed by using metal tungsten. Since the atomic masses of silicon, tungsten, and gold are 28, 184, and 197, respectively, the range of electrons is the longest for silicon, and is substantially the same for tungsten and gold. Also, since silicon and tungsten have similar values for both thermal conductivity and thermal expansion coefficient,
It is not distorted by the heat of the electron beam.
Further, since tungsten can be used in a semiconductor silicon process and can be selectively deposited on a substrate, a pattern can be easily and accurately formed as a stencil mask for electron beam reduction transfer lithography.

Hereinafter, a method of forming a stencil mask according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a process sectional view of a stencil mask forming method according to an embodiment of the present invention. A 5 μm thick silicon oxide film was deposited as an inorganic film 12 on a semiconductor silicon substrate 11, and a resist pattern 13 was formed on the inorganic film using lithography. Using this resist pattern as a mask, the inorganic film was etched to obtain a pattern having an accurate and vertical cross-sectional shape (FIG. 1A). After removing this resist pattern,
Using the pattern of the inorganic film as a mask, metal tungsten 14 was selectively deposited to a thickness of 5 μm on the semiconductor silicon substrate 11 (FIG. 1B). Further, a silicon oxide film as an inorganic film was removed (FIG. 1C). Thereafter, the substrate is immersed in an ethylenediamine / pyrocatechol solution to dissolve and remove only the silicon region 11, thereby using the metal tungsten film 14 as a mask material as it is, having excellent mechanical strength, high thermal stability, and high thermal stability. (FIG. 1)
(D)).

As described above, according to this embodiment, by using metal tungsten as a mask material as it is, the stencil mask forming process can be greatly simplified, and even when the electron beam acceleration voltage is 50 keV. ,
It is possible to form a practical stencil mask for electron beam reduction transfer lithography capable of blocking electrons. Although a silicon oxide film is used here as the inorganic film, a silicon nitride film may be used.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. (FIG. 2) is a process sectional view of a stencil mask forming method according to a second embodiment of the present invention. A 2 μm thick silicon oxide film is deposited as an inorganic film 21 on a semiconductor silicon substrate 11, and a resist pattern 2 is formed on the inorganic film 21 by using lithography.
2 was formed. Using this resist pattern as a mask,
The inorganic film was etched, and the silicon substrate was further etched by about 3 μm to obtain a pattern having an accurate and vertical cross-sectional shape (FIG. 2A). After removing this resist pattern, the metal tungsten 2 is selectively formed on the semiconductor silicon substrate 11 using the pattern of the inorganic film as a mask.
3 was deposited to a thickness of 5 μm (FIG. 2B). Further, a silicon oxide film as an inorganic film was removed (FIG. 2C).
After that, the substrate was immersed in an ethylenediamine-pyrocatechol solution, and only the silicon region 11 was dissolved and removed, so that the metal tungsten film 23 was used as a mask material as it was, which had excellent mechanical strength and high thermal stability.
A stencil mask free from heat distortion was formed (FIG. 2D).

As described above, according to the present embodiment, by using metal tungsten as a mask material as it is, the stencil mask forming process can be greatly simplified, and it is free from distortion due to heat and is sufficiently thin. It is possible to form an accurate and practical stencil mask for electron beam reduction transfer lithography that can block electrons and does not cause a beam shift due to charge-up.
Although a silicon oxide film is used here as the inorganic film, a silicon nitride film may be used.

[0018]

As described above, according to the present invention,
By selectively depositing tungsten on a semiconductor silicon substrate and using this metal tungsten as it is, beam deviation due to electron charge-up, which has excellent mechanical strength, high thermal stability, no distortion due to heat, occurs. An accurate, thin, and highly practical stencil mask can be easily formed. In addition, tungsten has a heavy atomic mass and an electron range of 5 μm or less, so that a thin film having a mask thickness of 5 μm or less can sufficiently shield electrons, and is effectively used as a stencil mask for electron beam reduction transfer lithography. And can greatly contribute to the manufacture of ultra-high-density integrated circuits.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a stencil mask forming method according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a stencil mask forming method according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating an electron range with respect to an acceleration voltage of an electron beam.

FIG. 4 is a process sectional view of a conventional stencil mask forming method.

[Explanation of symbols]

 Reference Signs List 11 semiconductor silicon substrate 12 inorganic film 13 resist pattern 14 tungsten

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-76216 (JP, A) JP-A-4-370918 (JP, A) JP-A-4-196209 (JP, A) JP-A-4-196209 240719 (JP, A) JP-A-58-87821 (JP, A) JP-A-59-213131 (JP, A) JP-A-4-188645 (JP, A) (58) Fields investigated (Int. ⁶ , DB name) H01L 21/027 G03F 1/16 G03F 7/20

Claims (4)

(57) [Claims] A step of depositing an inorganic film on a surface of a semiconductor silicon substrate, forming a resist pattern on the inorganic film by using a lithography technique, and etching the inorganic film using the resist pattern as a mask to form a pattern. Transferring, exposing the semiconductor silicon substrate;
Selectively depositing metal tungsten on the semiconductor silicon substrate; and, after removing the inorganic film, selectively removing a silicon portion of the semiconductor silicon substrate from a back surface. Stencil mask forming method. A step of depositing an inorganic film on the surface of the semiconductor silicon substrate, forming a resist pattern on the inorganic film by using lithography, and using the resist pattern as a mask to form the inorganic film and the semiconductor silicon substrate. Etching and transferring a pattern, selectively depositing metal tungsten on the semiconductor silicon substrate, and selectively removing the silicon portion of the semiconductor silicon substrate from the back surface after removing the inorganic film. And a step of forming a stencil mask. 3. The stencil mask forming method according to claim 1, wherein the inorganic film deposited on the semiconductor silicon substrate is a silicon oxide film. 4. The stencil mask forming method according to claim 1, wherein the metal tungsten deposited on the semiconductor silicon substrate has a thickness of 3 μm or more.