JP2924946B2 - Semiconductor device and inspection method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a simultaneous bidirectional circuit and a method for inspecting a semiconductor device in a wafer state.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor device having a simultaneous bidirectional circuit of this type, for example, one having a circuit configuration shown in FIG.

Here, the semiconductor device 1 includes a simultaneous bidirectional circuit 2A, 2B comprising an output circuit 3A and an input circuit 4A, an output circuit 3B and an input circuit 4B, and an internal signal 6 and a simultaneous bidirectional circuit 2A, 2B and a plurality (four in this case) of data latches F /
F8 and a plurality (three in this case) of pads 9 serving as input / output terminals. In the semiconductor device 1, another interface output circuit 20 connected to a specific pad 9 is also mounted. Further, in the semiconductor device 1, a relay 33 is connected to a specific pad 9 as each part constituting a test device, and a relay 33 and a voltage dividing resistor 31 (one pad of one device) 9 and a relay 33 are connected between the relay 33 and the relay 33 as shown in the figure.
1 is connected to a power supply 32 for level application for varying the power supply voltage. That is, the semiconductor device 1 is configured so as to be inspected together with the test device.

FIG. 6 is an essential diagram for explaining a use operation when inspecting a semiconductor device in another wafer state in which a part of the semiconductor device 1 and a part of another semiconductor device are paired. FIG.

Here, a pair of simultaneous bidirectional circuits 2A and 2C are connected between the semiconductor devices 1A and 1C via a connection line 40, and the output circuit 3 of each of the simultaneous bidirectional circuits 2A and 2C is connected.
A and 3C output signals on the connection line 40, and the resulting voltage level on the signal line 40 is input to the input circuits 4A and 4C.
4C detects and transmits a signal to the other party and simultaneously receives the signal of the other party.

More specifically, the own output circuit 3A outputs a high level (= high potential 41) or a low level (= low potential 42), and the other output circuit 3C outputs a high level or a low level. When outputting, the level near the connection line 40 becomes a high level or a low level. Input circuit 4
A and 4C detect the level on the connection line 40 to detect the output signal level of each other.

When the own output circuit 3A outputs a high level or a low level and the counterpart output circuit 3C outputs a low level or a high level, the high potential 41 of the output circuit 3A or the output circuit 3C Lower potential 4 of
2 or the through current path 43 to the output circuit 3A.

At this time, the potential level of the connection line 40 is divided by the internal resistances of the output circuits 3A and 3C, and usually becomes an intermediate level with respect to a half of the absolute value of the sum of the high level and the low level. This intermediate level is input to input circuit 4
A or the input circuit 4C detects the output level, and determines the output level of the output circuit 3C or the output circuit 3A on the other side from the output level of the output circuit 3A or the output circuit 3C.

In the test apparatus in the wafer state of the semiconductor device shown in FIG. 5 having the simultaneous bidirectionality for performing the above-described operations, the measurement probe 30 is connected to the pad 9 on the semiconductor device 1 as described above. Then, a configuration is adopted in which a level application power supply 32 is connected on the tester via a voltage dividing resistor 31. The level application power supply 32 here may be applied as a single unit as shown in FIG. 5 and simultaneously applying a plurality of pins, or may be provided as many as the number of simultaneous bidirectional circuits and apply one pin each.

As a test method for the semiconductor device 1 shown in FIG. 5, each data latch F / F 8 having a scan path 7 configuration on the semiconductor device 1 is scanned in a scan path mode, and each data latch F / F 8 is scanned. Set the data in. The output circuit 3A of the simultaneous bidirectional circuit 2A, 2B,
3B, and the level application power supply 32 turns on the relay 33 only at the location where the simultaneous bidirectional circuit exists, and applies the high level or the low level. As a result, the level obtained by dividing the same value as the internal resistance of the output circuits 3A and 3B by the voltage dividing resistor 31 is set near the pad 9.

The input circuits 4A and 4B determine whether the level output from the level application power supply 32 is high or low in accordance with the method described in the use operation of FIG. Set to F / F8. The data is taken out again in the scan mode, and the tester checks whether or not each of the simultaneous bidirectional circuits 2A and 2B is functioning properly.

FIG. 7 is a flowchart showing this inspection procedure. In the inspection procedure, first, a scan is performed by starting a bidirectional circuit test, and each data latch F
Data is set in / F8 (step S1). next,
Output from the output circuits 3A and 3B (Step S2), the level is detected by the input circuits 4A and 4B, and the output circuits 3A and 3B
Is determined (step S3). Further, the input circuit 4
The determination results of A and 4B are set in each data latch F / F 8 (step S4). Thereafter, as a scan operation, the data of each data latch F / F 8 is taken out by the scan path 7 (step S5), thereby completing the procedure.

Further, another related technique is disclosed in Japanese Unexamined Patent Publication No.
There is a bidirectional bus inspection system disclosed in Japanese Patent No. 75849. FIG. 8 shows a circuit configuration to which this inspection method is applied. Here, the simultaneous bidirectional buses 102A and 102B provided in the logic package 101 are connected to each other by the connection cable 104 using the connector 103, and one output data is used as the other input inspection data, so that the simultaneous two-way buses 102A and 102B are used. Inspection data can be added without being aware of the directional bus, and the interface with the tester can be reduced by the number of simultaneous bidirectional buses.

[0014]

In the above-described inspection method for a semiconductor device having simultaneous bidirectionality, it is necessary to supply a through current flowing through the simultaneous bidirectional circuit, and to perform simultaneous bidirectionality in order to obtain high-speed operation. Since the internal resistance of the circuit is reduced, the through current becomes very large.

In addition, when a level application power supply is provided for each simultaneous bidirectional circuit and a level is applied, there is a drawback that a signal driver of a tester has a limit in supply current capability and cannot be supplied. Even when multiple levels are applied at the same time by the power supply for application, a level supply power supply with sufficient supply capacity must be prepared separately from the main power supply on the tester side in a situation where the number of pins of the semiconductor device is increased. There is a disadvantage that it does not.

Further, in any case, noise tends to occur due to the regulated impedance and impedance mismatch of the tester system, and in such a case, there is a disadvantage that high-speed testing becomes difficult.

The present invention has been made to solve such a problem, and its technical problem is that level application to a simultaneous bidirectional circuit is unnecessary, noise is hardly generated, and a high-speed test can be performed with a small current. And a method of inspecting the semiconductor device.

[0018]

According to the present invention, in a semiconductor device having a plurality of simultaneous bidirectional circuits connected to pads in a one-to-one manner, the pads are connected to each other in pairs so that one of the simultaneous bidirectional circuits is connected. A method for testing a semiconductor device using an output signal obtained from a bidirectional circuit as an input signal to the other simultaneous bidirectional circuit is obtained.

On the other hand, according to the present invention, there is provided a semiconductor device having a plurality of simultaneous bidirectional circuits connected one-to-one to pads, the pads being connected to each other on a scribe line.

[0020]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

First, the outline of the semiconductor device inspection method of the present invention will be briefly described. In this inspection method, pads are connected in pairs in a semiconductor device having a plurality of simultaneous bidirectional circuits connected one-to-one to pads, and the pads are connected.
An output signal obtained from one simultaneous bidirectional circuit is used as an input signal to the other simultaneous bidirectional circuit.

FIG. 1 shows a circuit configuration of a semiconductor device having such a simultaneous bidirectional circuit as an embodiment.

That is, the semiconductor device 1 can be inspected in the same manner as the circuit configuration shown in FIG. 5, and includes a simultaneous bidirectional circuit comprising an output circuit 3A and an input circuit 4A and an output circuit 3B and an input circuit 4B. Circuits 2A and 2B, four data latching F / Fs 8 for latching data between internal signal 6 and simultaneous bidirectional circuits 2A and 2B, and three pads 9 serving as input / output terminals One of the pads 9 is connected to another interface output circuit 20. Further, here, the pads 9 of the simultaneous bidirectional circuits 2A and 2B are wired so as to be connected and connected by a test wiring 10, and a test device such as the circuit configuration shown in FIG. 5 is not provided. .

Therefore, the inspection method here will be specifically described below. However, it is assumed that each data latch F / F 8 is configured to form the scan path 7 when the mode is switched. In the inspection method, first, the data latch F / F 8 is scanned to set data, and then the output circuits 3A and 3B of the simultaneous bidirectional circuits 2A and 2B output based on the data. As a result, in the vicinity of the test wiring 10 according to the inspection procedure as shown in FIG. 7, three levels (high, low, intermediate values) are taken. Input circuits 4A, 4
B detects the level in the vicinity of the test wiring 10 and determines the value of the output circuit 3B, 3A on the other side based on the output level of the output circuit 3A, 3B of its own simultaneous bidirectional circuit 2A, 2B. Output to This value is the data latch F /
It is set to F8 and taken out by scanning to test whether the simultaneous bidirectional circuits 2A and 2B are functioning properly.

Such a test operation conforms to the inspection procedure of the flowchart as shown in FIG.

FIG. 2 is a main part circuit diagram showing a semiconductor device according to another embodiment in which a part of the semiconductor device 1 and a part of the semiconductor device in another wafer state are paired.

In this semiconductor device, the pads 9 are connected to each other by a test wiring 10 on a scribe line 12 so as to form a pair between the simultaneous bidirectional circuits 2A and 2C of the adjacent semiconductor devices 1A and 1C. ing. The semiconductor device here can be applied to a case where a plurality of small-scale semiconductor devices are simultaneously tested.
The same applies to the case of the semiconductor device shown in FIG.

FIGS. 3A and 3B show layout diagrams to which the semiconductor device of each embodiment described above is applied. FIG. 3A shows the layout of the semiconductor device of the embodiment shown in FIG. 1 and FIG. ) Relates to the semiconductor device of another embodiment shown in FIG.

FIG. 3A shows an example of a layout.
Simultaneous bidirectional circuits 2A, 2 connected one-to-one to pads 9
B and pads 9 for the simultaneous bidirectional circuits 2A and 2B in the semiconductor device 1B having the two separate interface circuits 20 are connected to each other on the scribe line 11, and the other semiconductors facing each other with the scribe line 11 interposed therebetween. A semiconductor device having a configuration including the device 1D is shown. Incidentally, in the case of the semiconductor device here, the simultaneous bidirectional circuit 2A,
Only a pair of pads 9 which are output terminals of 2B are formed so as to be connected by a test wiring 10 on a scribe line 11.

In FIG. 3B, as an example of the layout, the simultaneous bidirectional circuit 2 connected to the pad 9 one-to-one.
A, 2B and two separate interface circuits 20. A specific one of the pads 9 in the semiconductor device 1E, and two simultaneous bidirectional circuits 2C and 2D connected one-to-one to other pads 9 of the same configuration. A semiconductor device having a configuration in which a specific one of pads 9 of a semiconductor device 1F having another interface circuit 20 is connected in a pair on a scribe line 12 by a test wiring 10 is shown.

By the way, in the manufacturing process using the semiconductor device laid out as described above, a wiring cutting process for separating the scribe lines 11 and 12 from the simultaneous bidirectional circuits at the time of dicing after the completion of the wafer inspection is performed.
For example, a semiconductor device 1G in which the test wiring 10 is removed as shown in the layout plan view of FIG. 4 is obtained.

[0032]

As described above, according to the present invention, the pads of a semiconductor device having a plurality of simultaneous bidirectional circuits connected one-to-one to the pads are connected in pairs, and one of the pads is connected simultaneously. Since the output signal of the bidirectional circuit is used as an input signal of the other simultaneous bidirectional circuit, it is not necessary to apply a level to the simultaneous bidirectional circuit from the outside, so that a conventional test apparatus is not required. As a result,
A high-speed test can be performed with a small current without being limited by the capability of a measuring device such as a tester, and noise is hardly generated. In addition, a test wiring for connecting a pair of pads is provided on the scribe line, and the test wiring is cut off in a wiring cutting step at the time of dicing after the test, so that it does not affect the subsequent steps in the manufacturing process. Proper and rational manufacture and inspection of a semiconductor device in a wafer state can be performed.

[Brief description of the drawings]

FIG. 1 shows a circuit configuration of a semiconductor device (a testable device) having a simultaneous bidirectional circuit according to an embodiment of the present invention.

FIG. 2 is a view for explaining a use operation when testing a semiconductor device according to another embodiment in which a part of the semiconductor device shown in FIG. 1 is paired with a part of another semiconductor device; FIG.

FIGS. 3A and 3B are plan views showing layouts to which the semiconductor device according to each of the above-described embodiments is applied, wherein FIG. 3A is related to the semiconductor device according to the embodiment shown in FIG. 1 and FIG. Another embodiment relates to a semiconductor device of another embodiment.

FIG. 4 is a layout plan view showing a semiconductor device after dicing obtained in a wiring cutting step of a manufacturing process using the semiconductor device laid out as shown in FIGS. 3A and 3B;

FIG. 5 shows a circuit configuration of a conventional semiconductor device (including a test device) having a simultaneous bidirectional circuit.

FIG. 6 is provided to explain a use operation when a semiconductor device in another wafer state in which a part of the semiconductor device shown in FIG. 5 is paired with a part of another semiconductor device is inspected; It is a principal part circuit diagram.

FIG. 7 is a flowchart showing an inspection procedure in the semiconductor device shown in FIG.

FIG. 8 shows a circuit configuration to which a bidirectional bus inspection system, which is another related art, is applied.

[Explanation of symbols]

 1, 1A-1G semiconductor device 2A-2D simultaneous bidirectional circuit 3A-3C input circuit 4A-4C output circuit 6 internal signal 7 scan path 8 data latch F / F 9 pad 10 test wiring 11, 12 scribe line 20 Interface output circuit 30 Measurement probe 31 Voltage divider 32 Power supply for level application 33 Relay 40 Connection line 41 Higher potential 42 Lower potential 43 Through current path 101 Logic package 102A, 102B Simultaneous bidirectional bus 103 Connector 104 Connection cable

Claims (2)

(57) [Claims] In a semiconductor device having a plurality of simultaneous bidirectional circuits connected to pads in a one-to-one manner, by connecting the pads in pairs, an output signal obtained from one of the simultaneous bidirectional circuits is converted into the other. A method for testing a semiconductor device, wherein the method is used as an input signal to a simultaneous bidirectional circuit. 2. A semiconductor device having a plurality of simultaneous bidirectional circuits connected one-to-one to pads, wherein the pads are connected to each other on a scribe line.