JP2906387B2 - PNP transistor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PNP transistor circuit, and more particularly, to reducing the influence of light on the operation of a PNP transistor in a monolithic integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 shows an equivalent circuit of a photocurrent compensating circuit of a PNP transistor in a conventional bipolar monolithic integrated circuit, and FIG. 4 shows a cross-sectional structure of the integrated circuit.

As shown in FIG. 4, due to the structure of an integrated circuit, an N-type epitaxial layer (22) and a P-type substrate layer (2
Since the parasitic photodiode (104) exists between 1), the parasitic photodiode (104) is connected between the base terminal of the PNP transistor (Q ₁₀₁ ) and the ground in the equivalent circuit of FIG. Become.

In FIG. 3, a PNP transistor (Q
₁₀₁ ) is present in an integrated circuit provided close to the same chip as the photoelectric conversion element, it is highly likely that a photocurrent ( _IPD104 ) will be generated in the parasitic photodiode (104) by receiving light. Become. Therefore, the base current (I _B101 ′) of the PNP transistor (Q ₁₀₁ ) is
Sum of the currents (I _B101) and photocurrent (I _{PD 104)} flowing from the ₁₀₁₎ to other circuits, that is, the current value indicated by the following equation. I _B101 ′ = I _B101 + I _PD104 Therefore, the base current (I _B101 ′) of the PNP transistor (Q ₁₀₁ ) increases, which greatly affects the characteristics of the circuit.

Conventionally, in order to reduce this effect, the inventor described in Japanese Patent Application Laid-Open No. 3-262153, and added a current mirror circuit using PNP transistors (Q ₁₀₂ ) and (Q ₁₀₃ ) as shown in FIG. by a current for correcting the photocurrent (I _{PD 104)} of the parasitic photodiode (104) (I _C103) poured into the base terminal of the PNP transistor (Q _101), the photocurrent due to light entering from the surface (I _{PD 104)} A correction circuit was proposed.

[0006]

However, in the above circuit,
As shown in FIG. 3, when the potential of the base terminal (B ₁₀₁ ) of the PNP transistor (Q ₁₀₁ ) changes due to the influence of peripheral circuits and the like, the collector-emitter voltage (V _CEQ103 ) of the PNP transistor (Q ₁₀₃ ) And the collector current (I _C103 ) of the PNP transistor (Q ₁₀₃ ) changes due to the Early effect. Therefore, the correction for the photocurrent ( _IPD104 ) is deviated, and the photocurrent cannot be corrected with high accuracy.

The current amplification factor hf of the PNP transistor
e is lower than that of the NPN transistor, typically 2
When the current amplification factor hfe is reduced to about 0 to 60, the mirror coefficient of the current mirror becomes smaller than 1, the collector current (I _C103 ) of the PNP transistor (Q ₁₀₃ ) changes due to the Early effect, and the photocurrent ( _IPD104 ) , The photocurrent cannot be corrected with high accuracy, and the intended purpose cannot be achieved.

[0008] The present invention solves such a problem, and PNP
When transistor base terminal (Q ₁₀₁₎ (B ₁₀₁₎ changes the potential, or PNP constituting a current mirror
Current amplification factor hfe of transistors (Q ₁₀₂ ) and (Q ₁₀₃ )
It is an object of the present invention to provide a PNP transistor circuit that can perform almost the same operation as when light is completely shut off even when the power supply voltage decreases.

[0009]

According to a first aspect of the present invention, there is provided a PNP transistor circuit having a first PNP transistor formed in a monolithic integrated circuit.
And a fourth PNP transistor, and both base terminals of the second and third PNP transistors, an emitter terminal of the fourth transistor, and the third transistor.
It has a connection point that connects only the collector terminal of the transistor ,
The collector terminal of the second PNP transistor is connected to the base terminal of the fourth PNP transistor, and the collector terminal of the fourth PNP transistor is connected to the first PNP transistor.
Connected to the base terminal of the NP transistor ,
And a current mirror circuit in which the emitter of the third PNP transistor is connected to a power supply .

The PNP transistor circuit according to claim 2 is configured so as to satisfy the following conditional expression in the PNP transistor circuit according to claim 2. S ₁ = S ₄ − (S ₂ + S ₃ ) × {(2 / hfe) (1 + 1 / hfe) +1} where S ₁ : the area of the base region of the first PNP transistor S ₂ : the second Area of base region of PNP transistor S ₃ : Area of base region of third PNP transistor S ₄ : Area of base region of fourth PNP transistor hfe: Area of second, third and fourth PNP transistors It is a current amplification factor.

[0011]

According to the PNP transistor circuit of the first aspect, the difference between the photocurrent generated by the parasitic photodiode of the fourth PNP transistor and the photocurrent generated by the parasitic photodiode of the second and third PNP transistors. The current that has flowed out is taken out as the collector current of the fourth PNP transistor using the current mirror effect,
It flows into the base terminal of the P transistor. This compensates for a change in the base current caused by the photocurrent generated by the parasitic photodiode of the PNP transistor, and reduces the influence of light on the operation of the first PNP transistor. Then, even when the potential of the base terminal of the first PNP transistor changes or the current amplification factors of the second, third, and fourth PNP transistors decrease, the collector current of the fourth PNP transistor is substantially constant. The current flows into the base terminal of the first PNP transistor, and is not affected by a change in the potential of the base terminal of the first PNP transistor and a decrease in the current amplification factor of the second, third, and fourth PNP transistors. Can be.

According to the PNP transistor circuit of the second aspect, in the PNP transistor circuit of the first aspect, a current flowing from a collector of the fourth PNP transistor to a base terminal of the first PNP transistor; The photocurrent generated by the parasitic photodiode of the first PNP transistor becomes substantially equal to the first PNP transistor.
Compensation for a change in the base current of the NP transistor is performed with high accuracy.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the PNP transistor circuit according to the present invention will be described below with reference to FIGS.
FIG. 1 shows an equivalent circuit of this embodiment, and FIG. 2 shows a cross-sectional structure of the integrated circuit of this embodiment.

In FIG. 1, the PNP transistor circuit is P
It has an NP transistor (Q ₁ ), and the emitter, collector and base terminals (E ₁ ), (C ₁ ) and (B ₁ ) of the transistor (Q ₁ ) are connected to a peripheral circuit and
The function as an NP transistor is provided to peripheral circuits. Further, the transistor (Q ₁₎ base terminal (B ₁₎ of which is connected to the collector terminal of the transistor (Q _4). On the other hand, the PNP transistors (Q ₂ ), (Q ₃ ) and (Q ₄ ) constitute a circuit for reducing the influence of light on the operation of the transistor (Q ₁ ).
_A constant current is applied to the base terminal of the transistor (Q ₁ ) even when the potential change of the base terminal (B ₁ ) of the transistor (Q ₁ ) or the variation in hfe of the PNP transistors (Q ₂ ), (Q ₃ ) and (Q ₄ ). (B ₁ ).

That is, a PNP transistor (Q ₂ ),
(Q ₃ ) and (Q ₄ ) are PNP transistors (Q ₂ ),
While connecting the emitter terminal of the collector terminal of transistor (Q ₄₎ of the base terminal and transistor _{(Q 3) (Q 3)} , and connecting the base terminal of the transistor collector terminal and transistor (Q ₂₎ (Q ₄₎ ing. And
The emitter terminals of the transistors (Q ₂ ) and (Q ₃ ) are respectively connected to a power supply (V _CC ) to form a current mirror circuit.

The collector terminal of the transistor (Q ₄ ) is connected to the base terminal (B ₁ ) of the transistor (Q ₁ ) as described above.

Here, as shown in FIG. 1, the connection point (a) is a connection point where only the collector terminal of the transistor (Q ₂ ) and the base terminal of the transistor (Q ₄ ) are connected, and the other connection points are connected. Absent.

In order to realize the above PNP transistor circuit in a monolithic integrated circuit, as shown in FIG. 2, an N-type epitaxial layer (22) is formed by a P-type substrate layer (2).
1) is formed. In the cross-sectional view of FIG. 2, the emitter and the collector are omitted for easy understanding. Each of the formed N-type epitaxial layers (22) corresponds to the bases of the transistors (Q ₁ ), (Q ₂ ), (Q ₃ ) and (Q ₄ ), respectively. A parasitic photodiode (5) between the substrate layers (21),
(6), (7) and (8) exist. Therefore, the transistors (Q ₁ ), (Q ₂ ), (Q
₃ ) Parasitic photodiodes (5), (6), (7), reversely biased between each base terminal of (Q ₄ ) and the ground point.
(8) will be connected respectively.

[0019] Thus, by the light from entering the integrated circuit chip (20), the transistor (Q ₁₎ parasitic photodiode (5) in photocurrent connected to the base terminal (B ₁₎ of (I _PD5) is The base current (I _B ′) changes due to the generation of the photo current (I _PD5 ). The transistors (Q ₂ ), (Q ₃ ), (Q ₄ )
Similarly for the parasitic photodiode connected to the base terminal (6), (7), (8) photocurrent _{(I PD6), (I PD7} ), (I PD8) is generated respectively.

Incidentally, transistors (Q ₂ ),
The base currents of (Q ₃ ) and (Q ₄ ) are (IB ₂ ),
(I _B3 ), (I _B4 ), and transistors (Q ₂ ),
Assuming that the current amplification factors of (Q ₃ ) and (Q ₄ ) are hfe, the following equations (1) to (6) hold. I _PD8 = I _C2 + I _B4 (1) I _E4 = I _B2 + I _B3 + I _C3 -I _PD6 -I _PD7 (2) I _C2 = I _C3 (3) I _B2 = I _B3 (4) I _C2 = hfeI _B2 (5) I _E4 = I _C4 + I _B4 (6) From the equations (3), (4) and (5), I _B2 = I _B3 = I _{C2 / hfe = I C3 / hfe} ··· (7) (7) substituting equation into the equation (2) _{I E4 = I B2 + I B3} + I C3 -I PD6 -I PD7 = I C2 +2 (I
_C2 / hfe) −I _PD6 −I _PD7 = I _C2 (1+ (2 / hf
e))-I _PD6 -I _PD7 I _C2 = (I _E4 + I _PD6 + I _PD7 ) / (1 + 2 / hfe) (8) Substituting the equations (6) and (8) into the equation (1) gives the photocurrent (I
_PD8 ) is as follows. I _PD8 = I _C2 + I _B4 = ｛(I _E4 + I _PD6 + I _PD7 ) / (1
+ (2 / hfe))｝ + I _B4 = ｛(I _C4 + I _B4 + I _PD6
+ I _PD7 ) / (1+ (2 / hfe))｝ + I _B4 = ｛2
(1+ (1 / hfe)) I _B4 + I _C4 + I _PD6 + I _PD7 } /
(1+ (2 / hfe)) where I _B4 = I _C4 / hfe is substituted I _PD8 = ｛2 (1 + 1 / hfe) (I _C4 / hfe) + I
_C4 + _IPD6 + _IPD7 ｝ / (1 + 2 / hfe) = ｛((2 /
hfe) (1 + 2 / hfe) +1 ) I _C4 + I _PD6 +
I _PD7 ｝ / (1 + 2 / hfe) (9) From this, the collector current (I _C4 ) is expressed by the following equation. I
_C4 = {I _PD8 (1 + 2 / hfe) −I _PD6 −I _PD7 } /
{(2 / hfe) (1 + 2 / hre) +1} (1
0) _{(However, I PD8> I PD6 + I} PD7)

This current (I _C4 ) is applied to the transistor (Q ₁ )
Into the base terminal (B ₁ ). Therefore, assuming that the current flowing from the base terminal (B ₁ ) of the transistor (Q ₁ ) to the peripheral circuit is (I _B ), the following relationship is obtained. _{I B '= I B + I} PD5 -I C4 ··· (11)

[0022] As can be seen from this equation, compensated for by change in the base current of the transistor (Q ₁₎ due to light penetration (I _B ') to (I _PD5) (10) formula of the current (I _C4), the transistor The effect of light on the operation of (Q ₁ ) can be reduced. In particular, the current (I _C4 ) is
_PD5 ), I _B ′ = I _B , and
The effect of light penetration can be eliminated. This can be done as follows.

Generally, the photocurrent generated by a photodiode is proportional to the area of the junction of the photodiode. In the case of this embodiment, the photocurrent generated in the parasitic photodiodes (5), (6), (7), and (8) for the same light is the same as that of the N-type epitaxial layer (22) shown in FIG. It is proportional to the respective bonding area with the mold substrate layer (21). Therefore, the junction area of the parasitic photodiode (5) (the area of the base region of the transistor (Q ₁ ))
(S ₁ ) and the junction area of the parasitic photodiode (6) (the area of the base region of the transistor (Q ₂ )) (S ₂ ), and the junction area of the parasitic photodiode (7) (the transistor (Q
₃ ) between the area of the base region (S ₃ ) and the junction area of the parasitic photodiode (8) (the area of the base region of the transistor (Q ₃ )) (S ₄ ). And transistors (Q ₁ ), (Q ₂ ),
(Q ₃ ) and (Q ₄ ) may be arranged close to each other. S ₁ = S ₄ − (S ₂ + S ₃ ) {(2 / hfe) (1 + 1 / hfe) +1} (12) In the above relationship, I _C4 = I _PD5 .

Therefore, the following relationship is obtained from equation (11). _{I B '≒ I B ··· (} 13)

With the above setting, the base current (I _B ′) of the transistor (Q ₁ ) is affected by the photocurrent (I _PD5 ) generated in the parasitic photodiode (5) due to the penetration of light from the equation (13). And the current (I _B ) flowing from the base terminal (B ₁ ) of the transistor (Q ₁ ) to the peripheral circuit.

In this circuit, even when the potential of the base terminal (B ₁ ) of the transistor (Q ₁ ) changes, the collector-emitter voltage (V _CEQ3 ) of the transistor (Q ₃ ) is changed by the transistor (Q ₄ ) of FIG. change in) is little, the transistor (Q ₄₎ of the collector voltage constant regardless of the current I and _PD8 -I _PD6 -I _PD7 (transistor (Q _2),
(Q _3), can be poured into the base terminal of the (Q ₄₎ current if the amplification factor hfe is large enough) transistors (Q _1).

The transistors (Q ₂ ), (Q ₃ ),
In the case where the current amplification factor hfe of (Q ₄₎ becomes e.g. low as 20 well, (10) than _{I C4 = 0.995I PD8 - {(} I PD6 -I PD7) /1.105} next, I _C4 Of the current amplification factor hfe can be reduced.

[0028]

According to the present invention, as described above, the P
According to the NP transistor circuit, it is possible to reduce the influence of the light entering from the outside on the operation of the PNP transistor, and the potential of the base terminal of the first PNP transistor changes or flows into the base terminal of the first PNP transistor. Even when the current amplification rates of the second, third, and fourth transistors that form the current decrease, it is possible to compensate for a change in the base current caused by the photocurrent.

According to the PNP transistor circuit of the second aspect, the change in the base current caused by the photocurrent generated by the parasitic photodiode can be compensated with high accuracy, so that the light is completely cut off. The PNP transistor can be operated in a state substantially the same as the state of the PNP transistor. In addition, even when a change in the base terminal potential of the first PNP transistor and a decrease in the current amplification factors of the second, third, and fourth transistors that form a current flowing into the base terminal of the first PNP transistor occur, A change in the base current caused by the current can be compensated with high accuracy.

Therefore, the PNP transistor circuit according to the present invention can be applied to a circuit which handles a small current inside an element which cannot block light entering from the outside or an element where the influence of the photocurrent due to the parasitic photodiode cannot be ignored. It is extremely effective for this.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of one embodiment of a PNP transistor circuit of the present invention.

FIG. 2 is a diagram showing a cross-sectional structure of an integrated circuit according to the embodiment.

FIG. 3 is a diagram showing an equivalent circuit of a conventional PNP transistor circuit that has performed photocurrent compensation.

FIG. 4 is a diagram showing a cross-sectional structure of an integrated circuit of a conventional PNP transistor circuit in which photocurrent compensation is performed.

[Description of References] (5), (6), (7), (8) Parasitic photodiode (Q ₁ ) First PNP transistor (Q ₂ ) Second PNP transistor (Q ₃ ) Third PNP transistor (Q ₄ ) Fourth PNP transistor (a) Connection point in current mirror circuit

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-262153 (JP, A) JP-A-1-123456 (JP, A) JP-A-60-124861 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H01L 21/8222 H01L 21/8222-21/8228 H01L 21/8232 H01L 27/06 H01L 27/08 H01L 27/082

Claims (2)

(57) [Claims] 1. A PNP transistor circuit formed in a monolithic integrated circuit and having a first PNP transistor, wherein the second, third and fourth PNP transistors are used to form the second and third PNP transistors. And a connection point where only the emitter terminal of the fourth transistor and the collector terminal of the third transistor are connected, and the collector terminal of the second PNP transistor is connected to the base terminal of the fourth PNP transistor. And a collector terminal of the fourth PNP transistor is connected to a base terminal of the first PNP transistor, and emitters of the second and third PNP transistors are connected.
A PNP transistor circuit comprising a current mirror circuit connected to a power supply . 2. The PNP transistor circuit according to claim 1, wherein the following conditional expression is satisfied. S ₁ = S ₄ − (S ₂ + S ₃ ) × {(2 / hfe) (1 + 1 / hfe) +1} where S ₁ : the area of the base region of the first PNP transistor S ₂ : the second Area of base region of PNP transistor S ₃ : Area of base region of third PNP transistor S ₄ : Area of base region of fourth PNP transistor hfe: Area of second, third and fourth PNP transistors Current amplification factor.