JP2902503B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interval timer required for an information processing apparatus having a plurality of processors to realize a multitasking function.

2. Description of the Related Art In an information processing apparatus having a multitasking function, a predetermined time elapses after a processor starts processing a certain task so that one task does not occupy the processor. The task to be executed next is selected according to the task priority, and control of the processor is switched from one task to the next task.
Switching is performed by generating an interrupt by an interval timer.

[0003]

2. Description of the Related Art A conventional information processing apparatus has only one interval timer (hereinafter simply referred to as "timer"). FIG. 6 is a diagram illustrating a conventional example. FIG.
, A system processor (hereinafter referred to as “SPU”) is connected to the external storage devices 37 to 39 and the display device 40.

At the same time, an instruction execution processor (hereinafter referred to as “IPU”) 31 to 33 and a main memory 3 are connected by a bus.
5 is connected. The main memory 35 has a system area 36 for storing information necessary for realizing the multitask function. As shown in FIG. 6, conventionally, only one timer 34 is provided.

[0005] The timer 34 notifies the SPU 30 at regular intervals to issue an interrupt request. The SPU 30 sequentially issues an interrupt request to each of the IPUs 31 to 33. At this time, the SPU 30 checks a corresponding interrupt mask (hereinafter, simply referred to as “mask”). As a result, if the mask is open, the SPU 30 raises the interrupt request until the IPUs 31 to 33 accept the interrupt request. If the mask is closed, suspend the interrupt request.

Each of the IPUs 31 to 33 accepts only one interrupt request when there are a plurality of interrupt requests at the same time, and holds the other unacceptable interrupt requests. When receiving the machine interrupt, the IPUs 31 to 33 notify the SPU 30 of predetermined information and execute the next task.

FIGS. 7 to 10 are flowcharts showing the processing in the IPU related to the multitask function. 7 to 10, numbers starting with a capital letter S indicate processing numbers. Details of the internal interrupt processing of the processing number S74 shown in FIG. 7 are shown in FIG. FIG. 9 shows details of the processing of the suspended interrupt of the processing number S76 shown in FIG. FIG. 10 shows details of the machine interrupt processing of the processing number S84 shown in FIG. Hereinafter, the process numbers are shown in parentheses after the description of each process shown in the flowchart.

In FIG. 7, the IPU fetches an instruction from the main memory (S70) and interprets the fetched instruction (S7).
1) The interpreted instruction is executed (S72). Subsequently, it is checked whether or not there is an internal interrupt request from the SPU 30 (S73). As a result, if there is an internal interrupt, an internal interrupt process is performed (S74). SPU30
If there is no internal interrupt in the IPU, it is checked whether the mask has been opened by the execution of the previously executed instruction (S72) (S75). If the mask is open, the process proceeds to the suspended interrupt processing (S76).

In FIG. 8, the IPU checks whether the internal interrupt is a timer interrupt by a timer (S80).
As a result, if it is not a timer interrupt, other interrupt processing not directly related to the multitask function (S8)
Perform 6). If it is a timer interrupt, it is checked whether the mask is open (S81). If the mask is open, the interrupt request from the SPU is released (S82), and a machine interrupt process (S84) is performed. If the mask is closed, the timer interrupt is suspended and the timer suspension flag is turned on (S85).

In FIG. 9, the IPU first reads a timer hold flag (S90). Then, it is checked whether or not the timer hold flag is turned on (S91). If the timer hold flag is on, SP
The interrupt request from U is released (S92), and the turned-on timer hold flag is turned off (S93), and a machine interrupt process (S94) is performed.

In FIG. 10, the IPU first closes the mask (S100) so as not to accept another interrupt. Next, task scheduling processing is performed (S
101). Here, a task to be executed next is selected, and an environment for executing the task is prepared. Subsequently, an initial value is set in the timer (S102). The timer starts measuring the predetermined time again to generate the next timer interrupt. Finally, the process returns from the machine interrupt (S103) and the execution of the next task is started.

[0012]

In the information processing apparatus as described above, the SPU must issue an interrupt request to each IPU in order. Also,
In order to switch tasks, it is necessary to stop each IPU once and restart it. Therefore, there is a problem that as the number of IPUs increases, the load for interruption increases and system efficiency deteriorates.

Further, not all instructions executed by the IPU change the mask. Some do not change the mask. However, conventionally, since the SPU does not know what instruction the IPU has executed, it has checked whether or not the mask has changed for all the instructions after executing the instruction. That is, there is a problem that unnecessary processing is performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to smoothly process a timer interrupt in a multiprocessor system having a multitasking function.

[0015]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims. That is, the present invention has a system processor and a plurality of instruction execution processors, data by an internal interrupt
The information processing apparatus having a multi-tasking function to switch the disk, the plurality of instruction execution processors, internal
Interrupt execution means for executing an interrupt in response to an interrupt request
And an interrupt requesting an internal interrupt every predetermined time
Timer and the executed instruction determine the open / closed state of the interrupt mask.
Command determining means for determining whether the command is a command to be changed, and a command
The determining means determines that the instruction executed by the instruction execution processor is
Only when it is determined that the mask is changed,
Judge the open / close state of the interrupt mask corresponding to the interrupt request
Interrupt request by the open / close determining means
When it is determined that the interrupt mask corresponding to is closed
Means for suspending the interrupt request, and
The interrupt execution means interrupts the holding means.
Request is suspended and the interrupt
If the mask corresponding to the request is determined to be open
The interrupt request held by the holding means
This is an information processing device that executes an interruption by the user .

[0016]

FIG. 1 is a diagram illustrating the principle of the present invention. 1, the SPU 1 is connected to external storage devices 11 to 13 and a display device 14. At the same time, IPU2
To 4 and the main memory 9. In the main memory 9,
There is a system area 10 for storing information necessary for realizing the multitask function. And each processor 1 to
4 has timers 5-8.

The IPU implements a multitasking function by switching tasks according to an interrupt request issued by its own timer. Upon detecting an interrupt request from the timer, the IPU checks opening / closing of the mask, means for holding the interrupt request, means for releasing the hold of the interrupt request, means for checking whether the executed instruction changes the mask, Interrupt control is performed by using a means for checking the presence or absence of the interrupt request, a means for canceling the interrupt request, a means for performing a machine interrupt if necessary, and a means for setting a predetermined time in a timer.

[0018]

FIG. 2 is a diagram showing a configuration example of a timer. 2, the IPU 15 sets a predetermined time in a timer 16. The timer 16 sets the value of I when a predetermined time has elapsed.
An interrupt request signal is output to PU15. A predetermined time output from the IPU 15 through the receiver circuit 24 is set in the timer counter 17. This set time can be read by the IPU 15 through the selector 18 and the driver circuit 25. The set time of the timer counter 17 is A
It decreases according to the countdown signal output from the ND circuit 20.

When the set time is reduced and reaches a certain value, the check circuit 19 detects the value and outputs a check signal.
Here, the value is set to zero. The output of the AND circuit 21 is turned on by this check signal, and the flip-flop (hereinafter referred to as “FF”) circuit 22 is set.

The output of the FF circuit 22 is supplied to a driver circuit 26
And is output to the IPU 15 as an interrupt request signal. The FF circuit 22 is reset when the output of the OR circuit 23 is turned on by a timer value set signal for setting a predetermined time in the timer counter 17 or an interrupt request release signal for releasing an interrupt request. The countdown signal described above is equal to the timer clock signal while the timer valid signal is on, and is invalid while the timer valid signal is off.

FIG. 3 is a timing chart for explaining the operation of the timer shown in FIG. In FIG. 3, the timer count value indicates a time set in the timer counter 17. The J terminal input indicates a signal that is an output of the AND circuit 21 and is input to the J terminal of the FF circuit 22. The K terminal input is an output of the OR circuit 23 and indicates a signal input to the K terminal of the FF circuit 23. In FIG. 3,
It is assumed that the timer valid signal is on.

Since the timer valid signal is ON, the countdown signal becomes equal to the timer clock signal. The timer count value decreases each time a pulse of the countdown signal is received. The clock signal is the timer counter 1
7 and the operation timing of the FF circuit 22. The value output from the timer counter 17 changes from “1” to “0” by the pulse of the clock signal indicated by the letter Ta. The check signal is turned on by this “0”.

The K terminal input is the logical product of the countdown signal and the check signal, and turns on when both signals are on. The FF circuit 22 operates according to the pulse of the clock signal indicated by the alphabetical character Tb, and is set when the J terminal input is turned on. Therefore, the interrupt request signal turns on.

Thereafter, the FF circuit 22 is operated by the pulse of the clock signal indicated by the alphabetic character Tc. At this time, if the timer value set signal is on, the FF circuit 22 is reset by turning on the K terminal input. Therefore, the interrupt request signal is turned off, and the timer counter 17 is set to a predetermined countdown value.

FIG. 4 is a flowchart showing the firmware control of the IPU. Processing number S4 shown in FIG.
Details of the processing of each instruction of No. 2 are shown in FIG. Also,
The details of the internal interrupt processing of the processing number S44 are shown in FIG. 8, and the description is as described above. FIG. 5 is a flowchart showing the processing of each instruction. The details of the processing of the interrupt interrupted with the processing number S53 shown here are shown in FIG. 9, and the description thereof is as described above. However,
In the present invention, the issue of an interrupt request is based on the IP
Since U is a timer, the interrupt request to be released is from that timer.

In FIG. 4, the IPU retrieves an instruction from the main memory (S40) and interprets the retrieved instruction (S4).
1) Perform processing of each interpreted instruction (S42). Subsequently, it is checked whether or not there is an internal interrupt (S43). As a result, if there is an internal interrupt, an internal interrupt process is performed (S44), and then the next instruction is fetched (S44).
40). If there is no internal interrupt, the next instruction is taken out as it is (S40).

In FIG. 5, the IPU executes the interpreted command (S50). Then, it is determined whether the executed instruction is an instruction for changing the mask (S51). If the instruction is to change the mask, it is checked whether or not the mask has been opened by the execution of the previously executed instruction (S50) (S52). As a result, if the mask is open, the interrupted interrupt processing (S53) is entered.

[0028]

As described above, according to the present invention,
Since each IPU has a timer, it is possible to distribute the load for interruption. Further, since the opening / closing of the mask is not checked after the execution of the instruction which does not change the mask, unnecessary processing is not required. Thus, the present invention has the advantage of significantly improving system efficiency.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a timer.

FIG. 3 is a timing chart showing the operation of the timer shown in FIG. 2;

FIG. 4 is a flowchart illustrating firmware control of an IPU.

FIG. 5 is a flowchart showing the processing of each instruction.

FIG. 6 is a diagram illustrating a conventional example.

FIG. 7 is a flowchart showing a conventional firmware control.

FIG. 8 is a flowchart showing an internal interrupt process.

FIG. 9 is a flowchart showing the processing of a suspended interrupt.

FIG. 10 is a flowchart showing a machine interrupt process.

[Explanation of symbols]

 1,30 SPU 2-4,15,31-33 IPU 5-8,16,34 Timer 9,35 Main memory 10,36 System area 11-13,37-39 External storage device 14,40 Display device 17 Timer counter Reference Signs List 18 selector 19 check circuit 20, 21 AND circuit 22 FF circuit 23 OR circuit 24 receiver circuit 25, 26 driver circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/46 G06F 15/163

Claims (1)

(57) [Claims] 1. A system having a system processor and a plurality of instruction execution processors, wherein a task is switched by an internal interrupt.
Met the information processing apparatus including a multitask function to obtain
Thus , the plurality of instruction execution processors are configured to respond to an internal interrupt request.
An interrupt executing means for executing an interrupt by an interrupter, and an interval timer for requesting an internal interrupt at predetermined time intervals.
And the instruction that the executed instruction changes the open / close state of the interrupt mask.
Instruction determining means for determining whether the instruction is executed or not, and the instruction determining means
When it is determined that the instruction that has changed changes the mask
Only when the interrupt mask corresponding to the interrupt request is open or closed
Opening / closing determining means for determining whether an interrupt request
If it is determined that the mask is closed,
And an interrupt executing means for holding the interrupt request in the interrupting means.
In response to the interrupt request by the open / close determination means.
If it is determined that the corresponding mask is open,
Execute the interrupt due to the interrupt request
The information processing apparatus characterized by rows.