JPH05204867A - Timer interruption control system in symmetric multiprocessor system - Google Patents

Abstract

PURPOSE:To effectively use a processor with low priority and to reduce hardware quantity in a symmetric multiprocessor system. CONSTITUTION:One timer interruption mechanism 30 equipped with a priority register 31 by which the priority of each processor in a system can be set from an arbitrary processor, a timer mechanism 32 by which an arbitrary timer value can be set from the processor using timer interruption, and a timer interruption circuit 33 is provided in the system. The timer interruption circuit 33 judges the processor with the lowest priority at that time when a time represented by a timer value is counted in the timer mechanism 32 and a timer interruption detection signal 320 is outputted from the mechanism 32 by referring to the priority register 31, and turns on an interruption signal proper to the processor out of the timer interruption signals 330-333, and reports the timer interruption. Thereby, the processor with the lowest priority can perform interruption processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer interrupt control system in a symmetric multiprocessor system in which a plurality of processors operate equally.

[0002]

2. Description of the Related Art Conventionally, a symmetric multiprocessor processing type computer in which a plurality of processors operate in an equal manner,
That is, a symmetric multiprocessor system is known.
In this type of system, conventionally, a timer interrupt mechanism is provided for each processor. Each of these timer interrupt mechanisms could operate independently.

Further, each processor can set a timer value (time setting) in a timer interrupt mechanism provided in each processor. If a timer interrupt is generated from the timer interrupt mechanism, the processor in which the interrupt occurred (the processor having the timer interrupt mechanism in which the interrupt occurred) interrupted the process being executed and performed the interrupt process.

The above-mentioned timer interrupt is mainly used for real-time processing which is performed by the OS (operating system) at regular time intervals. The timer interrupt mechanism used in this OS was one on any processor and never used multiple timer interrupt mechanisms.

[0005]

As described above, in the conventional timer interrupt control method in the symmetric multiprocessor system, when the timer interrupt occurs, the interrupt time is set and the interrupt processing is performed only in the processor in which the interrupt occurs. Could not be done. For this reason,
The processor in which the interrupt has occurred has to perform interrupt processing regardless of the priority of the task being executed, and has to interrupt the processing of that processor.

Further, in the above-mentioned conventional system, the timer interrupt mechanism is prepared for the number of processors, but the timer interrupt mechanism actually used is one of them, and the system is redundant. There was a problem.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a processor for processing a task having the lowest priority (or not in a processing state) with a timer interrupt mechanism in the system. A timer interrupt control method in a symmetric multiprocessor system capable of selectively generating a timer interrupt, performing timer interrupt processing without interrupting the processing of tasks with high priority, and reducing the amount of hardware. Especially.

[0008]

According to the present invention, a timer means capable of setting an arbitrary timer value from an arbitrary processor in a symmetric multiprocessor system and a priority order of processing being executed by each processor in the system. When the priority setting means for setting the processor priority and the detection signal indicating that the set time has elapsed are output from the timer means, the processor having the lowest priority at that time is determined from the setting contents of the priority setting means. The processor is provided with a timer interrupt control means for notifying a timer interrupt so that the interrupt processing associated with the timer interrupt is performed by the processor with a lower priority.

[0009]

In the above arrangement, any processor in the system sets, in the priority setting means, the processor priority determined by the priority of the process being executed by each processor. The processor priority changes according to the system status and is reset each time.

A processor using a timer interrupt sets an arbitrary timer value in a timer means common to each processor. The timer means counts the time (set time) indicated by the set timer value, and when detecting that the set time has elapsed, outputs a detection signal to that effect.

When the detection signal is output from the timer means, the timer interrupt control means determines the processor having the lowest priority at that time from the setting contents of the priority setting means, and notifies the processor of the timer interrupt. The low-priority processor, which has received the timer interrupt from the timer interrupt control means, interrupts the processing of the task under execution, and starts the timer interrupt processing.

In this way, when the processor using the timer interrupt is executing a task with a high priority, the low-priority processor processes the interrupt without interrupting the task processing. Is possible.

[0013]

1 is a block diagram showing an embodiment of a symmetric multiprocessor system to which the present invention is applied.

In FIG. 1, 1-0, 1-1, 1-2, and 1-3 are processors having processor numbers # 0, # 1, # 2, and # 3 for forming a symmetric multiprocessor system. ,
Reference numeral 2 is a memory shared by the processors 1-0 to 1-3. The memory 2 has an OS (operating system) 2
0 is placed.

3 is a system controller for controlling the entire multiprocessor system, and 4 is processors 1-0 to 1
-3, the system bus 4 to which the memory 2 and the system controller 3 are connected. The system control unit 3 includes one timer interrupt mechanism 30 directly related to the present invention.

The timer interrupt mechanism 30 is provided for each processor 1
It has a priority order register 31 for holding the priority order of -0 to 1-3. The priority register 31 is connected to the system bus 4 and is writable by any processor 1-i (i is 1 to 3) via the system bus 4.

The timer interrupt mechanism 30 also has a timer mechanism 32 connected to the system bus 4. The timer mechanism 32 includes a timer register (not shown) in which an arbitrary timer value can be set from the arbitrary processor 1-i via the system bus 4, and the register setting value is subtracted at a constant time interval. Then, it detects that the value becomes “0”,
A timer interrupt detection signal 320 to that effect is output.

The timer interrupt mechanism 30 further has a timer interrupt control circuit 33. This timer interrupt control circuit 33
Is a timer interrupt detection signal 320 from the timer mechanism 32.
In response, the processor having the lowest priority at that time is discriminated from the setting contents of the priority register 31, and the timer interrupt is notified to the processor. The timer interrupt control circuit 33 is connected to the processors 1-0 to 1-3 by timer interrupt signals 330 to 3333. The timer interrupt signals 330 to 333 are used to notify from the timer interrupt control circuit 33 that a timer interrupt has occurred in the processors 1-0 to 1-3.

Next, the operation of the configuration of FIG. 1 will be described. First, according to the instruction from the OS 20, the processors 1-0 to 1-3
One of the processors 1-0 to 1-3 for the priority register 31 in the timer interrupt mechanism 30.
A value indicating the processor priority according to the priority of the task being executed is set via the system bus 4. The processor priority value is composed of, for example, a sequence of processor numbers arranged in order of priority. Therefore, if the processor (# 0) 1-0 has the highest priority, the processor (# 2) 1-2, the processor (# 1) 1-1, and the processor (# 3) 1-3 are given priority in this order. If the rank becomes lower, the priority register 31 stores “0213”.
Is set.

The priorities of the above-mentioned processors 1-0 to 1-3 change according to the status of the system, and can be rewritten by an instruction from the OS 20 each time. If there is a processor that is not performing processing, that processor has the lowest priority.

Now, under the control of the OS 20, for example, the processor 1-0 uses a timer interrupt. In this case, the processor 1-0 sets the timer value indicating the interval time in the timer mechanism 32 (the timer register included therein) in the timer interrupt mechanism 30 via the system bus 4. This timer value is, for example, the timer mechanism 3
2 subtracts the timer register setting value every 1 millisecond (-1)
If you want to use the timer interrupt service of 0.1 seconds when the hardware configuration is
("64" in hexadecimal notation). Further, the processor 1-0 (which uses the timer interrupt) writes the storage destination address of the information necessary for the timer interrupt processing at the specific address on the memory 2.

In the timer mechanism 32, when the timer value is set in the timer register, the subtraction operation is performed to decrement the contents of the register by -1 at a constant time interval (1 millisecond interval in the above example). Eventually, when the value of the timer register in the timer mechanism 32 becomes "0", that is, when the time indicated by the set timer value elapses, the timer mechanism 32 issues a timer interrupt detection signal 320 for notifying that effect to the timer interrupt detection signal 320. Output to the control circuit 33.

When the timer interrupt control circuit 33 receives the timer interrupt detection signal 320 from the timer mechanism 32, the setting contents of the priority register 31 (processor priority value).
And the processor with the lowest priority at that time (the processor with the lowest priority task processing or the processor with no processing) is determined from the contents.

Next, the timer interrupt control circuit 33 turns on the timer interrupt signal of the timer interrupt signals 330 to 333, which is connected to the processor determined to have the lowest priority, and notifies the processor of the timer interrupt. ..

Therefore, as described above, if "0213" is set in the priority register 31, the processor with the processor number # 3, that is, the processor 1-3, is valid from the timer interrupt control circuit 33. The timer interrupt signal 333 is output to notify the timer interrupt.

The processor in which the timer interrupt is entered, that is, the processor 1-3 having the lowest priority, suspends the processing of the task under execution, and immediately if no task processing is performed. , Starts timer interrupt processing on behalf of processor 1-0. At this time, the processor 1
-3 refers to the specific address of the memory 2 to obtain a storage destination address of information required for timer interrupt processing, and executes timer interrupt processing based on the information specified by the address.

As described above, in this embodiment, the processor that sets the timer interrupt and the processor that receives the timer interrupt are not necessarily the same, and the priority is lower than the processor (1-0) that sets the timer interrupt as described above. If there is a processor, the processor (1-3) with the lowest priority among them performs interrupt processing. For this reason,
Processing of a task with a high priority in the processor (1-0) to which the timer interrupt is set is not hindered by the timer interrupt processing.

[0028]

As described in detail above, according to the present invention,
One timer interrupt mechanism with a new configuration is provided in the system,
For this timer interrupt mechanism, time is set to use the timer interrupt from any processor, and when the set time has elapsed, the task with the lowest priority at that time is processed ( Interrupts are selectively notified from the timer interrupt mechanism to processors that are not in the processing state. Therefore, it is not always the same as the processor that set the timer interrupt, and the interrupt process must be performed by a processor with a lower priority. Can If a processor with a timer interrupt is executing a task with a high priority, that processing is not interrupted,
The processing efficiency is improved.

Further, since only one timer interrupt mechanism needs to be provided in the system, the amount of hardware can be reduced as compared with the conventional redundant configuration in which a timer interrupt mechanism is provided for each processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a symmetric multiprocessor system to which the present invention is applied.

[Explanation of symbols]

1-0 to 1-3 ... Processor, 2 ... Memory, 3 ... System controller, 4 ... System bus, 20 ... OS (operating system), 30 ... Timer interrupt mechanism, 31 ... Priority register, 32 ... Timer mechanism, 33 ... Timer interrupt control circuit, 320 ... Timer interrupt detection signal, 330-3
33 ... Timer interrupt signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichiro Suzuki No. 1 Toshiba-cho, Fuchu-shi, Tokyo Toshiba Corporation Fuchu factory

Claims (1)

[Claims] 1. A symmetric multiprocessor system in which a plurality of processors operate in equal proportion, a timer means capable of setting an arbitrary timer value from any of the processors and detecting a lapse of time indicated by the set timer value. And a priority setting means for setting a processor priority according to the priority of the processing being executed in each processor, and a detection signal from the timer means and receiving the detection signal from the timer setting means, A symmetry characterized in that it has a timer interrupt control means for discriminating a processor with a low priority and notifying the processor of a timer interrupt, and that the interrupt processing associated with the timer interrupt is performed by the processor with a low priority. Interrupt control method for distributed multiprocessor system.