JPH045729A - Processor device - Google Patents

Abstract

PURPOSE:To construct a highly reliable system capable of preventing surely the destruction of data by detecting that a stack pointer overflows by hardware, and interrupting the execution of an instruction. CONSTITUTION:At the time of the execution of a program, the maximum address of a stack area assigned beforehand to a memory 1 is set, and this value is set in a stack address register 8 by the program. As for the stack pointer 6, the address it shows is always compared with the set value of the register 8 by an address comparison circuit 9. When the address exceeds the set value, interruption is generated from an interruption generation circuit 10 to an instruction execution control part 4 based on the compared result of the circuit 9, and the control part 4 executed and so on. Through above- mentioned operation, the overflow of the pointer 6 is detected, and the destruction of a memory area other than stack can be prevented by executing the interrupting processing of the program or the new assignment of another memory by a processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processor device, and particularly to an overflow detection function for detecting an overflow of an address storage area of a stack pointer.

[Prior Art] FIG. 2 is a block diagram of a conventional processor control device.
In the figure, (1) is a memory that stores program data, information such as return addresses when an interrupt occurs, and (2)
is the memory and processor control unit interface control unit, (3) is the instruction analysis unit, (4) is the instruction execution and interrupt control unit, (5) is the program counter, (6) is the stack pointer, and (a) is the memory. This is an address control circuit.

Next, the operation will be explained. Program instructions are given by the address indicated by the program counter (5).
The memory (1) is connected through the bus interface control unit (2).
). The read instructions are sent to the instruction analysis section (
3), and the instruction execution unit (4) executes arithmetic processing, etc. At this time, if the instruction is a subroutine call, the program counter (5) is newly set to the destination address, but the original program address at that time,
Information for re-execution upon return from a subroutine such as program status is written to the address indicated by the stack pointer. The address held by the stack pointer is sequentially added each time it is written to indicate the latest stack pointer. The operation is similar for interrupts processed by the instruction execution control unit (5). Furthermore, when returning to the original program from a subroutine or interrupt processing routine, information such as an address for re-execution is read from the stack pointer. The address held by the stack pointer is decremented each time it is read, and indicates the latest stack address after being read.

(Problems to be Solved by the Invention) Since the conventional processor device is configured as described above, the address of the stack pointer is added every time a subroutine call or an interrupt occurs. Therefore, when the nesting of subroutines increases, or when a large number of interrupts occur, the memory area assigned as a stack is exceeded, and other assigned areas are destroyed. Or, if there is no physical memory, problems such as memory access errors occur.

This invention was made in order to solve the above-mentioned problems, and its purpose is to provide a processor device that can detect when the stack memory area assigned to the stack pointer exceeds the address. do.

[Means for Solving the Problems] A processor device according to the present invention includes a program counter that outputs an address signal to a memory in which each instruction is stored, reads and compares the instructions, and an instruction execution counter that executes the read instructions. a stack pointer that stores the return address when the instruction is a subroutine call that requires a return address; an address comparison circuit that determines whether the storage area of the stack pointer overflows outside the specified area due to the return address; and an interrupt generation circuit that outputs an interrupt signal indicating an overflow to the instruction execution section.

(Operation) According to the present invention, when the address comparison circuit detects that the stack pointer overflows, it activates the interrupt generation circuit, transmits the overflow to the instruction execution unit currently executing the instruction, and Preventing Program Runaway by Interrupting Execution, etc. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a memory device, (2) a bus interface control unit, (3) is an instruction analysis unit, (4) is an instruction execution control unit, (5) is a program counter, (6) is a stack pointer, and (6) is a stack pointer. ) is an address control unit, (8) is a stack pointer address register, (9) is an address comparison circuit that compares the contents of the stack pointer (6) and the stack address register (8), and (10) is an address comparison circuit (9). From the comparison result, it is found that this is an interrupt generation circuit that generates an interrupt to the instruction execution control unit (4) when an overflow is detected.

Next, the operation will be explained based on the above configuration.

First, when the program is executed, the maximum address of the stack area previously assigned to the memory (1) is set, and the value is set in the stack address register (8) by the program. The stack pointer (6) operates in the same manner as in the prior art, but the address it indicates is always compared with the set value of the stack address register (8) by the address comparison circuit (9). If the address exceeds the set value, the instruction execution control unit (4) is sent from the interrupt generation circuit (10) based on the comparison result of the address comparison circuit (9).
An interrupt is generated, and the instruction execution control unit (4) takes measures such as interrupting the program being executed. As a result of the above operations, an overflow of the stack pointer (6) is detected, and the processor interrupts the program or allocates another memory.
Destruction of memory areas other than the stack can be prevented.

In the above embodiment, the maximum value of the memory address assigned to the stack pointer (6) is held in the stack address register (8), or the address is held in the ROM, or fixed by a logic circuit. It is also possible.

Furthermore, when using a plurality of stack pointers, the same effect can be achieved by having the same number of corresponding stack address registers.

[Effects of the Invention] As described above, according to the present invention, since the hardware is configured to detect an overflow of the stack pointer and interrupt instruction execution, data destruction due to program runaway can be prevented before the overflow occurs. Since measures are taken by the instruction execution unit to prevent data destruction, it is possible to construct a highly reliable system that can reliably prevent data destruction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a processor device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional device. In the figure, (1) is a memory, (4) is an instruction execution control unit, (5) is a program counter, (6) is a stack pointer, (9) is an address comparison circuit, and (1o) is an interrupt generation circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] Outputs an address signal to the memory where each instruction is stored,
A program counter that reads instructions, an instruction execution unit that executes the read instructions, a stack pointer that stores the return address if the instruction is a subroutine call that requires a return address, and an area where the storage area for the stack pointer is defined by the return address. 1. A processor device comprising: an address comparison circuit that determines whether an overflow occurs; and an interrupt generation circuit that outputs an interrupt signal indicating an overflow to the instruction execution section when determining an overflow.