JPH0114611B2 - - Google Patents

Abstract

Each process in a multi-process computing system using so-called capabilities may have associated with it a process dumpstack protected by the capability mechanism. The functions of this dumpstack are (i) to provide the state of the process at the point at which it was suspended and (ii) to stack (or nest) information relating to the invoked procedures (i.e. sub-routines) of the process. Thus there is a fixed sized portion containing principally the machine registers, the indicators and the watchdog timer values and a variable sized portion containing information related to each nested procedure. Each stack link is of fixed size and contains three items:- relativised instruction address, the code block capability and process capability pointer list block capability. This arrangement is enhanced to allowtwo additional classes of information to be stored in each link namely (a) an indication of the data and capability registers preserved during the domain change procedure and (b) descriptors for local storage segments. The use of descriptors for local storage allows a pool of storage particular to the process to be allocated on a segmented basis with the security of the capability mechanism extended into that local storage area. The descriptors for local storage segments resemble closely SCT entries (i.e. they contain sumcheck, base and limit values) and they are relative to a new protected stack, the local store stack, which is referenced by a hidden capability register C(L). The processor module is provided with a new instruction "subset local store" for use in local store segment allocation and automatic de-allocation occurs when a return is made from the procedure in which the local segment was allocated. Such allocation and de-allocation mechanisms use the indications which takes the form of a primary descriptor held in the most significant eight bits of the IAR word. This descriptor is allocated as follows:- (i) zero, no stacked registers or local segments allocated, (ii) m.s.b. = 1, stacked registers to be passed and (iii) I.s.b. 1-7 = 1, indicates the number of local store segments allocated. Associated with the stacked register set is a one word descriptor which indicates the registers stacked.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to multiprogramming data processing systems, and more particularly to arrangements provided for storing operating parameters of a process during process interruptions (or pauses).

To obtain a system that is easy to develop and maintain, the program's control set is divided into system routines and application programs.
Each application program processes a limited set of tasks under the supervision of system routines.

In real-time environments requiring fast response times, any application program can be paused and another program can begin processing urgent tasks. Each application program can be launched several times to handle a series of similar tasks. Each boot, or so-called process, executes instructions from a common program but uses a separate working database. As a result, any number of processes can exist,
One is active and the other is paused, resulting in multiprogramming. System routines can run like processes, but some of them can be suspended or restarted to operate as called routines.

To maintain fast response, most or all system routines and application programs reside permanently in fast access memory. The remaining fast access memory holds permanent and dynamic data necessary for the program to perform its tasks and the work areas associated with each process. Infrequently used programs and large but infrequently accessed files can be kept in secondary storage and moved to fast access memory if desired. Each process is provided with a so-called process dump stack, in which the working parameters of the process at the time of suspension of the process are stored.

Such a system is described in KJ Hamer, Volume 27, System Technology, November 1977, pages 26-34.
References Hodges and GBKStagg “System 250
- Fault-Tolerant Modular Processing Systems for Control Applications. In such systems, each process is restricted from accessing its own storage or peripheral areas, so any breach immediately suspends the process to prevent information from deteriorating in memory or peripherals.If an active process accidentally writes to a storage area holding another process's database or its parent instructions,
The environment for this suspended process is degraded. When restarted, incorrect data and code may be affected and in turn degrade other processes. Thus, if the original error goes undetected, it will propagate and cause widespread damage. The system described in said document also prevents a process from modifying its own instructions;
Reentrant shared procedures implying program failure, changing constant tables, executing data following instructions, and reading instructions following data.

To create a secure environment for each process, storage protection configurations are used and include so-called "capabilities." Each process is assigned a memory block that holds its instructions and data. Each block is defined in size and location by a "base" and "limit" address and an "access" code that constrains the type of access to each block. One process has the capability to have permissible access to each of these storage areas. The value currently in use is kept in a hardware capability register and each memory access is checked for violations. Capability handling operation received UK patent no.
No. 1329721 and No. 1410631.
Each process is provided with a pointer table that defines the storage blocks assigned to that process.

As mentioned above, each process within system 250 has an associated process dump stack protected by a capability mechanism. The functions of the dump stack are (i) to provide storage for the process state at a suspension point; (ii) Stacking (or nesting) information regarding the calling sequence (or subroutine) of the process.

The process dump stack is therefore basically a fixed part containing machine registers and indicators, and one entry (i.e. link) for each nested routine (i.e. process or subroutine).
It consists of a variable register that operates as a press stack with a . The information typically stored within each nested routine link includes (a) a relativized instruction address register for the return point to the nested routine, and (b) a caper for the nested routine's code block. integrity pointer,
(c) It has a capability pointer to a nested routine pointer table.

It is an object of the present invention to extend the functionality provided by the process dump stack, particularly with respect to pressed stack area links.

The present invention provides a multiprogramming data processing system in which each process has (a) a fixed portion that stores the contents of machine registers and indicators when the process is paused; A process dump stack is provided having a variable portion that stores links of subroutines, each link containing (a) an instruction address to which the process is returned when returning the nested routine, and (b) a variable portion that stores the links of the nested routine. (c) a link descriptor indicating the size and content of the remaining links.

Two additional classes of information can be stored on each link due to the inclusion of link descriptors: (i) data and capability registers that are saved during domain change procedures; and (ii) local storage segments. This is a descriptor for use. Descriptors for local storage segments include total check, base and limit information. Here the base and limit values are related to the base of the local storage stack and are referenced to the hidden capability register C(L) as well as the dump stack. The link descriptor is held within the most significant eight bits of the IAR word. If this is 0, the link is
It consists of only three items: (i), IAR, (ii), code block, and (iii), process pointer block. The most significant bits of the main descriptor indicate the presence of a stacked register, and the seven least significant bits indicate the generated local storage capability number.

A stacked register set is accompanied by a one-word descriptor indicating the registers that are stacked when the subroutine is nested.

The capabilities of the local storage segment are (i)
This is done by a hardware instruction that is a request local store instruction and (ii) a subset local store instruction.

When a local storage segment is allocated by a "request local storage" instruction, a three word entry is made in the process dump stack. This entry contains a level number indicating the current procedure nesting level and some basic access information.
The base and limit values are relative to the local storage stack and are related to its base address.
The pointer field of the capability pointer is offset with respect to the base of the dump stack. Similar mechanisms can be used to configure capabilities for subsets of local storage segments. This is done by the "subset local store" instruction, which for a given capability of a local storage segment creates a subset of that segment and returns the capabilities for it to a register. Dump stack entries are marked as subset blocks, and the associated level number is related to the current procedure nesting level.

Local storage is allocated by explicit hardware instructions, but is automatically deallocated upon return from the link procedure in which the entry was made. All capabilities of a particular level are paused when that procedural level is returned, including the register capabilities.

The primary function of the level number associated with each capability is to enforce non-discretionary propagation control mechanisms.
This control ensures that no capabilities are stored within capabilities of lower attachment levels.
This safety mechanism is important to prevent capabilities from citing missing information or bad superceded information.

A "stacked register" in a link descriptor has a one-word register descriptor attached to it, which is stacked when domain switching occurs (i.e., when routines are nested). Indicates a register. This register descriptor is set by a “guaranteed call” instruction and a “return”
and "protected return" commands to enable automatic selection definition of domain interfaces.

The data register (DO) is used as a register descriptor in the "protected call" instruction. Two features of the descriptor are: which data and capability registers are saved during the call;
It is to indicate which data and capability registers are cleared or protected from being read by a new domain. The registers to be saved are then loaded into the dump stack link and the DO register pattern is loaded into the register descriptor of that link.

In a "protected return" instruction, register descriptors are used to determine which registers are cleared upon return to the calling routine.

In FIG. 1, the modular data processing system includes (i) several processing units CPU1 and CPU2, and (ii)
Several memory moduli STA, STB and STC
and (iii) a group of peripheral devices collectively represented in the PE. Each storage module and each peripheral device is provided with access units SAUA, SAUB, SAUC and PAUN.

Each processing unit is provided with a separate communication path or bus (CB1 and CB2 are interfaces for processing units CPU1 and CPU2, respectively).
It is provided via BIF1 and BIF2. )
Each bus connects all access units (SAUA,
SAUB, SAUC and PAUN) terminate on individual ports. All access units are equipped to recognize coded address information applied on the bus terminating on the input port. The various segments used to handle the process are distributed throughout the storage module, and all addressing operations are based on a capability register protection system.

Next, in FIG. 2, each processing unit CPU includes an A data file ADF and a B data file BDF, each of which has A and B capability register files (ACA/L and ACB) and
Contains 32 positions along with BCF (BCA/L and BCB). The capability register is a British patent no.
No. 1,329,721. Data file ADF
and BDF provide overlapping register configurations, each containing eight general purpose registers.

Types of registers There are four types of registers: data registers,
Some of the first three types, capability pointer registers, capability registers, and indicator registers, are general-purpose and can be directly accessed by all programs. The rest are special purpose registers used for specific functions and are accessible only to programs that handle the appropriate capabilities. The complete register structure is shown in FIGS. 3 and 4.

General-purpose data registers (D(0) to D(7)) There are eight general-purpose data registers, D(0) to D(7), each 24 bits long, and perform all data operations. During the storage address formation period. These seven registers D(1) to D(7) can be used as address qualifiers.Register D(0) is a mask register and is used when transferring part of one word to the storage device. It can be used to specify the required bits.
Register D(0) is also used to pass parameters from one instruction to another. The latter use will be described later.

General Capability Registers (C(0) to C(7)) When loading a capability register (C(0) to C(7)), it contains the base address, limit address, and access rights to the memory block. I'm here.

The processing unit uses a capability register C(7) to hold capabilities for the current program block, and an instruction to load a new capability into C(7) transfers control to the block defined by the loaded capability. Transfer. that each time an instruction is read from a program block, the processing unit has C(7) set in its main access field;
and the address of the instruction is between the base and limit addresses of the capability. If a capability is loaded into C(7) that does not have EXECUTE DATA, a failure interruption will occur and it will be used next. A fault abort also occurs if the instruction address is outside the base and limit ranges. Capability register C(6) is commonly used to refer to the domain capability pointer block because it forms part of each link in the process dump stack and This is because the return command is overwritten.

special purpose data register The special purpose data registers are shown below.

(1) Instruction address register (IAR) This register is general-purpose capability register C(7)
The program block specified by contains the absolute address of the current instruction. It is changed by call, return, and load capability C(7) instructions, and by instructions that modify the process.

2 Watchdog Timer Register (WTR) This register is modified by instructions that modify the process; the old value is stored in the process dump stack of a suspended process, and the new value is loaded from the dump stack of an active process. It is decremented every 100μs. When 0 is reached, a fault interruption occurs. (See Section 4) It therefore measures the total time each process is active.

3 Interrupt Accept Register (IR) This register contains a single bit, bit 6,
Set when a program trap is accepted.
(See Section 4) 4 Process Dump Stack Press Register (DSPPR) This register contains an absolute address pointer that defines the current top of the process dump stack. (ie, points to the first word in the area available for dumping.) It is changed by return calls, request local store, and subset local store instructions, and it is changed by modify process instructions.

5 Fault Indicator Dump Register Following the first fault abort, this register contains the state of the fault indicator register.

6 Level Number (LNR) and Local Storage Stack Pointer Register (LSPR) This register is divided into two parts. The most significant eight bits contain the process' current link level number. It is changed by call and return instructions and modified by modify process instructions. The least significant 16 bits of the register contain a relative address pointer (relative to the base of C(L)) that defines the current top of the local storage stack.
(i.e. points to the first word in the area available for allocation) which is changed by the request local store, subset local store and return instructions and by the modify process command.

7 Local Capability Count (LCCR) and Local Storage Clear Count Register (LSCCR) This register is divided into two parts. The eight most significant bits contain a count of the local capability number generated at the current link level.
It is modified by request local store and subset local store instructions, and by call, return, and modify process instructions. The least significant 16 bits of the register contain the local memory clear count. It is changed by request local storage and changed by change process instructions.

8 Data Registers D(A) and D(B) These registers are not used by any processor function, but can be accessed by data instructions using "internal mode." Special purpose data registers, except the interrupt accept register, are 24 bits long. All of them can be accessed by data commands using "internal modes" as well as feature commands.

Special Purpose Capability Registers There are eight special purpose capability registers used by the processing unit to access control information. Since no special loading instructions are provided, they can be read and modified by programs with the ability to address "internal modes."

1 Capability Register C(D) This register contains the base/limit address and access code for the active process's processor dump stack. It is changed by modify process instructions and manipulated by call, return, request local store, and subset local store instructions.

2 Capability Register C(I) This register defines a storage block whose first word contains the interval timer value. It measures the absolute time elapsed and is decremented by the processing unit every 100 μs. When it reaches 0, a normal interrupt occurs.

3 Capability Register C (C1) This register defines the storage block containing the first part of the system capability table.

4 Capability Register C (C2) This register defines the storage block containing the second part of the system capabilities table.

5 Capability Register C(N) This register defines a storage block whose first word contains a capability pointer that provides entry into the normal interrupt process.

6 Capability Register C(S) This register defines a 4-word storage block used by the processor when handling fault interruptions. The 12 most significant bits of the base word are incremented during the failure sequence and the rest of the registers are preset by the processor following power-up.

7 Capability Register C(L) This register defines the storage block for the current process's local storage stack. It is changed by a change process instruction.

8 Capability Register C(P) This register is used by the programmer interface when accessing storage.

Indicator Registers There are four indicator registers: the main indicator (PIR in Figures 2 and 4), fault indicator FIR, test TR, and historical HR register. These indicate various conditions within the processing unit. These are only accessible in internal mode. The contents of the main indicator register are changed by a modify process instruction, the old value is stored in the process dump stack of the suspended process, and the new value is then loaded from the dump stack of the active process.

Main Indicator Register (PIR) The main indicator register is 8 bits long. 0-2
Bit equals 0. (0 bit), less than 0, (1 bit), overflow, (2 bits). These are set or cleared by the result of a majority command.

Bits 4 and 5 are control indicators.

1 Special mode (4 bits) remains set for only one instruction. If set, it causes load capability instructions to access special purpose capability registers instead of the corresponding general purpose capability registers.

2 Interface failure suppression (5 bits) remains set for only one instruction. When set, it suppresses failure aborts, which usually means that operands retrieved from storage are
Occurs when detecting a storage interface failure.

The 7th bit is the first trial indicator. It is set by a fault interruption and affects the processing device's response to subsequent faults.

8 bits are the inhibit interrupt indicator. It prevents timer interrupts from occurring when set.

Fault Indicator Register (FIR) The Fault Indicator Register is 24 bits long. Any bit can be set with internal mode access, and any bit can be cleared. A fault abort will occur if set by the following events, but a processor/storage interface fault will occur if interface fault inhibition is set in the main indicator register.

Bits 0, 5, 9-11, and 14 indicate a processing unit/storage unit failure.

Bus Corrupt (0 bit) is set if any input line from the parallel bus does not return to logic 0 within 400 μs after a memory access.

Slave timeout (5 bits) when a storage module reports that it cannot accept an address or data during a storage access.
is set.

A storage interface timeout (9 bits) is set if the storage module does not respond within 50 μs.

A parity comparison fault (10 bits) is set if the storage module generates a forward word (ie, ``address'' or ``address/data'') and the parity returned to the CPU is not equal to that generated by the processing unit.

“Data/address” read from storage device
A read data parity fault (11 bits) is set if the parity is not equal to what the processor generates on the address and data from the storage device.

The Illegal Control Code (14 bits) is set when the storage module reports that it has received an Illegal Control Code during a CPU/Storage transfer. 3 bits and an odd parity code are used.

Two bits are the interrupt time limit indicator. It is set if the interrupt accept register is not accessed for 300mS after the interval timer word is decremented to 0 (if no inhibit interrupts are set), or if this condition does not occur after 300mS of failure interruption. be done.

Bits 6-8 and 18 indicate a capability failure. A capability comparison fault (6 bits) is set when it is determined that the duplicate base address, limit address, or access code in the capability register used in the access attempt is not the same. A capability total check fault (7 bits) is set if the total check word rotated 9 bits to the left does not match the base and limit values when the capability register is loaded.

If it is found that there is an address outside the range specified by the base and limit address of the capability to be used, capability base/limit violation (8 bits) is set.

The access field violation (8 bits) is set when an unauthorized transfer is attempted.

12 bits are an illegal operation indicator. It is set in place where an illegal action is attempted.

The 13 bit is a power failure indicator. It is set when the power supply limit is exceeded.

The 15 bit is a trap fault indicator. It is set when a program trap occurs while inhibit interrupts are set.

16 bits and 19 bits indicate a hardware failure. If a certain internal hardware is checked for failure, hardware failure 1 and hardware failure 2 are set.

The 17 bit is the watchdog timer zero indicator. It means that the watchdog timer register is 0.
It will be set when .

Bits 20-23 are set to the octal address of the capability register used when a fault or trap occurs.

Bits 3 and 4 can only be set/reset by data commands using "internal mode".

Test Register (TR) This register contains test facilities for fault detection mechanisms.

Historical register (HR) One register in a group of 16 26-bit registers can be addressed at a time by a 4-bit address counter. These constitute a first in/first out circular queue for use in fault investigation routines.

Figure 2 shows how to use the registers: bit multiplexer BM, arithmetic unit ALU, instruction register IREG, data in register MDIN, memory address register MAR, data out register.
MDOR, A, B capability check comparator
In conjunction with ACC and BCC, the operation of the processing device when executing an instruction that processes information in the process dump stack will be described later.

Process Dump Stack Associated with each process is a process dump stack, which is a storage block defined by special purpose capability registers C(D) when the process is running. The process dump stack has three functions.

1. Save the process environment during suspension.

2. Stack subroutine environment values during calls to other subroutines.

3. Acts as a local capability table for local storage blocks allocated on the local storage stack.

The process dump stack is updated by calls, request local storage, subset local storage instructions, and modification processes. The change process instruction includes two such stacks. The contents of a typical current process dump stack are shown in FIG.

A process dump stack has a fixed size area and a stack area. The fixed area is used to dump the environment of a suspended process.
During the modification process microsequence, the capability pointers from capability pointer registers P(0)-P(5) are dumped to locations Pd(0)-Pd(5) and data registers D(0)-D The contents of (7) are dumped to locations Dd(0) to Dd(7). Additionally, some special process values are dumped into the fixed area. These are the press register, watchdog timer, main display register, level number (LN) and local storage stack pointer register (LSSP).
and the local storage clear count register (LSCC). The capability pointer from the capability pointer registers P(6), P(7) is dumped onto the stack along with the current (associated) instruction address register and local capability count register.

The press pointer register points to the last word (ie, instruction address) dumped to the press pointer location during the modification process and written to the dump stack. During execution of the process, this register points to the top of the stack (ie, the next available location on the stack). Data registers D(1) to D(6) during call
and capability pointer register P(0)
~P(5) can be saved by specifying the command,
In this case the descriptor value indicates which registers are stacked as follows.

18-23 bits P(0)-P(5) 12-17 bits D(1)-D(6) Setting a specific bit to 1 indicates that the registers are stacked. Capability pointer registers P(6), P(7) are always saved along with the instruction address register (relative) for the next instruction by a call. Setting the most significant bit in the IAR word to 1 indicates that the register is stacked.

A three-word entry is made on the process dump stack whenever local storage is allocated on the local storage stack by a request local storage instruction or a subblock is defined by a subset storage instruction. The three-word entry consists of a total check word, a base word, and a limit word. The least significant 16 bits of the base word contain the offset with respect to the base of the local storage stack capability register C(L) in the first location of the designated block. The 23 bits of the base word contain subcapability bits. The least significant 16 bits of the limit word contain the offset with respect to the base of the local storage stack capability register C(L) of the final location of the specified block. The least significant eight bits of the limit word contain the level number that generated the local capability table entry. The total check word includes a 24-bit check word formed by adding the least significant 16 bits of the base word to the least significant 16 bits of the limit word. The format of the local capability table entry is shown in FIG.

A request local store instruction generates a local capability table with a subcapability bit reset, and a subset local store instruction generates a local capability table entry with a subcapability bit set.

Next, consider the execution performance of various instructions by which the processing device of FIG. 2 processes information held in the process dump stack. Although the various operations executed by the processing device are controlled by a microprogram control device (not shown), those skilled in the art will be able to understand the desired operations defined by the flowcharts of FIGS. 7 to 10, for example. It will be appreciated that the flowchart steps can be illustrated using a program ROM to generate the desired control signals. Although various register-to-register transfers occur in the following description, shorthand notation including the = sign is used to simplify the description. This symbol shall define “to be”,
The ALU:=MDIN statement is interpreted as an arithmetic unit (ALU) receiving data held in register MDIN.

The first instruction to be considered is "request local storage" and the flow diagram for that instruction is shown in FIG.

Request local storage instruction The instruction word IW shown at the top of FIG. A request is made to allocate the A field of the size and instruction word indicated by the data, and the capability descriptor for that local storage block is loaded into the capability register C(N).
The M field defines one of the data registers used as an address qualifier, the C(X) field defines a general capability register holding a descriptor for the block in which the desired memory location is held, and The A value defines the offset from the base of the block for the desired location. During the previous instruction cycle, the instruction word IW is read from storage into the instruction buffer IB of FIG. 2, and the function code and register selection fields are added to the microprogram storage (not shown) to initiate this instruction operation. However, it is executed by a subsequent sequence of steps under microprogram control.

Step S1LSCC=0? In this step, the local storage clear count register LSCCR is selected by the microprogram unit in the A-file and provided to the arithmetic unit ALU so that the microprogram unit can test the arithmetic unit control signal AUCS for zero.
If it is 0, there is no space available in local storage.

Step S2 - Read Storage Address In this step, the storage address defined by the A value of the instruction word is read from the appropriate storage module to the data input register. The sequence of operations typically performed in this step is as follows.

ALUd:=C(X) Base ALUa:=IREG(A value) ALU Add MAR:=ALU Memory Read @MAR MDIN:=BIN Assume that no address modification is required (ie, M=0). The above operation extracts the local storage block size value LSSB which is read from the appropriate storage module to the data in register MDIN.

Step S3-LSSB=0? In this step, the data read in step S2 is passed to the ALU and zero-tested by the microprogram device using the ALUCS signal. If it is 0, a failure is displayed, and if it is not 0, step S4 is executed.

Step S4 - LSPR + LSSB - 1 In this step, the local storage stack pointer register (LSPR) is read to define the current top of the local storage stack (i.e., the first word in the area available for allocation) and to determine the final word for the block request. (i.e. limit) address is step S2
It is calculated by subtracting 1 from the LSSB value read in and adding it to the current LSPR address. Typically the sequence includes the following actions:

ALUa:=LSPR ALUb:=MDIN-1 SAVE ALU Step S5 in LSB Limit In this step, the result of the step S4 operation is tested to see if the requested block overruns the local storage area. This is accomplished by selecting the limit half of the local storage capability register C(L) and comparing it with the results from the ALU in capability comparators ACC and BCC. A failure occurs when a test fails.

Step 6 Write LSB Base to DS In this step, the dump stack push pointer register DSPPR, which currently points to the top of the dump stack, is used to define the address where the base address for the requested local storage block is written. The region LK (RS&LCC) in FIG. 5, which indicates "links with stacked registers and generated local capabilities", indicates local storage capability entries consisting of sum check, base, and limit.

The operations performed can typically take the following sequence.

ALU:=DSPPR ALU+1 MAR:=ALU DSPPR:=ALU ALU:=LSPR MDOR:=ALU Memory write @MAR Step S7 ~ Writing LSB limit to DS The limit value for the local memory block required in this step is as follows. is written to the local storage capability entry.

ALU:=DSPPR ALU+1 MAR:=ALU DSPPR:=ALU ALU:=LSS-1+LSP MDOR:=ALU Memory write @MAR Step 8 - Write LNR to DS In this step, level number register LNR
The content of is written to the most significant 8 bits of the limit word addressed in step S7 as follows.

ALU:=LNR MDOR:=ALY Memory write @MAR Step S9-Write summation check to DS In this step, summation check for the local storage capability entry is formed and written to the first word of the local storage capability entry. It will be done.

ALUa:=DSPPR ALUb:=LSS-1+LSP ALU addition BM right circulation ALU:=BM MDOR:=ALU ALU:=DSPPR ALU-2 MAR:=ALU Memory write @MAR Step S10 - Increment LCCR In this step, local capacitor The value in the integrity count register LCCR is incremented by one. Typically this is accomplished by circulating the contents of the LCCR register to the ALU, causing the ALU to perform a +1 operation.

Step S11 - Increment LSPR by LSS In this step, the local storage block size information read in step S2 is added to the current value of the local storage pointer register LSPR to set a new pointer to the next free area in the local storage. Form.

Step S12--C(N) Loads In this step, the local capability descriptor formed above is loaded into the capability register defined by the "D" field of the instruction word.
The operations typically performed include regular load capability register operations and are similar to those described in GB 1329721 given the design differences between the two CPUs.

Step S13 - Load LSS to LSCCR In this step, the local memory size value read in step S2 is supplied to the local memory clear count register, and then steps S14, S15, and S16 are repeatedly executed to load the requested local memory size value. Clears a location in a memory block. This is done by decrementing the local memory clear count register (step S15).
This is achieved by adding 0 to the base value and writing 0 to the storage location so defined (step S16) and testing the local storage clear count value to 0. (Step S14) If all local storage block locations are cleared, the LSCCR value is 0, and a command is issued in step S14.

Dump stack link LK in Figure 5 from above
It can be seen that the local storage block defined by the local capability entry in (RS&LCC) is available to the current routine and that the generation of the local storage block is stored in the local capability count register LCCR.

Next, we will consider the "Store Subset Local" instruction, and the flow diagram for that instruction is shown in FIG.

Subset local storage instruction In this instruction, the command word shown at the top of Fig. 8 is C.
(X) defines the capability pointer for the local storage capability descriptor by the A field and the capability register into which the local storage capability descriptor is loaded. The instruction also receives a data register D(0) which holds the offset in its most significant 12 bits and the subset word size value in its least significant 12 bits.

Step SS1-Load C(N) In this step, M, C, A
The local storage capability descriptor defined by the pointer specified by the field is loaded. The operations typically performed are described in British Patent No.
Although related to the actions performed in issue 1329721,
Of course, the design of the CPU is different from that of this patent.

Step SS2 - Read LSBO and Size This step uses the offset value and size to define the space required for the subset in local storage and to define the address that indicates the limits of the subset in the local storage block. These operations are typically accomplished by the following sequence.

ALUa0 to 11 bits:=D(0) 11 to 24 bits ALUb:=C(N) Base ALU addition MDOR:=ALU D(X) :=ALU ALUa:=D(X) ALUb:=D(0)0 ~11-bit ALU Addition Step SS3 - S-SS in Limits The limit address formed by the final ALU addition operation in this step is calculated using the capability code comparators ACC and BCC to determine the limit of the local storage capability descriptor. test. If the limit address is outside the size of the local storage block, a failure is displayed, and if it is within the size, step SS4 is executed.

Step SS4 - Write LS-S base to DS This step adds the offset and the capability specified by the instruction D field (i.e. C(N)) currently stored in the data out register during step SS2. The result on a relative basis from the register is dump stacked and set to indicate that it is a subset descriptor.
Forms the base word for local capability entries with bits. The following sequence is typically executed by a microprogram device.

ALUa:=DSPPR ALU+1 MAR:=DSPPR Memory write @MAR Step SS5 - Write LS-S limit to DS In this step, the limit value of the local capability descriptor of the subset is written to the dump stack at the next location.

Step SS6 - Write LNR to DS In this step, level number register LNR
The value in is written to the most significant 8 bits of the entry written in step SS5.

Step SS7 - Write summation check to DS In this step, the base address of the subset block is added to the limit address, the result is rotated by 9 bits, and then this word is written to the dump stack specified by the dump stack press pointer register DSPPR. address and form the total entry of the local capability descriptor.

Step SS8 - Form the LS-S pointer of C(N) In this step, the capability register specified by the C(N) field is accessed, the most significant 9 bits of the limit word are extracted, and the process dump stack is pressed. The least significant 15 bits of the relative value of the pointer register are used to form a pointer for C(N).

Step SS9 - Increment DSPPR; Increment LCCR In this step, the content of the wrestling dump stack press pointer register DSPPR is incremented to point to the dump stack position "below" the limit word of the finally formed capability descriptor. Finally, the local capability count register LCCR
The count is incremented by one to indicate the local capability descriptor number generated by the process.

From the above description of the "Request Local Store" and "Subset Local Store" instructions, it can be seen that nested entries in the dump stack are used to hold locally generated capability descriptors, and a local capability count register is generated during routine execution. It can be seen that it indicates the local capability number. For subset local store instructions, 23 bits of the base entry are marked as "1".

Nested areas of the process dump stack are used to provide local capability descriptor tables as well as storage for registers that are saved when domain switches (ie, calls to other subroutines) occur. The instructions included are (a)
(b) a “protected call” instruction and (b) a “protected return” instruction.

Protected Call Instruction FIG. 9 shows a flow diagram of the operations performed by executing this instruction. When this command is input, D(0)
carries the register descriptor, which is (a) the most significant 12
(b) Define registers to be stored in the dump stack in bits, and (b) define registers to be blanked in the least significant 12 bits. Typically, one 1 in any one of 12 to 17 bits is data register D(1)~
D(6) and pointers to capability registers C(0) to C(S) in which 18 to 23 bits are stored are defined. Similarly, any 1 from 0 to 5 bits
Data registers D(1) to D(6) where 1 is blank
Define a capability register in which bits 6 to 11 are blank.

Step SC1--Read D(0) In this step, the contents of register D(0) are read and passed to the microprogram using the arithmetic unit status signal ALUCS.

Step SC2 - Memory register; Blank register The register saved in this step is the 5th register.
As shown, the memory is passed through the ALU to the storage device on successive storage write operations at successive locations within the link portion of the dump stack. Addressing is under the control of the address formed using the dump stack push pointer in register DSPPR. When the register storage is completed, the blank register is circulated through the ALU and the ALU output is set to 0.

Write D(0) to step CS3DS. When step CS3 is completed, the dump stack press pointer points to the lower entry of the last stacked register. FIG. 5 shows that this location is used to hold register descriptor entries. The DSPPR register is used to define the dump stack address where the contents of D(0) will be written.

ALU:=DSPPR MAR:=ALU ALU:=D(0) MDOR:=ALU Memory write @MAR ALU:=DSPPR ALU+1 DSPPR:=ALU When the memory write operation is performed in step CS3, the dump stack press pointer is incremented by 1. At steps CS4 and CS5, the preparation for storing the pointers C(6) and C(7) is completed, and the pressed pointer is subsequently incremented.

Step Write IAR to CS6DS In this step, the final entry of the nested routine is prepared, which has the IAR value relativized from 0 to 15 bits and the value of the local capability count register from 16 to 22 bits. , which has been incremented in the implementation of the "request local store" instruction of step S10 and the "subset local store" instruction of step SS9. The operations performed are typically the following.

ALUa:=IAR ALUb:=C(7)Base ALU±1 MDOR0~15 bits:=ALU0~15 bits ALU:=LCCR MDOR16~22 bits:=ALU16~22 bits ALU set 23~1 bits MDOR25 bits:=ALU23 Bit memory write @MAR ALU:=DSPPR ALU+1 DSPPR:=ALU Load step CS7C(6) Load the capability descriptor for the capability pointer table of the called process into the capability register C(6) in this step be done.

Step CS8C (6) Access OK? In this step, the microprogram device checks the access code loaded in step CS7.

Increment step CS9LCR; reset LCCR In this step, level number register LNR
The value of is incremented by 1 by passing it through the ALU,
The local capability count value in register LCCR is reset to zero.

Load step CS10C(7) In this step, program block capability register C( 7) is loaded.

This operation completes the function for the protected call and the nested link saves the local capability descriptor generated during the nested routine along with the saved registers and descriptors for the local capability descriptor and saved registers. Contains.

Consider the implementation of a "protected return" instruction that is executed at the end of the last called routine and returns control to a previously nested routine. 1st
Figure 0 shows the operations performed on protected instructions.

Protected Return Instruction The instruction word RLW shown at the top of FIG. D(0) having one pattern of 1 indicating the tie registers C(0) to C(5) is input.

Step RS1 - Make a register blank In this step, register D (0) is read and used to adjust the ALUCS signal, and the microprogram control sequentially selects registers to be blanked by circulating its contents to the ALU. can do.

Step RS2 - Read DS In this step the dump stack is addressed with the dump stack press pointer decremented by 1 to address the descriptor/IAR link entry and the information read goes to one of the internal data registers, e.g. D(1). Supplied, steps 23 bits
Test with RS5 to find out if any registers need to be unloaded from the link.

ALU :=DSPPR ALU−1 MAR :=ALU DSPPR:=ALU Memory read @MAR MDIN :=BII ALU :=MDIN D(1) :=ALU ALU :=DSPPR ALU−1 MAR :=ALU DSPPR:=ALU Step Load RS3C(7); Decrement DSPPR In this step, the pointer of C(7) is read from the dump stack, the capability register C(7) is loaded, and the dump stack press pointer is decremented.

Step Load RS3C(6) In this step, the pointer of C(6) is read from the dump stack and the capability register C(6) is loaded.

Is step RS5 register descriptor 23 bits 1? In this step, 23 bits of register D(1) loaded in step RS2 are tested.
If it is 0, there are no registers to be unloaded from the dump stack link shown as link LK(0) in FIG. 5, and steps RS6, RS7, and RS8 are ignored. If the bit tested is 1, these steps are performed to unload the stacked register from the link.

Decrement step RS6DSPPR; read REG descriptor In this step, the next entry in the link is read, which is the register descriptor as shown in Figure 5, and this descriptor contains the data stacked in step RS7. and capability register unloading control.

Step RS7DSPPR is decremented by (LCC x 3). This step adjusts the dump stack press pointer and completes the preparation for unloading the local capability descriptor if it exists.

Step RS9LCC×3=0? If it is 0, there is no local capability descriptor in the link as shown by LK(RS) in FIG. Step if tested value is 0
RS10, etc. is executed to set a local storage pointer to the base address of the first subset of capability descriptors generated by the "non-nested" routine.

Step RS10 - Save DSPPR; Increment DSPPR; Load LCC x 3 to LSCCR In this step, the dump stack press pointer in register DSPPR is saved for later use.
Typically it is held in one of the data registers that is not loaded during steps RS6, RS7, RS8. In addition, the local storage capability count register LCCR is loaded with a local capability count that defines the local capability number generated in this process.

Step RS11-ISLSCCR=0? This step tests the local capability count to see if it is zero. Obviously, the local capability count is not zero at this point.

Read step RS12 base entry This step reads the dump stack link entry at the location defined in step RS10 and tests the most significant bit of this word to see if it is a subset local capability base entry. be able to.

Step RS13 - Is the 23 bit = 0? In this step, test the dump stack entry read in the final step to see if it is the local capability descriptor base entry indicated by the 23 bit being "1". . If 23 bits are “1”, step
RS14 will be implemented.

Step RS14 - Decrement LCCR; DSPPR by 3
In this step, the local capability count in register LCCR is decremented by 1, and the dump stack pointer register is adjusted by 3 and if it is 1, then the base entry for the next local subset capability pointer is incremented by 1. Instruct. Steps RS11, RS12, and RS13 are then executed to check whether there is another local capability descriptor (step RS11) and whether it was generated by the execution of the returned process.
(Steps RS12, RS11) If no local subset capability descriptor is generated, step RS16 is executed to set the dump stack press pointer value to the start point of the dump stack link being unloaded and to set this area to the starting point of the dump stack link being unloaded. It can be reused in the next "call" instruction. Return to routine parameters If a local subset capability descriptor is found during unstacking, step RS15 is executed;
Before executing step RS16, the local storage pointer register LSPR is set to the base value of the entry.

Step RS14 - Decrement LNR; Set LCCR to 0. In this step, the return instruction returns control to the high-level subroutine, and steps RS11,
The local capability count register LCCR used in the loop including RS12, RS13, and RS14 is 0.
When the level is restored, the level number register LNR is decremented by 1.

Step RS18 - Check LDS In this step, capability register C
The local storage capability access codes of eight general purpose capability pointers (0) to C(5) are checked. If a relative process dump stack with an offset value equal to or greater than the push pointer value is found,
The corresponding capability register is left blank.

Step RS19 - Load IAR This step uses the relativized IAR value stored in step RS2 to form the actual IAR value of the returned routine.

The return instruction protected from above removes all stacked registers except when a call to a lower subroutine is made from the dump stack link, sets the level number register LNR to the next high level, and returns the dump stack and local Adjust the storage pointer register before returning to the next higher level subroutine.

Conclusion From the above explanation, we can use the dump stack to nest subroutines, and each link holds a pointer to the capability registers C(6) and C(7) (i.e., the process capability table and the process program code block). ), the relativized address values from nested routines are nested with the local storage capability descriptors of local storage blocks generated during the routine, along with the selection of general purpose registers and general capability register pointers. I understand. The information held on each link is qualified by a generated local capability descriptor number and a descriptor indicating the stacked registers. The instructions that handle the enhanced dump stack mechanism built into the CPU are
(i) request local storage and subset local storage instructions that partition local storage blocks and assign capability descriptors to them and store the descriptors in the link area of the dump stack for the subroutine requesting the local storage blocks; and (ii) , protected call and return instructions that nest and unstack the stacking and unstacking of selected register contents in links nested in subroutines, respectively. Also, although local storage is assigned a definite instruction, it is automatically deallocated upon a return from the subroutine whose link the local storage capability descriptor entry is made. When a procedural level is returned in this way, all capabilities of the particular level are suspended, including the register capabilities. The level number that accompanies each local storage capability entry enhances the non-discretionary propagation control mechanism. This facility ensures that capability descriptors cannot be stored and used in low-level subroutines. This safety mechanism is important to prevent missing references to capability descriptors and to prevent degraded information after returning to a higher level subroutine.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a typical multiprocessor system for use in an embodiment of the invention; FIG. 2 is a block diagram of a typical processor unit suitable for use in an embodiment of the invention; Figure 3 shows the general purpose registers held in the register file within the processor unit, Figure 4 shows the special purpose registers and indicator registers within the processor unit, Figure 5 shows a typical dump stack, and Figure 6 shows the local caper. Figure 7 is a flow diagram of a request local storage instruction, Figure 8 is a flow diagram of a subset local storage instruction, Figure 9 is a flow diagram of a protected call instruction, and Figure 10 is a flow diagram of a protected return. FIG. 3 is a flow diagram of instructions. Explanation of reference symbols, CPU1, CPU2...processing units,
STA, STB, STC...Storage module, PE...Peripheral device, SAUA, SAUB, SAUC, PAUN...Access unit, BIF1, BIF2...Interface, ADF, BDF...Data file, ACF, BCF
...Capability register file.

Claims (1)

[Scope of Claims] 1. A multi-user data processing device, comprising a processor module that executes a plurality of processes that execute nested subroutines, each of the plurality of processes having a A separate process dump stack is provided having a fixed area storage element for storing the contents of machine registers and indicators and a variable area storage element for storing the links of each nested subroutine executed by the process. and each link is
(i) the instruction address to which the process should return when the nested subroutine is resumed; and (ii) a pointer to the nested subroutine's code block, which code block carries the instructions of the nested subroutine. defining the pointer, the process executes the local storage request instruction in a link of a storage element of the variable area of a process dump stack in the multi-user data processing device capable of generating a local storage request instruction; Apparatus is provided in said processor module to define a link and an indicator for defining the remaining size and content of a block of local storage that is divided into a plurality of local storage segments, said local storage segment being The processor module is used for local storage of information related to the nested subroutine in the event of abort during execution of the local storage request instruction, and the processor module includes a local storage stack pointer register and a local storage clear count register. and wherein the local storage stack pointer register contains the starting address of free space within the local segment, and the local storage clear count register contains the available size of the free space of the local storage block for storage; The contents of the local storage stack pointer register and the local storage clear count register are changed by the processor module, and the local storage stack pointer register and the local storage clear count register are changed by the execution of the local storage request instruction. the processor module further includes means for accessing the local storage stack pointer register and the local storage clear count register and during execution of the local storage request instruction. 1. A multi-user processing device comprising: apparatus for generating local capability descriptor information for storage in a variable portion of a process dump stack. 2. In the multi-user processing device according to claim 1, the local storage request instruction is used to request storage of the data processing device that is occupied by a block of local storage allocated to the process being executed by the processor module. A multi-user processing device that uses a processor module's local storage capability registers that contain information indicative of regions. 3. A multi-user processing device according to claim 2, wherein the link descriptor includes information indicating the number of local storage segments generated during execution of the subroutine. 4. A multi-user processing device according to claim 2, in which the descriptor of the link, when marked, stores the contents of at least one general purpose data and capability register of the processor module. A multi-user processing device including an indicator indicating that it contains a storage location. 5. A multi-user processing device according to claim 4, wherein the link includes a register-stacked descriptor indicating a match between general purpose data and the contents of a capability register stored in the link. . 6. The multi-user processing device of claim 2, wherein the processor module includes subset local storage instructions for controlling separation of local storage segments into smaller subsets;
The operation of the subset local storage instruction is at least one
A multi-user processing device comprising: marking a portion of an entry within a link with a flag bit to indicate that the entry relates to a subset of a local storage segment. 7. A multi-user processing device according to claim 6, wherein each entry generated by a local storage request instruction or a subset local storage instruction is performed when the local storage segment or subset is generated. A multi-user data processing device that stores the number of levels assigned to subroutines.