JP2901781B2 - Inspection method for semiconductor device - Google Patents

Inspection method for semiconductor device

Info

Publication number
JP2901781B2
JP2901781B2 JP11441591A JP11441591A JP2901781B2 JP 2901781 B2 JP2901781 B2 JP 2901781B2 JP 11441591 A JP11441591 A JP 11441591A JP 11441591 A JP11441591 A JP 11441591A JP 2901781 B2 JP2901781 B2 JP 2901781B2
Authority
JP
Japan
Prior art keywords
probe
electrode
electrodes
short
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11441591A
Other languages
Japanese (ja)
Other versions
JPH04342150A (en
Inventor
勲 衣目川
正 高垣
広宣 豊島
清 沼田
常洋 岡元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Plant Technologies Ltd
Original Assignee
Hitachi Techno Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Techno Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Techno Engineering Co Ltd
Priority to JP11441591A priority Critical patent/JP2901781B2/en
Publication of JPH04342150A publication Critical patent/JPH04342150A/en
Application granted granted Critical
Publication of JP2901781B2 publication Critical patent/JP2901781B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の検査方法に
係り、特に、半導体素子を実装する支持基板の両主面に
電気的に接続して設けられる複数の対応した電極にプロ
ーブを当接して電気的特性を測定する検査方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of inspecting a semiconductor device, and more particularly, to a method of contacting a probe with a plurality of corresponding electrodes provided to be electrically connected to both main surfaces of a support substrate on which a semiconductor element is mounted. And an inspection method for measuring electrical characteristics.

【0002】[0002]

【従来の技術】半導体装置の製造工程中に、半導体素子
あるいは半導体素子を実装する支持基板上の複数の電極
にプローブを当接し、導通状態や抵抗測定等の検査が行
われている。
2. Description of the Related Art During a manufacturing process of a semiconductor device, a probe is brought into contact with a plurality of electrodes on a semiconductor element or a supporting substrate on which the semiconductor element is mounted, and inspections such as a conduction state and a resistance measurement are performed.

【0003】この検査方法を紹介するものとして、特開
昭64−50434 号公報がある。
[0003] Japanese Patent Application Laid-Open No. Sho 50-50434 discloses this inspection method.

【0004】[0004]

【発明が解決しようとする課題】半導体素子の高集積化
に伴い、半導体素子を実装する支持基板上の複数の電極
は微小化する傾向にある。一例として直径約0.25mm
の電極を設けたものがある。この様に微小なものにプロ
ーブを当接させることは困難が伴う。また、電極材とし
て用いられるものには軟かいものもあり、微小で軟かい
金属にプローブを押し当てると電極が容易に変形してし
まい、測定は行えても、その後、支持基板は使用不能に
なるものがある。そこで、プローブ当接に手加減を加え
ると、充分な接触圧力の確保ができず、高い測定精度が
得られなくなる。
With the increase in the degree of integration of a semiconductor device, a plurality of electrodes on a support substrate on which the semiconductor device is mounted tend to be miniaturized. As an example, about 0.25mm in diameter
Are provided. It is difficult to bring the probe into contact with such a minute object. In addition, some of the materials used as electrode materials are soft.When a probe is pressed against a small and soft metal, the electrodes are easily deformed, and even if measurement can be performed, the support substrate becomes unusable after that. There is something. Therefore, if manual adjustment is applied to the probe contact, sufficient contact pressure cannot be ensured, and high measurement accuracy cannot be obtained.

【0005】それゆえ、本発明の目的は、支持基板上の
電極を破損することなく特性測定を高精度に行うことが
できる検査方法を提供することにある。
Therefore, an object of the present invention is to provide an inspection method capable of measuring characteristics with high accuracy without damaging an electrode on a supporting substrate.

【0006】[0006]

【課題を解決するための手段】上記目的を達成する本発
明検査方法の特徴とするところは、軟かい電極が設けら
れる支持基板の一主面に複数の電極を短絡する膜を設
け、この短絡膜と他方の主面の各電極にプローブを当接
して特性測定を行うことにある。
A feature of the inspection method of the present invention that achieves the above object is that a film for short-circuiting a plurality of electrodes is provided on one main surface of a support substrate on which a soft electrode is provided, and the short-circuit is provided. It is to measure characteristics by bringing a probe into contact with the film and each electrode on the other main surface.

【0007】[0007]

【作用】一主面上の短絡膜にプローブを当接することに
より、軟かい材質の電極にプローブを当接する必要がな
くなり、それにより、その電極が破損されることはなく
なる。また、短絡膜にプローブを強く当接し、短絡膜に
プローブで傷を付けることがあっても、その短絡膜は除
去されるので、支障はなく、また、強く当接することに
より、必要な接触圧力は確保でき、高い測定精度が得ら
れる。
By contacting the probe with the short-circuit film on one principal surface, it is not necessary to contact the probe with an electrode made of a soft material, so that the electrode is not damaged. Further, even if the probe is strongly contacted with the short-circuit film and the short-circuit film is scratched by the probe, the short-circuit film is removed, so that there is no problem. Can be secured and high measurement accuracy can be obtained.

【0008】[0008]

【実施例】以下、本発明検査方法を図面に示す一実施例
に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The inspection method of the present invention will be described below with reference to an embodiment shown in the drawings.

【0009】図1は、本発明検査方法を実施する検査装
置の要部分解斜視図である。
FIG. 1 is an exploded perspective view of a main part of an inspection apparatus for performing the inspection method of the present invention.

【0010】図1において、1は、上プローブブロック
であり、このプローブブロック1は図示していない上固
定板に支持固定されている。また、プローブブロック1
は複数のプローブ2が下面に垂設されている。各プロー
ブ2には個々にリード線20が接続されている。
In FIG. 1, reference numeral 1 denotes an upper probe block, and the probe block 1 is supported and fixed to an upper fixing plate (not shown). Probe block 1
Has a plurality of probes 2 suspended from the lower surface. Each probe 2 is individually connected to a lead wire 20.

【0011】3は、図示していない半導体素子を面実装
する支持基板である。図1の点線で示した区分け内に1
個ずつ半導体素子が固着される。その固着は上面に設け
た電極4を介して行う。電極4の材質の一例はタングス
テンである。
Reference numeral 3 denotes a support substrate on which a semiconductor element (not shown) is surface-mounted. 1 is included in the division indicated by the dotted line in FIG.
The semiconductor elements are fixed individually. The fixing is performed via an electrode 4 provided on the upper surface. An example of the material of the electrode 4 is tungsten.

【0012】支持基板は図2に示す様に、下面には上面
の各電極4に対応して設けられる複数の軟質の電極16
がある。また、電極16は、半田バンプ用のBLMであ
り、一例として金が外用される。両電極4,16間は支
持基板3中に埋設した配線膜30により接続されてい
る。尚、配線膜30中の抵抗Rは薄膜技術を応用して設
けた終端抵抗である。
As shown in FIG. 2, the support substrate has a plurality of soft electrodes 16 provided on the lower surface corresponding to the respective electrodes 4 on the upper surface.
There is. The electrode 16 is a BLM for a solder bump, and gold is used externally as an example. The two electrodes 4 and 16 are connected by a wiring film 30 buried in the support substrate 3. The resistance R in the wiring film 30 is a terminating resistance provided by applying the thin film technology.

【0013】支持基板3の下面には短絡膜5を設けてい
る。これは、電極16全てを短絡している。短絡膜5の
形成は、蒸着やメッキで設けても良いが、金や銀,銅の
箔を接触させるものであっても良い。
A short-circuit film 5 is provided on the lower surface of the support substrate 3. This shorts all of the electrodes 16. The short-circuit film 5 may be formed by vapor deposition or plating, but may be formed by contacting gold, silver, or copper foil.

【0014】図1における6は、支持基板3の固定治具
である。治具6の中央に支持基板3を収納する略方形の
保持堤7が設けられている。保持堤7の一角にネジ8と
押圧部材9が設けられており、ネジ8を回転させて、保
持堤7に支持基板3を押圧固定する。
Reference numeral 6 in FIG. 1 denotes a jig for fixing the support substrate 3. At the center of the jig 6, a substantially rectangular holding bank 7 for storing the support substrate 3 is provided. A screw 8 and a pressing member 9 are provided at one corner of the holding bank 7, and the screw 8 is rotated to press and fix the support substrate 3 to the holding bank 7.

【0015】保持堤内側の床面10には複数のプローブ
通過孔10aが設けられている。固定治具6は図示して
いないが、下プローブブロック11に取外可能に固定さ
れる。下プローブブロック11には固定治具6のプロー
ブ通過孔10aに対応する位置に下プローブ12が直立
されている。下プローブブロック11はX,Y,θ,Z
方向に移動可能なテーブル群13上に固定されている。
A plurality of probe passage holes 10a are provided in the floor 10 inside the retaining bank. Although not shown, the fixing jig 6 is detachably fixed to the lower probe block 11. In the lower probe block 11, a lower probe 12 is erected at a position corresponding to the probe passage hole 10a of the fixing jig 6. Lower probe block 11 is X, Y, θ, Z
It is fixed on a table group 13 that can move in the direction.

【0016】固定治具6に支持基板3を固定して短絡膜
5と下プローブ12を当接させてから、テーブル群13
を図示していないコントローラで移動させ、支持基板3
上の電極4を上プローブ2に当接させる。図2では、上
電極4,短絡膜5に上下両プローブ2,12を当接さ
せ、特性測定を行なう状況を示している。
After fixing the support substrate 3 to the fixing jig 6 and bringing the short-circuit film 5 and the lower probe 12 into contact with each other, the table group 13
Is moved by a controller (not shown), and the supporting substrate 3 is moved.
The upper electrode 4 is brought into contact with the upper probe 2. FIG. 2 shows a situation in which the upper and lower probes 2 and 12 are brought into contact with the upper electrode 4 and the short-circuit film 5 to measure the characteristics.

【0017】図2に示す14は、上下両プローブ2,1
2とリード線20,21と接続されたスキャナで、上電
極4と短絡膜5の最短距離に位置する上下両プローブ
2,12を選択し、通電して特性測定部15で導通試験
や抵抗,インピーダンス,絶縁抵抗等の測定を行なう。
In FIG. 2, reference numeral 14 denotes upper and lower probes 2, 1
The upper and lower probes 2 and 12 located at the shortest distance between the upper electrode 4 and the short-circuit film 5 are selected by a scanner connected to the lead wires 20 and 21 and energized. Measure impedance, insulation resistance, etc.

【0018】下プローブ12は支持基板3の短絡膜5に
当接され、電極16に直接触れることはない。そのた
め、強く下プローブ12を短絡膜5に接触させることが
できる。上電極4は硬い材質のものであり、上プローブ
2を電極4に強固に圧接できる。
The lower probe 12 is in contact with the short-circuit film 5 of the support substrate 3 and does not directly touch the electrode 16. Therefore, the lower probe 12 can be strongly contacted with the short-circuit film 5. The upper electrode 4 is made of a hard material so that the upper probe 2 can be firmly pressed against the electrode 4.

【0019】上プローブ2は上電極4の個々と接触する
ので、下プローブ12が短絡膜5により短絡されていて
も、対応関係にある上下両電極4,16間で混触を生ず
ることはない。従って、上下プローブ2,12の接触圧
力は充電確保でき、電極16を破損することなく、高精
度に検査を遂行できる。
Since the upper probe 2 is in contact with each of the upper electrodes 4, even if the lower probe 12 is short-circuited by the short-circuit film 5, no contact occurs between the upper and lower electrodes 4, 16 in a corresponding relationship. Therefore, the contact pressure of the upper and lower probes 2 and 12 can be ensured to be charged, and the inspection can be performed with high accuracy without damaging the electrode 16.

【0020】尚、短絡膜5の特性を前もって測定してお
くことにより、その内部抵抗は補正により除去できる。
By measuring the characteristics of the short-circuit film 5 in advance, its internal resistance can be removed by correction.

【0021】上記実施例では、上下プローブブロック
1,11に複数のプローブ2,12を設けているが、各
々単数のプローブを有したものでも支障ない。
In the above embodiment, a plurality of probes 2 and 12 are provided in the upper and lower probe blocks 1 and 11, however, a single probe may be used.

【0022】BLMとして用いる材料を短絡膜5として
蒸着により設けておいて、プローブ12はBLMとなる
部分以外に当接させ、検査後に電極16が形成される様
にエッチング加工を行えば、支持基板3の加工工程と特
性測定工程の一部を重ねることができる。
If the material to be used for the BLM is provided as a short-circuit film 5 by vapor deposition, the probe 12 is brought into contact with a portion other than the portion to be the BLM, and etching is performed so that the electrode 16 is formed after the inspection. Part 3 of the processing step and the characteristic measurement step can be overlapped.

【0023】[0023]

【発明の効果】以上説明したように、本発明によれば、
支持基板上の電極を破損することなく、特性測定を高精
度に行うことができる。
As described above, according to the present invention,
The characteristics can be measured with high accuracy without damaging the electrodes on the support substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明検査方法の一実施例に用いられる検査装
置の要部分解斜視図。
FIG. 1 is an exploded perspective view of a main part of an inspection apparatus used in an embodiment of the inspection method of the present invention.

【図2】図1に示す検査装置により測定を行う状況を示
す図。
FIG. 2 is a diagram showing a situation where measurement is performed by the inspection device shown in FIG. 1;

【符号の説明】[Explanation of symbols]

2…上プローブ、3…支持基板、4…上電極、5…短絡
膜、12…下プローブ、15…特性測定部、16…下電
極。
2 upper probe, 3 support substrate, 4 upper electrode, 5 short circuit film, 12 lower probe, 15 characteristic measuring section, 16 lower electrode.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 豊島 広宣 茨城県竜ケ崎市向陽台五丁目2番地 日 立テクノエンジニアリング株式会社開発 研究所内 (72)発明者 沼田 清 神奈川県秦野市堀山下1番地 株式会社 日立製作所 神奈川工場内 (72)発明者 岡元 常洋 神奈川県秦野市堀山下1番地 株式会社 日立製作所 神奈川工場内 (56)参考文献 特開 昭60−27139(JP,A) 特開 平2−6764(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/66 G01R 31/26 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hironobu Toshima 5-2-2 Koyodai, Ryugasaki-shi, Ibaraki Pref. Inside the R & D Laboratory (72) Inventor Kiyoshi Numata 1- 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. In the factory Kanagawa factory (72) Inventor Tsuneo Okamoto 1 Horiyamashita, Hadano-shi, Kanagawa In the Hitachi factory Kanagawa factory (56) References JP-A-60-27139 (JP, A) JP-A-2-6764 ( JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/66 G01R 31/26

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】一主面に複数の電極を備え、他の主面に上
記各電極に対応した電極が設けられ、両主面の各対応し
た電極が電気的に接続されていて上記一主面上にその各
電極に接続される様に半導体素子が実装される支持基板
の上記両主面の各対応した電極にプローブを当接して各
対応した電極間の特性を測定する半導体装置の検査方法
において、上記一主面にその複数の電極を短絡する膜を
設け、該短絡膜と上記他の主面の各電極にプローブを当
接して各対応した電極間の特性を測定することを特徴と
する半導体装置の検査方法。
A first surface provided with a plurality of electrodes; another main surface provided with electrodes corresponding to the respective electrodes, and corresponding electrodes on both main surfaces being electrically connected to each other; Inspection of a semiconductor device in which a probe is brought into contact with each corresponding electrode on both main surfaces of a support substrate on which a semiconductor element is mounted so as to be connected to each electrode on the surface, and a characteristic between each corresponding electrode is measured. In the method, a film for short-circuiting the plurality of electrodes is provided on the one main surface, and a probe is brought into contact with the short-circuit film and each electrode on the other main surface to measure characteristics between the corresponding electrodes. Inspection method for a semiconductor device.
【請求項2】上記請求項1の検査方法において、一主面
の電極は軟かい材質よりなるものであり、他の主面の電
極は硬い材質のものであることを特徴とする半導体装置
の検査方法。
2. The inspection method according to claim 1, wherein the electrode on one main surface is made of a soft material, and the electrode on the other main surface is made of a hard material. Inspection methods.
JP11441591A 1991-05-20 1991-05-20 Inspection method for semiconductor device Expired - Fee Related JP2901781B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11441591A JP2901781B2 (en) 1991-05-20 1991-05-20 Inspection method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11441591A JP2901781B2 (en) 1991-05-20 1991-05-20 Inspection method for semiconductor device

Publications (2)

Publication Number Publication Date
JPH04342150A JPH04342150A (en) 1992-11-27
JP2901781B2 true JP2901781B2 (en) 1999-06-07

Family

ID=14637124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11441591A Expired - Fee Related JP2901781B2 (en) 1991-05-20 1991-05-20 Inspection method for semiconductor device

Country Status (1)

Country Link
JP (1) JP2901781B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10253688A (en) * 1997-03-10 1998-09-25 Sony Corp Apparatus and method for continuity inspection of flexible circuit board
JP3327534B2 (en) * 1999-11-24 2002-09-24 日本特殊陶業株式会社 Substrate inspection device, substrate manufacturing method, and substrate with bump
JP4588941B2 (en) * 2001-08-10 2010-12-01 日置電機株式会社 Resistance measuring device and circuit board inspection device

Also Published As

Publication number Publication date
JPH04342150A (en) 1992-11-27

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