JP2897828B2 - Thin film transistor array substrate and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix liquid crystal panel, and more particularly to a thin film transistor array substrate used for the liquid crystal panel.

[0002]

2. Description of the Related Art An active matrix liquid crystal panel is obtained by forming a thin film transistor (hereinafter, referred to as a TFT), each electrode line, a storage capacitor and the like on a glass substrate.
After forming an alignment film on each of the FT array substrate and a counter electrode substrate obtained by forming a black matrix, a color filter and a common electrode on another glass substrate,
The structure is such that the substrates are bonded using a sealant, liquid crystal is injected into the gap between the substrates, and the injection port is sealed with a sealant. Also, an active matrix type liquid crystal display device
It is configured by arranging peripheral members such as a driving LSI (or driving IC or driver) and a backlight on the above-described active matrix liquid crystal panel.

In the liquid crystal panel constituting the above-described liquid crystal display device, the TFT array substrate is provided with a TFT as a switching element and a storage capacitor for reducing display unevenness. Among the elements, various ingenuity are devised depending on the purpose. In particular, in a liquid crystal display device using such a TFT array substrate, in order to perform a display of good quality, it is necessary to sufficiently maintain the signal voltage charged in the pixel electrode until the next rewriting. There is. This is because when the held signal voltage decreases, display unevenness occurs and the screen becomes unsightly. Therefore, since it is important to increase the storage capacitance for holding the signal voltage in the pixel electrode to a certain extent or more, the storage capacitance electrode is indispensable as a component thereof.

A TFT array substrate of this type, which is constructed for a specific purpose, is disclosed in Japanese Patent Application Laid-Open No. Hei 5-100249 (hereinafter referred to as Reference 1). Japanese Unexamined Patent Publication No. Hei 7-181514 (hereinafter referred to as Reference 2). In each of the cited examples, examples of a plurality of TFT array substrates are disclosed, and in the following, characteristic features will be briefly described as conventional examples.

[0005] The TFT array substrate of Example 1 (hereinafter referred to as Conventional Example 1) in Reference 1 is an inverted staggered TF.
T, a pixel electrode, and a storage capacitor electrode provided with the pixel electrode and the gate insulating film interposed therebetween. In particular, the gate electrode and the storage capacitor electrode of the TFT are formed of a transparent conductive film. Is what it is. The channel portion of the TFT is formed of polysilicon (hereinafter, referred to as p-Si) obtained by crystallizing amorphous silicon (hereinafter, referred to as a-Si) by laser annealing or the like. This is because, as can be understood from the fact that a-Si is used in a solar cell, when it receives light, it generates a photocurrent by a photoelectric conversion function due to its characteristics. This is because a-Si cannot be applied to a channel portion when a transmission type having a backlight is assumed because the gate electrode is transparent.

In the TFT array substrate of Example 2 (hereinafter referred to as Conventional Example 2) in Reference Example 1, the gate electrode and the storage capacitor electrode are formed of a transparent conductive film as in Conventional Example 1, and the channel portion is formed. It is formed by a-Si. Accordingly, the liquid crystal panel has a configuration in which a black matrix is arranged on the TFT on the counter electrode substrate side.
The light is transmitted through the array substrate.

In each of the TFT array substrates of Conventional Example 1 and Conventional Example 2, an interlayer insulating film is provided on the pixel electrode and the TFT, and a passivation film is provided so as to cover the whole. Is provided.

[0008] On the other hand, one embodiment of the cited reference 2 (hereinafter referred to as "example")
This is referred to as Conventional Example 3. The TFT array substrate includes an inverted staggered TFT, a pixel electrode, and a storage capacitor electrode provided so as to interpose the pixel electrode and an insulating film. Is formed of a metal anodic oxide film. In addition, the gate insulating film is formed by CVD (chemical vapor deposition) generally used as the gate insulating film.
And the like, and a two-layer structure of a metal anodic oxide film.

Incidentally, the two examples shown as the prior art in the cited reference 1 are provided with a dual-gate positive staggered TFT as the TFT, and are not directly related to the present invention described later. Description is omitted. Further, with respect to another embodiment in the cited example 2,
Since the yield is expected to decrease and the cost to increase because the process is too complicated, it is not feasible, and therefore, the description is omitted.

Here, Conventional Examples 1 to 3 are not described in the respective gazettes.
Each is designed for a specific purpose. Conversely, each TFT array substrate may be evaluated as having an inappropriate configuration for other purposes. For example, the TFT array substrate of Conventional Example 1 has a channel portion made of p-Si and requires a crystallization step by laser annealing or the like, so that an increase in cost due to capital investment or the like is unavoidable. In addition, since a technically complicated process such as laser annealing is performed, there is a high possibility that the yield will decrease. That is, the TFT array substrate of Conventional Example 1 has a structure that is suitable for the purpose of improving the aperture ratio but is not suitable for the purpose of reducing the cost and preventing the yield from lowering. On the other hand, if laser annealing or the like is not performed in Conventional Example 1, p-
In order to apply Si, a high temperature process is inevitable. When this high-temperature process is included in the process, expensive quartz glass must be used as the glass substrate, and as a result, the cost increases dramatically,
It is out of the question from the viewpoint of cost reduction. Further, although the aperture ratio increases in both of Conventional Examples 1 and 2, since the passivation film is formed over the entire surface,
Since the passivation film absorbs light, a decrease in panel transmittance, that is, a decrease in display brightness is caused. That is, each of the TFT array substrates of Conventional Examples 1 and 2 has a structure that is not suitable for the purpose of preventing a decrease in display brightness. In the third conventional example, the metal anodic oxide film itself can be manufactured at low cost if the conditions are satisfied. However, the increase in cost due to the addition of a new process, the capital investment, and the process management. This causes an increase in cost. Further, an exposed portion between the drain electrode and the source electrode in the channel portion is referred to as a back channel. In the conventional example 3, since no passivation film for protecting the back channel is provided, impurities are contained in the back channel. May be adsorbed. When impurities are adsorbed on the back channel in this manner, the leakage current increases, and as a result, the off characteristics are deteriorated, causing display unevenness and the like.
Further, in the conventional example 3, since a channel portion is formed by depositing and etching before forming a through hole in an insulating film and filling the through hole with an electrode material in a manufacturing process, impurities are formed inside the through hole. May remain, which may cause poor contact and the like. In other words, the TFT array substrate of Conventional Example 3 has a structure that is not suitable for the purpose of preventing variation in performance, reducing cost, and preventing reduction in yield.

As described above, the TFT array substrate has a different structure for each purpose, and cannot necessarily achieve other purposes. Similarly, the manufacturing process of each TFT array substrate is also selected according to the purpose, and other purposes cannot always be achieved by the same manufacturing process.

For example, in a color TFT liquid crystal display device for a vehicle used in a navigation system or the like, it is possible to prevent a cost increase while maintaining a certain level of performance, and to prevent a decrease in yield and the like.
Furthermore, high reliability at high temperature and high humidity is required. The structural features are determined as follows according to the purpose or requirement. That is, in order to reduce the cost, it is necessary that the channel portion be made of a-Si so that expensive quartz glass is not used as the glass substrate, and that the number of steps in the manufacturing process is small. is necessary. When a liquid crystal display device is configured with a liquid crystal panel for color display, the liquid crystal display device needs to be a transmission type having a backlight. In this case, since the channel portion is made of a-Si, if a backlight is provided on the TFT array substrate side, the gate electrode is required to have a light shielding property. Furthermore, in order to stabilize the characteristics of the TFT, it is necessary to provide a passivation film for protecting the back channel portion. However, if provided on the entire surface, the transmittance is reduced, so that only the TFT portion is provided. A configuration in which a passivation film is provided is general.

From such a viewpoint, as a conventional TFT array substrate having a structure suitable for the above purpose, there is a liquid crystal panel provided with a TFT array substrate of Conventional Example 4 shown in FIGS. Here, FIG.
FIG. 2 is a plan view showing a configuration for one pixel in a liquid crystal panel including the TFT array substrate of FIG. Also, FIG.
FIG. 3 is a cross-sectional view showing a cross section taken along line AA ′ in FIG.
FIG. 14 is a sectional view showing a section taken along line BB ′ in FIG.

Hereinafter, a method of manufacturing a liquid crystal panel having a TFT array substrate according to Conventional Example 4 will be described with reference to FIGS. First, Cr and / or
Alternatively, after patterning a gate electrode 101 made of a metal film such as Al, a gate insulating film 107 made of a material such as a silicon oxide film and / or a silicon nitride film, a channel portion 102 made of a-Si, and an n-type a-Si ( Hereinafter, n ⁺ a-
Say Si. ) Are sequentially formed.

Here, when the driving IC is mounted on the liquid crystal panel, the gate electrode and each of the drain electrode 103, the source electrode 104, and the drain bus line 112 formed in a later step are connected to the driving IC. Terminals for mounting the IC must be electrically connected.
Metal wiring (not shown) for making this electrical connection
For example, the same layer and the same material are used for the same layer where the drain electrode 103, the source electrode 104, and the drain bus line 112 are formed. In such a case, the electrical connection between the drain electrode 103 and the metal wiring is
It can be performed only by patterning the metal wiring. However, between the gate bus line 111 to which the plurality of gate electrodes 101 are connected and the layer where the metal wiring is formed,
The gate insulating film 107 is interposed. Therefore, in order to electrically connect the gate electrode 101 and the terminal included in the driving IC, a hole is formed in the gate insulating film 107 so that a through hole ( (Not shown). Therefore, after forming up to the contact layer 108, the through hole is formed.

Thereafter, like the gate electrode 101, Cr
And / or drain electrode 103, source electrode 104, drain bus line 112 formed of a metal film such as Al
Then, the pixel electrode 105 made of a transparent conductive material such as ITO is formed. Thereafter, the contact layer 108 in the channel portion is removed by etching. At this time, FIG.
In the TFT shown in FIG.
-Si is also slightly etched. Such a method of forming an inverted staggered TFT is called channel etching.
This channel etching has the disadvantage that the thickness of a-Si cannot be reduced, but also has the advantage that the characteristics of the TFT are stabilized.

After etching the contact layer 108,
Passivation film 1 made of a material such as silicon nitride film
09 is formed to form a TFT array substrate 300. Here, in Conventional Example 4, the passivation film 109 on the pixel electrode 105 is removed in order to prevent a decrease in panel transmittance due to light absorption of the passivation film, that is, a decrease in display brightness. That is, as shown in FIG. 12, the passivation film 109
5, passivation film opening region 1 over substantially one surface
14 is provided.

The TFT array substrate 3 of the conventional example 4 as described above.
In FIG. 14, the storage capacitor electrode 106 is formed at the same time as the gate electrode by the same patterning process using the same material as the gate electrode 101, as shown in FIG. Further, in the TFT array substrate 300 of the fourth conventional example, the storage capacitor electrode 106 is disposed on the glass substrate 100 in a partial region of the pixel electrode 105 via the gate insulating film 107 acting as a storage capacitor insulating film.
Located on the side. The storage capacitor electrode 106 is an electrode provided to add a large capacity to the pixel electrode 105 and maintain a high holding voltage.

The counter substrate 200 is shown in FIGS.
As shown in FIG. 2, a black matrix layer 220 made of a metal film such as Cr and a color filter 230 are provided on a glass substrate 210, and a protective film 240 and a transparent conductive film such as ITO are further formed thereon. The counter electrode (common electrode) 250 is formed.

After the alignment films 420 and 430 are formed on each of the TFT array substrate 300 and the counter electrode substrate 200 thus obtained, and alignment processing is performed,
A seal pattern (not shown) is formed using a sealant, and the TFT array substrate 300 and the counter electrode substrate 20 are formed.
0 are adhered at a predetermined distance. Further, a liquid crystal 410 is injected into a gap between these two substrates to form a liquid crystal layer 400, and then the liquid crystal panel is sealed to complete a liquid crystal panel. When a polarizing plate, a driving circuit, a housing, and the like are added to this liquid crystal panel, a liquid crystal display device is obtained.

[0021]

However, the TFT array substrate having the structure of the conventional example 4 requires 190 hours in a high temperature and high humidity environment such as 60 ° C. and 90% RH (relative humidity). Although no problem occurs if the device is left for a long time, if the device is left in the high-temperature and high-humidity environment for more than 500 hours, a high density of bright spots will occur around the display area, and the display quality will deteriorate. Had a problem of doing so. That is, the TFT array substrate of Conventional Example 4 cannot maintain a high reliability under a high temperature and high humidity environment for a long time.

In view of the above, the present invention prevents the increase in cost, prevents the yield from lowering, and maintains high reliability in a high-temperature, high-humidity environment for a long time. It is an object of the present invention to provide a TFT array substrate that can be used.

Another object of the present invention is to provide a method of manufacturing the TFT array substrate in which the number of manufacturing steps is not increased as compared with Conventional Example 4 in order to prevent an increase in cost.

[0024]

Means for Solving the Problems In order to solve the above-mentioned problems, the inventor of the present invention carried out cross-sectional observation of a portion where a bright spot defect occurred. As a result, three facts as shown in FIG. 15 were confirmed. The first point is that the storage capacitor electrode 10
That is, the metal film forming No. 6 is corroded and disappeared from the end. Two points are that defects 132 such as cracks exist in the gate insulating film 107 near the corroded portion 131. Third, there are some precipitates around the crack. As a result of metal ion analysis in the liquid crystal panel for the bright spot defect, the liquid crystal material and TFT
Metal ions forming the storage capacitor electrode 106 were detected from the surface of the array substrate. This kind of metal ion is
Naturally, it is not detected from the normal part. The storage capacitor electrode 1 of the gate insulating film 107
The fact that defects 132 such as cracks are likely to occur in the gate insulating film 107 located on the stepped portion such as the end portion of 06, and that the film quality of the stepped portion of the pixel electrode 105 is poor well known.

From the above, the inventors of the present invention speculated that the occurrence of a bright spot defect is caused by the following mechanism.

Since it is in a high-temperature, high-humidity environment, it is highly probable that moisture will enter the liquid crystal panel from outside the liquid crystal panel through a seal pattern or the like that bonds the TFT array substrate 300 and the counter electrode substrate 200 together. . When moisture invades into the liquid crystal panel in this way, if there is a sparse film portion in the pixel electrode 105, the invading moisture becomes
The light passes through a portion of the pixel electrode 105 having a low film quality and a defect 132 such as a crack existing in the gate insulating film 107 and reaches the storage capacitor electrode 106. Also,
The moisture that has reached the storage capacitor electrode 106 is stored in the storage capacitor electrode 1.
Corrosion of the metal film forming 06 is caused. When the metal film is corroded in this manner, a metal oxide (not shown) generated by the corrosion is deposited on the defect 132 such as a crack. As a result, it is presumed that the pixel electrode 105 and the storage capacitor electrode 106 are short-circuited via the metal oxide due to the corrosion, thereby causing a bright spot defect.

Therefore, according to the present invention, at least the moisture that has entered the inside of the liquid crystal panel is at least one of a portion of the pixel electrode 105 having a low film quality and a defect 132 such as a crack existing in the gate insulating film 107. In order to prevent passing through one side, the pixel electrode 10
5, between the corresponding predetermined region and the gate insulating film 107;
And / or a corrosion prevention film is provided on a predetermined region above the pixel electrode 105. Further, in order to suppress an increase in cost, this corrosion prevention film is formed only by changing the pattern in a conventional process of patterning a passivation film or the like. Further, in order to reduce the decrease in light transmittance due to the provision of the corrosion prevention film, the minimum size of the corrosion prevention film that can obtain the above-mentioned effects is defined.

According to the mechanism of the occurrence of the bright spot defect estimated by the inventor of the present invention, it seems that Conventional Examples 1 to 3 can prevent corrosion of the storage capacitor electrode. Originally, since the purposes and the like are different, as will be understood from the description of each, for example, there will be some problems in other aspects, such as cost, and the object of the present invention cannot be achieved. Things.

On the other hand, the present invention solves all of the above-mentioned problems.

Specifically, the present invention provides the following means for solving the above-mentioned problems.

That is, according to the present invention, as a first thin film transistor array substrate, a thin film transistor, a pixel electrode electrically connected to a source electrode of the thin film transistor, and one of the pixel electrodes are formed on a glass substrate. A thin film transistor array substrate used for a liquid crystal panel, having a configuration in which a plurality of pixel components including a storage capacitor electrode provided with a part thereof and an insulating material provided therebetween through an insulator to form a storage capacitor are arranged in a matrix Wherein the storage capacitor electrode is formed of a predetermined metal extending in a first predetermined direction on a plane of the glass substrate, and a direction perpendicular to the first predetermined direction on the plane. A predetermined width in the second predetermined direction that is wider by the first width than the width of the storage capacitor electrode, and is provided between the insulator and the pixel electrode. And / or is provided on the pixel electrode so as to cover above the storage capacitor electrode when viewed from the glass substrate, to prevent moisture from reaching the storage capacitor electrode when the liquid crystal panel is formed, and A thin film transistor array substrate further comprising a corrosion prevention film for preventing corrosion of the predetermined metal constituting the electrode is obtained.

According to the invention, as the second thin film transistor array substrate, in the first thin film transistor array substrate, the storage capacitor electrode is provided separately from a gate electrode of the thin film transistor. And the first width is not less than 6 μm and not more than 20 μm.
The corrosion prevention film has a width of not more than 3 μm and not more than 10 μm from each end of the storage capacitor electrode in the second predetermined direction so as to cover the storage capacitor electrode. Thus, a thin film transistor array substrate characterized by being provided is obtained.

Further, according to the present invention, as the third thin film transistor array substrate, in the first thin film transistor array substrate, the storage capacitor electrode is the thin film transistor of the pixel component adjacent in the second predetermined direction. Wherein the first width is a width of 3 μm or more and 10 μm or less, and the corrosion prevention film is formed in one of the pixel constituent elements by the storage capacitor electrode. A thin film transistor array substrate provided so as to cover the storage capacitor electrode within a range of 3 μm or more and 10 μm or less from an end on the thin film transistor side in the second predetermined direction toward the thin film transistor. Is obtained.

Further, according to the present invention, in any one of the first to third thin film transistor array substrates as a fourth thin film transistor array substrate, the thin film transistor has an inverted staggered structure. Is made of a-Si, and the back channel in the channel is
A thin film transistor array substrate is obtained, wherein the insulator covered by the passivation film and the insulator forming the storage capacitor and the gate insulating film of the thin film transistor are integrally formed.

According to the invention, as a fifth thin film transistor array substrate, in the fourth thin film transistor array substrate, the corrosion prevention film is formed on the pixel electrode by using the same material as the passivation film. Thus, a thin film transistor array substrate characterized by being provided is obtained.

Here, the fifth thin film transistor array substrate can be manufactured by the following method.

That is, a thin film transistor array substrate having a structure in which a plurality of thin film transistors and pixel electrodes having an inverted staggered structure are arranged in a matrix on a glass substrate, A storage capacitor electrode provided on the same layer as the gate electrode of the thin film transistor, and provided on the pixel electrode so as to cover only the upper portion of the storage capacitor electrode and the periphery thereof. In the method for manufacturing a thin film transistor array having a corrosion prevention film, a metal material for forming a gate electrode of the thin film transistor is formed on the glass substrate, and the formed metal material is patterned, Simultaneous formation of gate electrode and storage capacitor electrode Forming an insulating material for forming the passivation film over the entire surface after forming the thin film transistor, and patterning the formed insulating material to simultaneously form the passivation film and the corrosion prevention film. The fifth thin film transistor array substrate can be manufactured by a method for manufacturing a thin film transistor array substrate, comprising the steps of:

Further, according to the present invention, as the sixth thin film transistor array substrate, in the fourth thin film transistor array substrate, the corrosion prevention film is formed of the a-Si thin film.
And a thin film transistor array substrate provided between the insulator and the pixel electrode.

Here, the sixth thin film transistor array substrate can be manufactured as follows.

That is, a thin-film transistor array substrate having a configuration in which a plurality of thin-film transistors and pixel electrodes having an inverted staggered structure are arranged in a matrix on a glass substrate, and the channel portion of the thin-film transistors is a-Si. A storage capacitor electrode provided on the same layer as a gate electrode included in the thin film transistor, an insulator integrally formed with a gate insulating film included in the thin film transistor, above and above the storage capacitor electrode A method of manufacturing a thin film transistor array including a corrosion prevention film provided between the insulator and the pixel electrode so as to cover only the periphery of the thin film transistor array, wherein the metal material for forming a gate electrode of the thin film transistor array is A film is formed on a glass substrate, and the formed metal material is patterned. By the steps of forming said storage capacitor electrode and the gate electrode at the same time, after the formation of the gate insulating film, is deposited the a-Si, it was formed a
Manufacturing the sixth thin film transistor array substrate by a method for manufacturing a thin film transistor array substrate, the method further comprising: simultaneously forming the channel portion and the storage capacitor electrode by patterning Si. Can be.

Further, according to the present invention, as the seventh thin film transistor array substrate, in the fourth thin film transistor array substrate, the corrosion prevention film comprises the first and second thin film transistor array substrates.
Wherein the first corrosion prevention film is provided on the pixel electrode using the same material as the passivation film, and the second corrosion prevention film is Using a-Si, a thin film transistor array substrate provided between the insulator and the pixel electrode is obtained.

Here, the seventh thin film transistor array substrate can be manufactured by the following method.

That is, a thin film transistor array substrate having a structure in which a plurality of thin film transistors and pixel electrodes having an inverted staggered structure are arranged in a matrix on a glass substrate, and a channel portion of the thin film transistor is a-Si. And a passivation film provided on the back channel in the channel portion, a storage capacitor electrode provided on the same layer as the gate electrode of the thin film transistor, and a gate insulating film of the thin film transistor. A corrosion prevention film provided between the insulator and the pixel electrode and on the pixel electrode so as to cover only the integrally formed insulator and the upper part of the storage capacitor electrode and the periphery thereof; The method of manufacturing a thin film transistor array, comprising: Forming a metal material for forming a gate electrode having on the glass substrate, and patterning the formed metal material to simultaneously form the gate electrode and the storage capacitor electrode; and Forming a gate insulating film, forming the a-Si film, and patterning the formed a-Si film to form the channel portion and the storage capacitor electrode simultaneously; and forming the passivation film. Forming an insulating material over the entire surface after the formation of the thin film transistor, and patterning the formed insulating material to simultaneously form the passivation film and the corrosion prevention film. The seventh thin film transistor array substrate can be manufactured by the characteristic method of manufacturing a thin film transistor array substrate.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

The active matrix type liquid crystal display device according to the embodiment of the present invention has a structure schematically shown by an equivalent circuit in FIG.

In FIG. 1, reference numeral 111 denotes a gate bus line forming a scanning line driven by the gate bus line driver 310, and 112 denotes a drain bus forming a signal line driven by the drain bus line driver 320. Lines are shown. Also, 330
Has a gate electrode electrically connected to the gate bus line 111 and a drain electrode connected to the drain bus line 1.
12 shows a TFT electrically connected to the reference numeral 105.
Denotes a pixel electrode connected to the TFT 330 and formed of a transparent conductive film such as ITO. Furthermore,
TFT 330 and pixel electrode 1 arranged in a matrix
A broken line frame surrounding the area 05 indicates the TFT array substrate 300 and the counter electrode substrate 200.
These two substrates are arranged to face each other via a liquid crystal (or a liquid crystal layer).

The storage capacitor C _ST and the liquid crystal capacitor C _LC are connected in parallel to the source electrode of the TFT 330. Here, the storage capacitor C _ST is connected to the pixel electrode 10
5 and the pixel electrode 105 is a capacitive element formed by a storage capacitor electrode disposed via an insulating film in the direction of the glass substrate on the TFT 330 side with respect to the pixel electrode 105. On the other hand, the liquid crystal capacitive element _CLC is Liquid crystal (or liquid crystal layer)
Is a capacitive element formed by a counter electrode (or a common electrode and a display electrode) on a counter electrode substrate disposed through the substrate.

Here, in the liquid crystal display device shown in FIG. 1, a selection pulse is sequentially applied to the gate bus line 111 by the gate bus line driver 310 during scanning. When a selection pulse is applied to a certain gate bus line 111, that gate bus line 1
The plurality of TFTs 330 connected to 11 are simultaneously turned on while the selection pulse is being applied. that time,
The pixel electrode 105 connected to the source electrode of each TFT 330 in the conductive state is charged with the signal voltage applied to the drain bus line 112. Next, when a non-selection pulse is applied to the gate bus line 111, the TFT 330 in the conductive state is turned off, while the pixel electrode 105 holds the charged signal voltage. to continue. The held signal voltage is rewritten by the next signal voltage when the corresponding TFT is turned on again.

Hereinafter, some embodiments of the present invention represented by such an equivalent circuit will be described with reference to the drawings.

(First Embodiment) A TFT array substrate according to a first embodiment of the present invention has a structure as shown in FIGS. Here, FIG. 2 is a plan view showing a configuration for one pixel of the TFT array substrate of the present embodiment. FIG. 3 is a sectional view showing a section taken along line AA ′ in FIG. 2, and FIG. 4 is a sectional view taken along line BB in FIG.
It is sectional drawing which shows the cross section along the 'line.

As understood from FIGS. 2 and 3, the TFT 330 is provided with a gate electrode 101 connected to a gate bus line 111 on a glass substrate 100 so as to cover the gate electrode 101. A gate insulating film 107 is provided over the entire surface of the glass substrate 100. A channel portion 102 made of a-Si is provided in a region above the gate electrode 101 of the gate insulating film 107, and each of the channel portions 102 has a contact made of n ⁺ a-Si for achieving ohmic contact. The drain electrode 103 and the source electrode 104 are connected through the layer 108. Drain electrode 103
Are connected to the drain bus line 112 to transmit a signal voltage. The source electrode 104 is connected to the pixel electrode 105. Further, a passivation film 109 is provided on the TFT 330 in order to protect the back channel 113 included in the channel portion 102.

As understood from FIGS. 2 and 4, in the present embodiment, the storage capacitor electrode 106 provided on the glass substrate 100, the gate insulating film 107 interposed as a dielectric, and the pixel electrode A storage capacitor element is formed by a part of the region 105.

Here, the feature of this embodiment is that a corrosion prevention film 110 is provided in a region above the storage capacitor electrode 106 on the pixel electrode 105. Also,
As apparent from FIGS. 2 and 4, the corrosion protection film 110 is formed.
Is formed by removing the passivation film 109, which is conventionally removed over the entire surface of the pixel electrode 105, so as to leave a portion above the storage capacitor electrode 106, as shown in FIG. I have. That is, the passivation film opening region 114 from which the passivation film 109 is removed is provided over almost the entire surface of the pixel electrode 105 in the conventional example 4 (FIG. 12).
In the present embodiment, the storage capacitor electrode 106 is used.
Is divided into two parts so as to straddle the upper part of. More precisely, the corrosion prevention film 110 covers an area as described below.

That is, the passivation film 10 provided on the pixel electrode 105 and acting as the corrosion prevention film 110
9 is a defect 132 such as a crack in the gate insulating film 107.
In which the end portion of the storage capacitor electrode 106 in which the pits easily occur is covered.

Here, by observing the cross section of the defective portion of the bright spot defect which was performed to solve the problem of the conventional example 4, the defect 132 such as a crack existing in the gate insulating film 107 was found to be an end face of the storage capacitor electrode 106. It has been confirmed that a large amount exists within a range of from 2 μm to 2 μm. Further, the alignment accuracy in the photolithography process is usually 1 μm or less. Therefore, the overlap amount of the corrosion prevention film 110 with respect to the storage capacitor electrode 106 is 3
It is sufficient if the thickness is at least μm. On the other hand, the passivation film 109 and the corrosion prevention film 1 are formed on the pixel electrode 105.
If 10 is left unnecessarily, as described above, a decrease in panel transmittance due to light absorption of the silicon nitride film, that is, a decrease in display brightness is caused. Therefore, the passivation film 10
As a result of examining the relationship between the area covered by 9 and the decrease in panel transmittance, if the area covered by the passivation film 109 is within 10 μm from each end of the storage capacitor electrode 106, the panel transmission becomes substantially problematic. No reduction in rate was found to occur. Therefore, in the present embodiment,
The amount of overlap of the corrosion prevention film 110 with respect to the storage capacitor electrode 106 was set to 3 to 10 μm, and the passivation film 109 on the pixel electrode 105 in the remaining area was removed by etching to suppress a decrease in the transmittance of the panel.

In the present embodiment having such a configuration, the T
The FT array substrate has a relatively dense film quality even if a defect 132 such as a crack, which has conventionally acted as an intrusion path for moisture from the outside, exists in the gate insulating film 107. Since the corrosion prevention film 110 formed of an insulating material such as a silicon nitride film plays a role of blocking the intrusion path, the corrosion of the storage capacitor electrode 106 can be prevented. As a result, in this embodiment, it is possible to prevent the occurrence of a bright spot defect caused by a short circuit between the storage capacitor electrode 106 and the pixel electrode 105.

Hereinafter, a method of manufacturing a TFT array substrate according to the present embodiment will be described with reference to FIGS.

First, Cr, Al,
A metal film such as Ta is sputtered to a thickness of 100 to 300 nm.
Thereafter, the gate electrode 101 and the storage capacitor electrode 106 are formed by patterning into a predetermined shape by using a photolithography technique, followed by etching. Next, a silicon nitride film serving as a gate insulating film 107 is formed to a thickness of 200 to 600 nm by a plasma CVD method mainly containing silane and ammonia gas, and a channel portion 102 is formed to a channel portion 102 using a plasma CVD method mainly containing silane.
-Si to a film thickness of 50 to 300 nm, and furthermore, a channel electrode 102 and a drain electrode 10 to be formed in a later step by a plasma CVD method using silane and phosphine gas as main components.
3 and n ⁺ a-Si to be a contact layer 108 for achieving ohmic contact with the source electrode 104 are sequentially deposited to a thickness of 30 to 100 nm. After that, the channel portion 102 and the contact layer 108 are patterned into a predetermined island-like shape by photolithography, and then etched. Further, a patterning step of etching and removing a region of the gate insulating film 107 corresponding to a portion where a terminal for mounting a driver IC is provided is performed, and a gate bus line 111 and a metal wiring (FIG. (Not shown) are formed.

Next, a metal film of Cr, Al, Ta, or the like is formed by sputtering to a thickness of 100 to 300 nm, and then patterned into a predetermined shape, and etched to form a drain electrode 103, a source electrode 104, and a drain bus. Line 11
Form 2 and so on. Subsequently, a transparent conductive material such as ITO is formed by sputtering, patterned into a predetermined shape, and then etched to form the pixel electrode 105. Thereafter, in order to divide the contact layer 108 into a source electrode side and a drain electrode side, an unnecessary contact layer on the channel portion 102 is removed by etching. Thereafter, a silicon nitride film having a thickness of 100 to 400 nm is formed by a plasma CVD method containing silane and ammonia gas as main components, and then patterned into a predetermined shape and etched to protect the back channel 113. Passivation film 10
By forming 9 and corrosion prevention film 110, TFT array substrate 300 of the present embodiment is obtained.

Here, referring again to the features of the present embodiment, the passivation film 109 and the corrosion prevention film 110 are integrally formed using the same material and the same patterning process, and the region which functions as the corrosion prevention film 110 is formed. Has a structure that covers the storage capacitor electrode 106 and the end.

Further, the counter electrode substrate is provided with a black matrix layer (not shown) made of a metal film such as Cr and a color filter on a glass substrate (not shown), and then a protective film (not shown). And a counter electrode (not shown). Further, an alignment film (not shown) is formed on each of the TFT array substrate 300 and the counter electrode substrate to perform an alignment process, a seal pattern (not shown) is formed, and the resultant is overlaid and baked. Inject and seal to complete the liquid crystal panel.

Here, in order to verify the effect of the TFT array substrate of the present embodiment, the TFT array substrate of Conventional Example 4 (see FIGS. 12 to 14) and the TFT array substrate of the present embodiment were used. A liquid crystal panel and a liquid crystal display device were prepared and left in a high-temperature and high-humidity environment of 60 ° C. and 90% RH.
As a result, when the TFT array substrate of Conventional Example 4 is used,
In about 200 to 500 hours, the display quality was degraded due to the occurrence of crowded bright spot defects.
When an FT array substrate was used, no increase in bright spot defects occurred even after 1000 hours.

In this embodiment, since the corrosion prevention film 110 is formed integrally and simultaneously using the same patterning step as the patterning step for providing the passivation film 109, the number of patterning steps is the same as that of the conventional example 4.
This is the same as the above step, and there is no possibility that the step becomes complicated. That is, the cost does not increase due to an increase in the number of steps and the like as compared with the conventional example 4. Further, in the present embodiment, a decrease in the yield due to the complicated process is suppressed as compared with Conventional Example 4.

(Second Embodiment) A TFT array substrate according to a second embodiment of the present invention has a structure as shown in FIGS. Here, FIG. 5 is a plan view showing a configuration of one pixel in the TFT array substrate of the present embodiment, and FIG. 6 is a cross-sectional view showing a cross section taken along line BB ′ in FIG. . The cross section along the line AA 'in FIG. 5 is the same as that of the first embodiment described above. Therefore, if necessary, refer to FIG. It is omitted.

The TFT array substrate of this embodiment is similar to that of FIG.
As shown in FIG. 6, a corrosion prevention film 115 composed of a-Si and n ⁺ a-Si is provided in a region above the storage capacitor electrode 106 on the gate insulating film 107, and the corrosion prevention film 115 and A pixel electrode 105 formed so as to cover the gate insulating film 107; a corrosion prevention film 115; a gate insulating film 107;
6 constitute a storage capacitor element. Here, the corrosion prevention film 115 is formed by the TFT 33 as described later.
0, using the same material as the channel portion 102 and the contact layer 108 in the same step as the step of etching the channel portion 102 into an island shape.

In this embodiment, a structure in which the corrosion prevention film 115 made of the same material as the channel portion 102 and the contact layer 108 which are the semiconductor layers covers the storage capacitor electrode 106 on the gate insulating film 107 and the end portion. It is provided in. Therefore, as in the first embodiment, even if a defect 132 such as a crack, which has conventionally functioned as a path for ingress of moisture from the outside, exists in the gate insulating film 107, corrosion prevention is not performed. The film 115 plays a role of blocking the intrusion path, so that corrosion of the storage capacitor electrode 106 can be prevented. As a result, the TFT array substrate of the present embodiment can prevent the occurrence of a bright spot defect due to a short circuit between the storage capacitor electrode 106 and the pixel electrode 105. In the present embodiment, as in the first embodiment, the amount of overlap of the corrosion prevention film 115 with the storage capacitor electrode 106 is set to 3 to 10 μm from each end. In addition, the passivation film 109 on the pixel electrode 105 is substantially entirely etched away in consideration of the alignment accuracy in the photolithography process.

Hereinafter, a method of manufacturing the TFT array substrate according to the present embodiment having such a configuration will be described with reference to FIGS.

First, Cr, Al,
A metal film such as Ta is sputtered to a thickness of 100 to 300 nm.
Thereafter, the gate electrode 101 and the storage capacitor electrode 106 are formed by patterning into a predetermined shape by using a photolithography technique, followed by etching.

Thereafter, a silicon nitride film to be the gate insulating film 107 is formed to a thickness of 200 to 600 nm by plasma CVD using silane and ammonia gas as main components, and the channel portion 1 is formed by plasma CVD using silane as main component.
A-Si of 02 to a film thickness of 50 to 300 nm,
Plasma CVD mainly containing silane and phosphine gas
According to the method, n ⁺ a-Si serving as a contact layer 108 for electrically connecting the channel portion 102 to the drain electrode 103 and the source electrode 104 formed in a later step is sequentially deposited to a thickness of 30 to 100 nm. . Next, after the channel portion 102 and the contact layer 108 are patterned into a predetermined island shape by photolithography technology,
At the same time as the etching process, a corrosion prevention film 115 made of the same semiconductor layer as the channel portion 102 and the contact layer 108 is formed so as to cover the storage capacitor electrode 106 and its end.

Thereafter, a patterning step of etching and removing a region of the gate insulating film 107 corresponding to a portion for providing a terminal for mounting a driver IC for driving is performed, and a gate bus line 111 and a metal wiring are formed as in the conventional example. (Not shown), a through-hole (not shown) is formed for electrical connection with the device. Next, a metal film of Cr, Al, Ta, or the like is formed by sputtering to a thickness of 100 to 300 nm.
The metal film is patterned into a predetermined shape, and is etched to form a drain electrode 103, a source electrode 104, and a drain bus line 112. Subsequently, a transparent conductive material such as ITO is formed by sputtering, patterned into a predetermined shape, and then etched to form the pixel electrode 105. Thereafter, in order to divide the contact layer 108 into a source electrode side and a drain electrode side, an unnecessary contact layer on the channel portion 102 is removed by etching. Next, in order to protect the back channel 113, a silicon nitride film is formed to a thickness of 100 to 400 nm by a plasma CVD method containing silane and ammonia gas as main components, and then patterned into a predetermined shape and etched. Of the TFT of the present embodiment
An array substrate is obtained.

In this embodiment, too, the corrosion prevention film 11
5 is formed using the same patterning step as the step of patterning the channel portion 102 and the contact layer 108 in an island shape, the number of patterning steps is the same as that of the conventional example 4, and the steps may be complicated. There is no. Therefore, in the present embodiment, compared to the conventional example 4, there is no increase in cost due to an increase in the number of steps and the like.
Further, in the present embodiment, compared to Conventional Example 4,
The decrease in yield due to the complexity of the process is also suppressed.

(Third Embodiment) As shown in FIGS. 7 and 8, a TFT array substrate according to a third embodiment of the present invention includes both the first and second embodiments. The structure which applied the structure of is provided. Here, FIG. 7 is a plan view showing a configuration for one pixel in the TFT array substrate of the present embodiment, and FIG. 8 is a cross-sectional view showing a cross section taken along line BB ′ in FIG. . AA in FIG.
The cross section along the line ´ is the same as that of the first embodiment described above, and therefore, if necessary, reference is made to FIG. 3 and the drawing and description are omitted.

The TFT array substrate of this embodiment is similar to that of FIG.
As shown in FIG. 8, a corrosion prevention film 115 composed of a-Si and n ⁺ a-Si is provided in a region above the storage capacitor electrode 106 on the gate insulating film 107, and further, the pixel electrode 105 A corrosion prevention film 110 made of the same material as the passivation film 109 is provided in a region above the storage capacitor electrode 106. A pixel electrode 105 formed so as to cover the corrosion prevention film 115 and the gate insulating film 107; a corrosion prevention film 115 and the gate insulating film 107;
Constitutes a storage capacitance element. Here, the corrosion prevention film 115 is made of TFT as in the second embodiment.
Channel section 102 and contact layer 10 at 330
8 and is formed by the same process as the process of etching the channel portion 102 into an island shape. In addition, the corrosion prevention film 110 is conventionally formed of the pixel electrode 10.
5. Passivation film 1 removed over the entire surface on
09, as shown in FIG. 2, so as to leave a portion above the storage capacitor electrode 106. That is, the passivation film opening region 114 from which the passivation film 109 is removed is provided over almost the entire surface of the pixel electrode 105 in the conventional example 4 (see FIG. 12), but in the present embodiment, , And is divided into two parts so as to straddle the upper part of the storage capacitor electrode 106.

In the present embodiment having such a configuration, T
In the FT array substrate, as in the first and second embodiments, for example, a defect 132 such as a crack which has conventionally acted as an intrusion path for moisture from the outside exists in the gate insulating film 107. Even when the corrosion prevention film 110 is formed, both the corrosion prevention film 110 on the pixel electrode 105 and the corrosion prevention film 115 on the gate insulating film 107 serve to close the invasion path, thereby preventing the corrosion of the storage capacitor electrode 106. can do. As a result, the TFT array substrate of the present embodiment can more reliably prevent the occurrence of a bright spot defect caused by a short circuit between the storage capacitor electrode 106 and the pixel electrode 105. In this embodiment, as in the first embodiment, the amount of overlap of the corrosion protection films 110 and 115 with respect to the storage capacitor electrode 106 is set to 3 to 10 μm from each end of the storage capacitor electrode 106. .

Hereinafter, a method of manufacturing the TFT array substrate according to the present embodiment having such a configuration will be described with reference to FIGS.

First, Cr, Al,
A metal film such as Ta is sputtered to a thickness of 100 to 300 nm.
Thereafter, the gate electrode 101 and the storage capacitor electrode 106 are formed by patterning into a predetermined shape by using a photolithography technique, followed by etching. After forming the gate electrode 101 and the storage capacitor electrode 106, the plasma C containing silane and ammonia gas as main components
The silicon nitride film to be the gate insulating film 107 is formed to a thickness of 200 to 600 nm by the VD method, and the a-S to be the channel part 102 is formed by the plasma CVD method containing silane as a main component.
i is set to a thickness of 50 to 300 nm, and the channel portion 102 is electrically connected to the drain electrode 103 and the source electrode 104 formed in a later step by a plasma CVD method using silane and a phosphine gas as main components. N ⁺ a-Si to be a contact layer 108 of
nm.

After that, the channel portion 102 and the contact layer 108 are patterned into a predetermined island shape by photolithography and etched, and at the same time, the corrosion prevention film 115 made of the same semiconductor layer as the channel portion 102 and the contact layer 108 is formed. To the storage capacitor electrode 10
6 so as to cover the upper part and the upper part of its end.
After that, the driver IC for driving in the gate insulating film 107
A patterning step of etching and removing a region corresponding to a portion where a terminal for mounting the semiconductor device is to be performed is performed.
And a through-hole (not shown) for conducting between the holes.

Next, a metal film such as Cr, Al, Ta
A sputter film is formed to a thickness of 0 to 300 nm, then patterned into a predetermined shape, and etched to form a drain electrode 1.
03, a source electrode 104 and a drain bus line 112 are formed. Subsequently, a transparent conductive material such as ITO is formed by sputtering, patterned into a predetermined shape, and then etched to form the pixel electrode 105. Thereafter, in order to divide the contact layer 108 into a source electrode side and a drain electrode side, an unnecessary contact layer on the channel portion 102 is removed by etching. Thereafter, a silicon nitride film having a thickness of 100 to 400 nm is formed by a plasma CVD method containing silane and ammonia gas as main components, and then patterned into a predetermined shape and etched to protect the back channel. By forming the film 109 and the corrosion prevention film 110, the TFT array substrate of the present embodiment can be obtained.

Here, also in the present embodiment, the corrosion prevention film 110 is formed integrally and simultaneously using the same patterning process as the patterning process for providing the passivation film 109, and the corrosion prevention film 115 is formed on the channel portion 102 and the contact layer 108. Is formed using the same patterning step as the step of patterning into islands, so that the number of patterning steps is the same as that of the conventional step, and there is no possibility that the steps become complicated. Therefore, the present embodiment is similar to Conventional Example 4.
There is no increase in cost as compared with. Further, in the present embodiment, a decrease in the yield due to the complicated process is suppressed as compared with Conventional Example 4.

Although the first to third embodiments have been described above, the present invention is not limited to these embodiments, and various changes can be made under the concept. For example, the gate electrode, storage capacitor electrode, source / drain electrode, etc. can be composed of other metal materials or composite films, and the gate insulating film and passivation film corrosion prevention film are formed of various insulating films and composite films. Can be.

Further, for example, as shown in FIGS. 9 to 11, the storage capacitor electrode can be formed as a part of the gate bus line.

FIG. 9 shows a gate electrode 101 (gate bus line 11) of a pixel adjacent to a storage capacitor electrode 106.
For the TFT array substrate formed integrally with 1),
This is an application of the concept of the first embodiment. That is,
In the TFT array substrate shown in FIG. 9, a film made of the same material as the passivation film 109 is used as the corrosion prevention film 110. In this case,
Considering one end of the storage capacitor electrode 106 to be one, the amount of overlap of the corrosion protection film 110 is 3
To within 10 μm.

FIG. 10 shows a gate electrode 101 (gate bus line 11) of a pixel adjacent to a storage capacitor electrode 106.
For the TFT array substrate formed integrally with 1),
This is an application of the concept of the second embodiment. That is,
In the TFT array substrate shown in FIG. 10, a semiconductor film made of a-Si and n ⁺ a-Si is provided as the corrosion prevention film 115. In this case, too, considering the end of the storage capacitor electrode 106 as one, the overlap amount of the corrosion prevention film 115 is 3 to 1 from the end.
It should be within 0 μm.

FIG. 11 shows a gate electrode 101 (gate bus line 11) of a pixel adjacent to a storage capacitor electrode 106.
For the TFT array substrate formed integrally with 1),
This is an application of the concept of the third embodiment. That is,
In the TFT array substrate shown in FIG. 11, the passivation film 10 is used as the corrosion prevention films 110 and 115.
9, a-Si and n @ + a-S
and a semiconductor film made of i. Also in this case, assuming that one end of the storage capacitor electrode 106 is regarded as one, the amount of overlap of the corrosion prevention film 115 is within 3 to 10 μm from the end.

[0085]

As described above, according to the present invention,
A corrosion prevention film is provided between the pixel electrode forming the storage capacitor element and the insulator film, or on the pixel electrode, or both, so as to cover almost only the upper part including the end of the storage capacitor electrode. Since the gate insulating film has a structure that can reinforce the upper end of the storage capacitor electrode where cracks and the like are likely to occur in the gate insulating film, moisture from the outside can enter the liquid crystal panel in a high temperature and high humidity environment. In the event of intrusion, even if defects such as cracks, which conventionally acted as a moisture intrusion path, exist in the gate insulating film, the corrosion prevention film plays a role in blocking the intrusion path. From
A TFT array substrate capable of preventing corrosion of the storage capacitor electrode can be obtained. As a result, according to the present invention, it is possible to prevent a reduction in display quality such as occurrence of a bright spot defect caused by a short circuit between the storage capacitor electrode and the pixel electrode.

Further, according to the present invention, since the corrosion prevention film covers almost only above the storage capacitor electrode and above the end portion thereof, the panel transmittance, that is, the display brightness is not reduced. Thus, a TFT array substrate that can prevent the occurrence of a bright spot defect can be obtained.

Further, according to the present invention, the corrosion prevention film is formed simultaneously by the patterning step of providing the passivation film, the step of patterning the channel portion and the contact layer in an island shape, or both of the steps. Complicated steps can be prevented, and cost can be prevented. Furthermore, in the present embodiment, there is no reduction in yield due to complicated processes.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a plan view showing the structure of one pixel of the TFT array substrate according to the first embodiment.

FIG. 3 is a sectional view showing a section taken along line AA ′ in FIG. 2;

FIG. 4 is a sectional view showing a section taken along line BB ′ in FIG. 2;

FIG. 5 is a plan view illustrating a structure of one pixel of a TFT array substrate according to a second embodiment.

FIG. 6 is a sectional view showing a section taken along line BB ′ in FIG. 5;

FIG. 7 is a plan view illustrating a structure of one pixel of a TFT array substrate according to a third embodiment.

FIG. 8 is a sectional view showing a section taken along line BB ′ in FIG. 7;

FIG. 9 is a plan view showing an application example of the first embodiment.

FIG. 10 is a plan view showing an application example of the second embodiment.

FIG. 11 is a plan view showing an application example of the third embodiment.

FIG. 12 is a plan view showing a structure for one pixel of a liquid crystal display device including a TFT array substrate of Conventional Example 4.

FIG. 13 is a sectional view showing an AA ′ section in FIG. 12;

FIG. 14 is a cross-sectional view showing a BB ′ cross section in FIG. 12;

FIG. 15 is a cross-sectional view showing the cause of the occurrence of a bright spot defect in Conventional Example 4.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Glass substrate 101 Gate electrode 102 Channel part 103 Drain electrode 104 Source electrode 105 Pixel electrode 106 Storage capacitor electrode 107 Gate insulating film 108 Contact layer 109 Passivation film 110 Corrosion prevention film 111 Gate bus line 112 Drain bus line 113 Back channel 114 Passivation film Opening area 115 Corrosion prevention film 200 Counter electrode substrate 300 TFT array substrate 310 Gate bus line driver 320 Drain bus line driver 330 TFT

Claims (10)

(57) [Claims] 1. A thin film transistor over a glass substrate, a pixel electrode electrically connected to a source electrode of the thin film transistor, and a part of the pixel electrode and an insulator to form a storage capacitor. In a thin film transistor array substrate used for a liquid crystal panel, a plurality of pixel components each having a storage capacitor electrode provided through a thin film transistor array substrate are arranged in a matrix. Wherein the storage capacitor electrode is formed of a predetermined metal extending in a first predetermined direction in a second predetermined direction on the plane, which is a direction perpendicular to the first predetermined direction. The storage capacitor has a predetermined width that is wider by a first width than the storage capacitor and has a predetermined width between the insulator and the pixel electrode and / or on the pixel electrode as viewed from the glass substrate. A corrosion prevention film provided so as to cover an upper part of the electrode, for preventing moisture from reaching the storage capacitor electrode when the liquid crystal panel is formed, and for preventing corrosion of the predetermined metal forming the storage capacitor electrode; A thin film transistor array substrate, further comprising: 2. The thin film transistor array substrate according to claim 1, wherein the storage capacitor electrode is provided separately from a gate electrode of the thin film transistor, and the first width is 6 μm to 20 μm. The corrosion prevention film covers the storage capacitor electrode within a wide range of 3 μm or more and 10 μm or less from each end in the second predetermined direction of the storage capacitor electrode. A thin film transistor array substrate provided. 3. The thin film transistor array substrate according to claim 1, wherein the storage capacitor electrode has a structure that is integrated with a gate electrode of the thin film transistor of the pixel component adjacent in the second predetermined direction. The first width is a width of 3 μm or more and 10 μm or less, and the corrosion prevention film is formed in one of the pixel components.
The storage capacitor electrode is provided so as to cover the storage capacitor electrode within a range of 3 μm or more and 10 μm or less from an end of the thin film transistor side in the second predetermined direction toward the thin film transistor. Thin film transistor array substrate. 4. The thin film transistor array substrate according to claim 1, wherein the thin film transistor has an inverted staggered structure, and a channel portion of the thin film transistor is a-Si.
The back channel in the channel portion is covered with a passivation film, and the insulator forming the storage capacitor and the gate insulating film of the thin film transistor are formed integrally. Thin film transistor array substrate. 5. The thin film transistor array substrate according to claim 4, wherein the corrosion prevention film is provided on the pixel electrode using the same material as the passivation film. . 6. The thin film transistor array substrate according to claim 4, wherein the corrosion prevention film is provided between the insulator and the pixel electrode using the a-Si. Thin film transistor array substrate. 7. The thin film transistor array substrate according to claim 4, wherein the corrosion prevention film is composed of first and second corrosion prevention films, and the first corrosion prevention film is formed of the first and second passivation films. The same material is provided on the pixel electrode, and the second corrosion prevention film is provided between the insulator and the pixel electrode using the a-Si. A thin film transistor array substrate characterized by the above-mentioned. 8. A thin film transistor array substrate having a structure in which a plurality of thin film transistors and a plurality of pixel electrodes each having an inverted staggered structure are arranged in a matrix on a glass substrate, and the thin film transistor is arranged on a back channel of a channel portion of the thin film transistors. A storage capacitor electrode provided on the same layer as the gate electrode of the thin film transistor, and provided on the pixel electrode so as to cover only the upper portion of the storage capacitor electrode and the periphery thereof. In the method for manufacturing a thin film transistor array provided with a corrosion prevention film, a metal material for forming a gate electrode of the thin film transistor is formed on the glass substrate, and the formed metal material is patterned, Forming a gate electrode and the storage capacitor electrode simultaneously And forming an insulating material for forming the passivation film over the entire surface after the formation of the thin film transistor, and patterning the formed insulating material to simultaneously form the passivation film and the corrosion prevention film. And a method for manufacturing a thin film transistor array substrate. 9. A thin film transistor array substrate having a structure in which a plurality of thin film transistors and pixel electrodes having an inverted staggered structure are arranged in a matrix on a glass substrate, and a channel portion of the thin film transistors is a-Si. A storage capacitor electrode provided on the same layer as a gate electrode included in the thin film transistor, an insulator integrally formed with a gate insulating film included in the thin film transistor, above and above the storage capacitor electrode A method of manufacturing a thin film transistor array including a corrosion prevention film provided between the insulator and the pixel electrode so as to cover only the periphery of the thin film transistor array, wherein the metal material for forming a gate electrode of the thin film transistor array is A film is formed on a glass substrate, and the formed metal material is patterned. Thereby, simultaneously forming the gate electrode and the storage capacitor electrode; and forming the a-Si film after forming the gate insulating film, and patterning the formed a-Si film. Forming a channel portion and the storage capacitor electrode at the same time. 10. A thin film transistor array substrate having a structure in which a plurality of thin film transistors and pixel electrodes each having an inverted staggered structure are arranged on a glass substrate in a matrix, and a channel portion of each of the thin film transistors is a-Si. And a passivation film provided on the back channel in the channel portion, a storage capacitor electrode provided on the same layer as the gate electrode of the thin film transistor, and a gate insulating film of the thin film transistor. A corrosion prevention film provided between the insulator and the pixel electrode and on the pixel electrode so as to cover only the integrally formed insulator and the upper part of the storage capacitor electrode and the periphery thereof; A method of manufacturing a thin film transistor array, comprising: Forming a metal material for forming a gate electrode on the glass substrate, and patterning the formed metal material to simultaneously form the gate electrode and the storage capacitor electrode; and Forming an insulating film, forming the a-Si film, and patterning the formed a-Si film to simultaneously form the channel portion and the storage capacitor electrode; and forming the passivation film. Forming an insulating material over the entire surface after the formation of the thin film transistor, and patterning the formed insulating material to simultaneously form the passivation film and the corrosion prevention film. Of manufacturing a thin film transistor array substrate.