KR100202232B1 - Structure and fabrication method of liquid crystal display device - Google Patents

Structure and fabrication method of liquid crystal display device Download PDF

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KR100202232B1
KR100202232B1 KR1019960013975A KR19960013975A KR100202232B1 KR 100202232 B1 KR100202232 B1 KR 100202232B1 KR 1019960013975 A KR1019960013975 A KR 1019960013975A KR 19960013975 A KR19960013975 A KR 19960013975A KR 100202232 B1 KR100202232 B1 KR 100202232B1
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insulating film
substrate
electrode
liquid crystal
crystal display
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KR1019960013975A
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Korean (ko)
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KR970071096A (en
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구동효
박재용
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구자홍
엘지전자주식회사
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133345Insulating layers
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

본 발명은 투명기판, 게이트전극, 게이트절연막층, 반도체층, 소스전극과 드레인전극을 포함하는 액정표시장치의 제조방법에 있어서 상기 게이트절연막을 가스유량비 SiH4: O2가 1: 1020이고, 기판의 온도가 350이하이고, 희석가스로 N2을 사용하는 조건에서 투명기판에 증착하여 형성하는 제조방법을 적용한다.The present invention is a transparent substrate, a gate electrode, a gate insulating layer, a semiconductor layer, a gas flow rate SiH the gate insulating film in the manufacturing method of the liquid crystal display device comprising a source electrode and a drain electrode 4: O 2 is 1: 10 20, substrate temperature is 350 Or less, and in conditions using N 2 as a diluent gas applying the manufacturing method of forming by deposition the transparent substrate.

이와 같은 제조방법은 게이트전극을 형성한 후 400이상의 고온으로 절연막을 증착하지 않으므로 게이트전극 등의 금속이 스트레스를 받아서 힐락이 발생할 염려가 없으며, 일반적으로 저항이 높은 고융점 물질을 사용하는 것보다 저항이 낮은 저융점 물질을 사용할 수 있기 때문에 전도도를 향상시킬 수 있다.This manufacturing method is 400 after forming the gate electrode Since the insulating film is not deposited at the high temperature, there is no fear of heel lock due to stress of the metal such as the gate electrode. Can be improved.

Description

액정표시장치의 제조방법 및 액정표시장치의 구조Manufacturing Method of Liquid Crystal Display and Structure of Liquid Crystal Display

제1도는 종래의 기술을 설명하기 위한 액정표시장치의 단면도.1 is a cross-sectional view of a liquid crystal display device for explaining the conventional technology.

제2도는 종래의 기술을 설명하기 위한 액정표시장치의 평면도.2 is a plan view of a liquid crystal display device for explaining the conventional technology.

제3도는 제2도의-선의 단면도.3 is the second - Section of the line.

제4도는 본 발명에 따른 액정표시장치의 실시예를 설명하기 위한 공정 단면도.4 is a cross-sectional view for explaining an embodiment of a liquid crystal display device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11,12 : 투명기판 15 : 화소전극11,12: transparent substrate 15: pixel electrode

16 : TFT 17 : 공통전극16 TFT 17 Common electrode

13 : 스페이서 14 : 액정13 spacer 14 liquid crystal

18 : 게이트버스선 19 : 소스버스선18: gate bus line 19: source bus line

35 : 에치스토퍼층 18a : 게이트전극35: etch stopper layer 18a: gate electrode

19a : 소스전극 19b : 드레인전극19a: source electrode 19b: drain electrode

23 : 제1절연막 22 : 반도체층23: first insulating film 22: semiconductor layer

25 : 오믹접촉층 26 : 보호막25: ohmic contact layer 26: protective film

21 : 제2절연막 31 : 콘택홀21: second insulating film 31: contact hole

본 발명은 박막트랜지스터(이하 TFT라 칭한다)가 내장된 액정표시장치에 관한 것으로서 특히 TFT의 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device in which a thin film transistor (hereinafter referred to as TFT) is incorporated, and more particularly, to a structure and a manufacturing method of a TFT.

상기 종류의 액정표시장치는 예를 들면 제1도 및 제2도에 나타낸 바와 같이 투명기판(11) 및 (12)이 셀(cell)갭을 유지하기 위한 스페이서(spacer)(13)에 의하여 액정이 주입될 수 있는 소정의 간격을 두고 서로 대향하여 설치되어 있다.In this type of liquid crystal display, for example, as shown in FIGS. 1 and 2, the transparent substrates 11 and 12 are separated by a spacer 13 for maintaining a cell gap. It is provided to face each other at predetermined intervals which can be injected.

한쪽의 투명기판(11)의 내면에 화소전극(15)이 복수개 형성되어 있다.A plurality of pixel electrodes 15 are formed on the inner surface of one transparent substrate 11.

상기 각 화소전극(15)에는 스위칭소자로 기능하는 TFT(16)가 형성되어 있다.Each pixel electrode 15 is formed with a TFT 16 serving as a switching element.

상기 TFT의 드레인전극이 화소전극에 접속되는 부분이 된다.The drain electrode of the TFT becomes a portion connected to the pixel electrode.

상기 복수개의 화소전극(15)과 대향해서 다른 한쪽의 투명기판(12)의 내면에 투명한 공통전극(17)이 형성되어 있다.A transparent common electrode 17 is formed on the inner surface of the other transparent substrate 12 facing the plurality of pixel electrodes 15.

상기 화소전극(15)은 장방형으로서 예를 들면 제2도에 도시된 바와 같이 투명기판(11)위에 종횡방향으로 상호 근접하여 격자상으로 배열되어 있다.The pixel electrodes 15 are rectangular, for example, arranged in a lattice shape on the transparent substrate 11 in close proximity to each other in the longitudinal and transverse directions.

상기 화소전극들(15)의 횡방향과 근접하여 각각 게이트버스선(18)이 형성되어 있다.Gate bus lines 18 are formed in close proximity to the lateral directions of the pixel electrodes 15.

또한 상기 화소전극(15)의 종방향과 근접하여 소스버스선(19)이 형성되어 있다.In addition, a source bus line 19 is formed to be close to the longitudinal direction of the pixel electrode 15.

상기 게이트버스선(18) 및 소스버스선(19)의 교차점 부근에 TFT(16)가 설치되어 있다.The TFT 16 is provided near the intersection of the gate bus line 18 and the source bus line 19.

상기 각 교차점 부분에 설치된 TFT의 게이트전극은 게이트버스선(18)에서 분기되며, 소스전극은 소스버스선(19)에서 분기된다.The gate electrodes of the TFTs provided at the intersection points are branched at the gate bus lines 18, and the source electrodes are branched at the source bus lines 19. The gate electrodes of the TFTs shown in FIG.

상기 게이트버스선(18)과 소스버스선(19)을 각 1개씩 선택하여 전압을 인가하면 상기 전압이 인가된 TFT(16)만이 온(ON)되고, 온된 TFT의 드레인전극에 접속된 화소전극(15)에 전하를 축적하여 화소전극(15)과 공통전극(17)과의 사이의 액정(14)부분만 전압이 인가되게 된다.When each of the gate bus line 18 and the source bus line 19 is selected and a voltage is applied, only the TFT 16 to which the voltage is applied is turned ON, and the pixel electrode connected to the drain electrode of the turned on TFT Charges are accumulated in the 15 so that voltage is applied only to the liquid crystal 14 portion between the pixel electrode 15 and the common electrode 17.

상기 전압이 인가된 액정은 액정분자 각도가 변하게 되고, 상기 액정분자의 각도에 따라 빛을 투과하거나 차단한다.The liquid crystal to which the voltage is applied changes the angle of the liquid crystal molecules, and transmits or blocks light depending on the angle of the liquid crystal molecules.

상기와 같은 원리를 이용하여 각 화소전극(15)마다 빛의 투과 및 차단을 선택적으로 컨트롤할 수 있다.By using the same principle as described above, transmission and blocking of light may be selectively controlled for each pixel electrode 15.

상기의 TFT(16)를 포함하는 종래의 투명기판(11)은 예를 들어 제2도 및 제2도의-단면을 나타낸 제3도에 도시한 바와 같이 구성되어 있다.The conventional transparent substrate 11 including the TFT 16 is, for example, shown in FIGS. - It is comprised as shown in FIG. 3 which showed the cross section.

투명기판(11) 위에 횡방향으로 형성되는 게이트버스선(18)과 상기 게이트버스선(18)에서 종방향으로 분기하는 게이트전극(18a)은 Mo,Cr등의 고융점 금속막으로 형성된다.The gate bus line 18 formed laterally on the transparent substrate 11 and the gate electrode 18a branching in the longitudinal direction from the gate bus line 18 are formed of a high melting point metal film such as Mo or Cr.

상기 게이트전극(18a)이 형성된 투명기판(11) 위에 SiNx, SiOx 등의 무기막으로 된 제1절연막(23)이 Plasma Enhanced Chemical Vapor Deposition(이하 PECVD라 칭한다)법으로 형성된다.On the transparent substrate 11 on which the gate electrode 18a is formed, a first insulating film 23 made of an inorganic film such as SiNx, SiOx or the like is formed by a plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD) method.

상기 제1절연막(23)은 통상 게이트절연막이라 부른다.The first insulating film 23 is commonly referred to as a gate insulating film.

상기 게이트전극(18a) 부분의 제1절연막(23) 위에 SiNx등으로 된 제2절연막(21)과 비정질 실리콘(이하a-Si이라 칭한다) 등으로 된 반도체층(22)이 형성된다.A second insulating film 21 made of SiNx or the like and a semiconductor layer 22 made of amorphous silicon (hereinafter referred to as a-Si) or the like are formed on the first insulating film 23 of the gate electrode 18a.

상기 제2절연막(21)은 반도체층과 양질의 계면을 얻을 수 있게 하며 TFT의 문턱전압을 좋게하는 역할을 한다.The second insulating film 21 serves to obtain a good interface with the semiconductor layer and to improve the threshold voltage of the TFT.

상기 a-Si등의 반도체층(22) 위에 SiNx 등으로 된 에치스토퍼층(35)과 오믹접촉층(25)이 형성된다.An etch stopper layer 35 made of SiNx or the like and an ohmic contact layer 25 are formed on the semiconductor layer 22 such as a-Si.

이어서, 종방향으로 형성되는 소스버스선(19)과 상기 소스버스선(19)에서 횡방향으로 분기하는 소스전극(19a)이 형성된다.Subsequently, source bus lines 19 formed in the longitudinal direction and source electrodes 19a branching laterally from the source bus lines 19 are formed.

또한, 상기 소스전극(19a)과 소정의 간격을 두고 드레인전극(19b)이 형성된다.In addition, the drain electrode 19b is formed at a predetermined distance from the source electrode 19a.

상기 소스전극(19a) 및 드레인전극(19b)은 오믹접촉층(25)과 접촉되도록 형성된다.The source electrode 19a and the drain electrode 19b are formed to contact the ohmic contact layer 25.

상기 소스 드레인전극 등을 덮도록 SiNx 등의 무기막으로 된 보호막(26)이 형성되고, 드레인전극부의 콘택홀(31)을 통하여 드레인전극(19b)과 접촉되는 투명도전막인 ITO(Indium Tin Oxide)막이 보호막(26)위에 형성되어 화소전극(15)이 구성된다.A protective film 26 made of an inorganic film such as SiNx is formed to cover the source drain electrode and the like, and an ITO (Indium Tin Oxide) which is a transparent conductive film contacting the drain electrode 19b through the contact hole 31 of the drain electrode part. A film is formed on the protective film 26 to form the pixel electrode 15.

그런데 상기 종래의 액정표시장치에서 TFT의 특성을 지배하는 중요한 요소는 게이트절연막인 제1절연막(23)이다.However, in the conventional liquid crystal display device, an important factor that governs the characteristics of the TFT is the first insulating film 23 which is a gate insulating film.

상기 TFT의 제1절연막은 PECVD법으로 증착되는 SiOx막이 많이 사용된다. 상기 PECVD법의 문제점은 플라즈마 공간에서 SiH4의 분해반응을 증가시켜서 반응성이 높은 화학종을 다량으로 만들어 내기 때문에 기상중합반응에 의한 파티클(particle)이 발생하기 쉽다.As the first insulating film of the TFT, a SiOx film deposited by PECVD is frequently used. The problem of the PECVD method is that particles generated by the gas phase polymerization reaction tend to be generated because a large amount of highly reactive species are generated by increasing the decomposition reaction of SiH 4 in the plasma space.

이러한 파티클은 TFT소자 제조에 있어서 화소전위를 보조하는 보조용량전극부나, 게이트버스선과 소스버스선과의 교차부에 발생하는 핀홀의 원인이 되기 때문에 화상의 점결합이나 선결함을 발생시킨다.Such particles cause point bonding and predecession of the image because they cause the pin-capacitance at the intersection of the sub-capacitance electrode portion and the gate bus line and the source bus line to assist the pixel potential in manufacturing a TFT element.

따라서 상기와 같은 문제점을 해결하기 위한 방안으로 일부 Atmosphreric Pressure Chemical Vapor Deposition(이하 상압 CVD라 칭한다)법을 이용하여 SiOx막을 증착함으로써 핀홀 및 파티클 등의 결함을 해소하고 있다.Accordingly, as a solution to the above problems, defects such as pinholes and particles are eliminated by depositing SiOx films using some Atmosphreric Pressure Chemical Vapor Deposition (hereinafter, referred to as atmospheric pressure CVD).

그러나, 상기 상압 CVD법의 문제점은 400이상의 고온으로 증착하기 때문에 Mo,Cr등과 같은 고융점 금속이 아닌 저융점 금속(알루미늄 계열)을 게이트전극 또는, 게이트버스선으로 사용할 경우에 열스트레스에 의한 힐락(hillock)이 발생하여 게이트버스선과 소스버스선 간의 단락 또는, 화소전위를 보조하는 보조용량전극부의 단락을 일으켜 생산성을 떨어뜨린다.However, the problem of the atmospheric CVD method is 400 Because of the high temperature deposition, when a low melting point metal (aluminum series) is used as a gate electrode or a gate bus line instead of a high melting point metal such as Mo or Cr, hillock occurs due to thermal stress, resulting in a gate bus line and a source. The short circuit between the bus lines or the storage capacitor electrode portion assisting the pixel potential causes a decrease in productivity.

본 발명은 상기와 같은 힐락 등의 문제점을 해결하기 위하여 가스유량비 SiH4: O2가 1 : 1020 이고 기판의 온도가 350이하의 조건에서 SiOx로 된 제1절연막을 투명기판(11)에 증착하여 형성하는 것을 특징으로 한다.In order to solve the problems of Hillock and the like, the present invention provides a gas flow rate ratio of SiH 4 : O 2 1: 10. 20 and substrate temperature is 350 A first insulating film made of SiOx is deposited on the transparent substrate 11 under the following conditions.

이하 본 발명에 따른 액정표시장치의 제조방법의 실시예를 제4도의 공정 단면도에 의하여 상세히 설명한다.Hereinafter, an embodiment of a method of manufacturing a liquid crystal display device according to the present invention will be described in detail with reference to the process cross section of FIG.

[실시예]EXAMPLE

투명기판(11) 위에 금속막 예를 들어 알루미늄막을 증착한 후 패터닝하여 게이트버스선(18)과 상기 게이트버스선에서 분기한 게이트전극(18a)을 형성한다(제4a도).A metal film, for example, an aluminum film is deposited on the transparent substrate 11 and then patterned to form a gate bus line 18 and a gate electrode 18a branched from the gate bus line (FIG. 4A).

상기 게이트버스선(18)은 단면도에 나타나지 않는다.The gate bus line 18 is not shown in the cross sectional view.

상기 제4a도 후에 절연성을 높이고 힐락을 방지하기 위하여 양극산화막을 형성할 수도 있으나 본 실시예에서는 설명을 생략한다.An anode oxide film may be formed to increase insulation and prevent hillock after FIG. 4A, but the description thereof will be omitted.

상기 공정 후에 게이트절연막인 제1절연막이 되는 SiOx막을 기판 위에 증착한다(제4b도).After the above step, a SiOx film serving as a first insulating film as a gate insulating film is deposited on the substrate (FIG. 4B).

상기 제1절연막(23)의 증착은 상압 CVD법에서 원료가스로 SiH4와 O2를 사용하고 희석가스로는 N2를 사용하여 실시한다.Deposition of the first insulating film 23 is performed by using SiH 4 and O 2 as source gas and N 2 as dilution gas in atmospheric pressure CVD.

기판 온도는 350이하로 하고 가스유량비는 일정비율로 조절한다.Substrate temperature is 350 The gas flow rate is adjusted to be a ratio below.

본 실시예에서는 예를 들어 가스유량비 SiH4: O2가 1 : 1020 으로 하였다.In this embodiment, for example, the gas flow rate ratio SiH 4 : O 2 is 1: 10. It was set to 20.

이어서 제2절연막이 되는 SiNx층과 반도체층이 되는 a-Si층과 에치스토퍼층이 되는 SiNx층을 PECVD법을 이용하여 연속 증착한 후 패터닝하여 제2절연막(21)과 반도체층(22)과 에치스토퍼층(35)을 형성한다(제4c도).Subsequently, the SiNx layer serving as the second insulating film, the a-Si layer serving as the semiconductor layer, and the SiNx layer serving as the etch stopper layer are successively deposited by PECVD and then patterned to form the second insulating film 21 and the semiconductor layer 22. An etch stopper layer 35 is formed (FIG. 4C).

상기 제2절연막(21)과 에치스토퍼층(35)은 경우에 따라 생략할 수 있다.The second insulating layer 21 and the etch stopper layer 35 may be omitted in some cases.

그러나 상기 제2절연막을 생략하고 SiO2층과 a-Si층을 직접 적합한 경우 TFT의 문턱전압이 높아지고 전계효과 이동도의 값도 작아서 주변구동회로와의 정합이 어렵기 때문에 이것을 방지하기 위하여 상기 제2절연막을 형성한 것이다.However, when the second insulating film is omitted and the SiO 2 layer and the a-Si layer are directly applied, the threshold voltage of the TFT is high and the value of the field effect mobility is small, so that it is difficult to match the peripheral driving circuit. 2 An insulating film is formed.

또한 에치스토퍼층(35)은 저온 상압 CVD법을 이용하여 SiOx 또는 SiOx와 SiNx를 연속증착하여 형성할 수도 있다.In addition, the etch stopper layer 35 may be formed by continuously depositing SiOx or SiOx and SiNx using a low temperature atmospheric pressure CVD method.

이어서 n+a-Si층이 되도록 반도체층에 이온을 도핑하여 증착한 후 페터닝하여 오믹접촉층(25)을 형성한다(제4d도).Subsequently, the semiconductor layer is doped with ions so as to be an n + a-Si layer and deposited, and then patterned to form an ohmic contact layer 25 (FIG. 4D).

이어서 금속막 예를 들어 알루미늄, 크롬막 등을 증착한 후 패터닝하여 신호선으로 기능하는 소스버스선(19), 상기 소스버스선(19)에서 분기한 소스전극(19a) 및 드레인전극(19b)을 형성한다(제4e도).Subsequently, a metal film, for example, an aluminum or chromium film is deposited, and then patterned to form a source bus line 19 functioning as a signal line, a source electrode 19a and a drain electrode 19b branched from the source bus line 19. (Fig. 4e).

상기 소스버스선(19)은 공정 단면도에 나타나지 않는다.The source bus line 19 is not shown in the process sectional view.

이어서 무기절연막 또는 유기절연막으로 된 보호막(26)을 기판 위에 증착하고 드레인전극(19a)과 화소전극(15)을 연결하는 콘택홀(31)을 형성한다(제4f도).Subsequently, a protective film 26 made of an inorganic insulating film or an organic insulating film is deposited on the substrate, and a contact hole 31 connecting the drain electrode 19a and the pixel electrode 15 is formed (FIG. 4f).

이어서 ITO막을 상기 보호막 위에 스퍼터링법으로 증착하고, 상기 ITO막을 패터닝하여 화소전극(15)을 형성한다(제4g도).Subsequently, an ITO film is deposited on the protective film by sputtering, and the ITO film is patterned to form a pixel electrode 15 (FIG. 4G).

상기 실시예에 의한 제조방법은 특히 상압 CVD 장치로 기판온도가 350이하이고 가스유량비가 SiH4: O2는 1 : 1020 인 조건에서 TFT의 저융점 금속으로 된 게이트전극 위에 제1절연막(23)을 형성하는 것이 종래 제조방법과 구별되는 가장 큰 특징적인 점이다.In the manufacturing method according to the above embodiment, the substrate temperature is 350 in an atmospheric pressure CVD apparatus. Gas flow ratio is less than SiH 4 : O 2 is 1: 10 The formation of the first insulating film 23 on the gate electrode made of the low melting point metal of the TFT under the condition of 20 is the most characteristic point distinguished from the conventional manufacturing method.

상기에 대한 효과는 제1절연막을 종래 제조방법과 같이 400이상의 고온으로 증착하지 않고 350이하의 낮은 온도로 증착하기 때문에 저융점 금속을 게이트전극등으로 사용하더라도 금속막의 스트레스로 인한 힐락이 발생할 염려가 없다.The effect on the above is that the first insulating film is 400 as in the conventional manufacturing method. 350 without deposition at high temperatures Since the deposition is performed at the following low temperature, even if the low melting point metal is used as the gate electrode or the like, there is no fear of the hillock due to the stress of the metal film.

따라서, 일반적으로 저항이 큰 고융점 물질 보다는 저항이 작은 저융점 물질을 사용할 수 있기 때문에 전도도를 향상시킬 수 있다.Therefore, in general, the conductivity can be improved because a low melting point material having a lower resistance than a high melting point material having a high resistance can be used.

또한, 350이하의 낮은 온도에서 보호막(26)을 증착할 수 있기 때문에 고온으로 인한 TFT의 파괴 및 기능 불량을 방지할 수 있다.In addition, 350 Since the protective film 26 can be deposited at the following low temperature, it is possible to prevent destruction of TFTs and malfunctions due to high temperatures.

Claims (7)

기판, 게이트전극, 절연막, 반도체층, 소스전극과 드레인전극을 포함하는 액정표시장치의 제조 방법에 있어서; 상기 절연막은 가스유량비 SiH4: O2가 1 : 1020이고, 상기 기판의 온도가 350이하의 조건에서 증착되는 것을 특징으로 하는 액정표시장치의 제조방법.A method of manufacturing a liquid crystal display device comprising a substrate, a gate electrode, an insulating film, a semiconductor layer, a source electrode and a drain electrode; The insulating film has a gas flow rate ratio of SiH 4 : O 2 equal to 1: 10. 20, the temperature of the substrate is 350 A method for manufacturing a liquid crystal display device, which is deposited under the following conditions. 제1항에 있어서; 상기 절연막은 상압 CVD에 의하여 형성되는 것을 특징으로 하는 액정표시장치의 제조방법.The method of claim 1; The insulating film is a method of manufacturing a liquid crystal display device, characterized in that formed by atmospheric pressure CVD. 제1항에 있어서; 상기 절연막은 게이트절연막이 되는 제1절연막을 포함하는 것을 특징으로 하는 액정표시장치의 제조방법.The method of claim 1; And the insulating film includes a first insulating film serving as a gate insulating film. 제3항에 있어서; 상기 제1절연막은 SiOx인 것을 특징으로 하는 액정표시장치의 제조방법.The method of claim 3; And the first insulating layer is SiOx. 기판과; 상기 기판 위에 형성된 게이트전극과; 상기 게이트전극이 형성된 기판 위에 상압 CVD에 의하여 가스유량비 SiH4: O2가 1 : 1020 이고, 상기 기판의 온도가 350이하의 조건에서 형성된 제1절연막과; 상기 게이트전극부의 제1절연막 위에 섬 모양으로 형성된 반도체층과; 상기 반도체층 위에 양쪽으로 분리되어 형성된 오믹접촉층과; 상기 양쪽의 오믹접촉층 위에 형성된 소스전극 및 드레인전극과; 상기 소스 드레인전극이 형성된 기판을 덮도록 형성된 보호막과; 상기 보호막을 통하여 상기 드레인전극과 접촉되고, 상기 보호막 위에 형성된 화소전극을 포함하는 것을 특징으로 하는 액정표시장치.A substrate; A gate electrode formed on the substrate; Gas flow ratio SiH 4 : O 2 is 1: 10 by atmospheric pressure CVD on the substrate on which the gate electrode is formed. 20, and the temperature of the substrate is 350 A first insulating film formed under the following conditions; A semiconductor layer formed in an island shape on the first insulating film of the gate electrode part; An ohmic contact layer formed separately on both sides of the semiconductor layer; Source and drain electrodes formed on both ohmic contact layers; A protective film formed to cover the substrate on which the source drain electrode is formed; And a pixel electrode in contact with the drain electrode through the passivation layer and formed on the passivation layer. 제5항에 있어서; 상기 제1절연막은 SiOx인 것을 특징으로 하는 액정표시장치.The method of claim 5; And the first insulating layer is SiOx. 제6항에 있어서; 상기 제1절연막과 상기 섬모양으로 형성된 반도체층 사이에 SiNx로 된 제2절연막이 형성되는 것을 특징으로 하는 액정표시장치.The method of claim 6; And a second insulating film made of SiNx is formed between the first insulating film and the semiconductor layer formed in the island shape.
KR1019960013975A 1996-04-30 1996-04-30 Structure and fabrication method of liquid crystal display device KR100202232B1 (en)

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