JP2894966B2 - Asymmetric MOS semiconductor device, method of manufacturing the same, and electrostatic discharge protection circuit including the semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method of manufacturing the same, and an electrostatic discharge protection circuit including the semiconductor device.

[0002]

2. Description of the Related Art As the number of pins of a VLSI has been increased with the miniaturization and higher functionality of constituent elements of a large-scale integrated circuit (VLSI), an electrostatic discharge protection (ESD) transistor has a higher voltage.
The area ratio in the LSI chip has been increasing. In order to reduce the area ratio, higher performance of the ESD protection transistor is required. Further, in order to reduce the manufacturing cost, it is necessary to suppress an increase in the number of manufacturing steps as much as possible.

[0003] From such a demand, a MOS semiconductor device having an offset single drain structure has been proposed as an ESD protection transistor.

FIG. 7 shows a MOS type semiconductor device having an offset single drain structure. In FIG.
0 is a P-type semiconductor substrate, 701 is a gate oxide film, 702 is a gate electrode, 703 is a gate side wall, and 704 is an N-type high concentration diffusion layer.

A characteristic of this semiconductor device is that
There are the following two points.

1) No LDD (Lightly doped drain) structure is adopted. The LDD structure refers to a structure in which an impurity diffusion region having a lower impurity concentration than a normal drain region is provided between a drain region and a channel region. The LDD structure is simultaneously formed not only on the drain region side but also on the source region side. On the other hand, a structure in which an impurity diffusion region having an impurity concentration lower than that of a normal drain region is not provided between a drain region and a channel region is called a single drain structure, as distinguished from an LDD structure. The MOS type semiconductor device of FIG. 7 has a single drain structure. Therefore, the electric field strength of the current path where the amount of current is maximum and the electric field strength at the PN junction are L
Relaxed as compared with those having a DD structure. as a result,
The ESD breakdown voltage per unit gate width increases.

2) Since the drain region is offset rightward in the drawing from the region immediately below the gate electrode, a high concentration diffusion layer (normal drain region) enters the end immediately below the normal gate electrode. GIDL (Gate Induced)
Drain Leakage) The current decreases. The structure shown in FIG. 7 may be called an “offset single drain structure”.

[0008] LS actually manufactured and manufactured using a CMOS process of 0.5 μm and 0.8 μm rules
However, in the I chip, as the ESD protection transistor, a MOS semiconductor device having an LDD structure is employed similarly to the transistor in the logic circuit portion.

FIG. 8 shows a conventional MOS type semiconductor device having an LDD structure (see Japanese Patent Application Laid-Open No. 54-4482).
In the figure, 800 is a P-type semiconductor substrate, 801 is a gate oxide film, 802 is a gate electrode, 803 is a gate side wall, 8
04 is an N-type low concentration diffusion layer, and 805 is an N-type high concentration diffusion layer.

The ESD breakdown voltage per unit gate width of the MOS type semiconductor device having the LDD structure is smaller than that of the MOS type semiconductor device having the offset single drain structure.
About half. In order to obtain sufficient ESD breakdown voltage,
Usually, the gate width is set sufficiently large.

[0011]

The conventional transistor structure has the following problems.

In the case of the offset single drain structure, there is a problem in that when it also serves as an I / O (input / output) circuit, the parasitic resistance of the offset portion becomes very large, and the driving force is reduced. In the case of the LDD structure, there is a problem that the ESD breakdown voltage is small.

Further, the conventional structures of the ESD protection circuit and the I / O circuit have a problem that speed and power consumption are increased due to a large parasitic effect, and a layout area is large and a chip area is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a MOS semiconductor device having a high ESD breakdown voltage, a small GIDL current, and a large driving force, and a MOS device therefor. An object of the present invention is to provide a manufacturing method and an electrostatic discharge protection circuit.

[0015]

According to the present invention, there is provided an asymmetric MOS semiconductor device comprising: a first conductivity type semiconductor layer having an upper surface; a gate insulating film provided on the upper surface of the semiconductor layer; A second conductivity type source region and a second conductivity type provided in a second region of the upper surface of the semiconductor layer, which is offset to the outside of the first region located immediately below the gate electrode. MO with drain region
An S-type semiconductor device, wherein an electric resistance of a portion of the upper surface of the semiconductor layer between the first region and the source region is higher than an electric resistance between the first region and the drain region. Small, thereby achieving the above objectives.

In a preferred embodiment, a second conductivity type impurity diffusion layer is provided on a portion of the upper surface of the semiconductor base layer between the first region and the source region.

In a preferred embodiment, the second conductivity type impurity diffusion layer has an impurity concentration lower than that of the source region.

In a preferred embodiment, the second conductivity type impurity diffusion layer has a thickness smaller than a maximum thickness of the source region.

In a preferred embodiment, the second conductivity type impurity diffusion layer extends from the source region to the inside of the first region. The semiconductor layer may be formed from a single crystal silicon substrate, or may be formed on an insulating substrate.

In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

Another asymmetric MOS type semiconductor device according to the present invention has a top surface, a semiconductor substrate including a first conductivity type region and a second conductivity type region in contact with the top surface, and the second conductivity type of the semiconductor substrate. A MOS type semiconductor device comprising: a first conductivity type MOS transistor provided in a region; and a second conductivity type MOS transistor provided in the first conductivity type region of the semiconductor substrate, wherein the second conductivity type MOS transistor is provided in the semiconductor substrate. Type MOS transistor
A gate insulating film provided on the first conductive type region, a gate electrode provided on the gate insulating film, and a first electrode located on the upper surface of the first conductive type region and located immediately below the gate electrode;
A second region provided in a second region offset outside the region.
A source region of a conductivity type and a drain region of a second conductivity type, and the electrical resistance of a portion between the third region and the source region on the upper surface of the first conductivity type region is the same as that of the third region. The first conductivity type MOS transistor is smaller than the electric resistance between the drain region and the first conductivity type MOS transistor. The first conductivity type MOS transistor includes a gate insulating film provided on the second conductivity type region, and a gate electrode provided on the gate insulating film. A first-conductivity-type source region and a first-conductivity-type drain region provided in a fourth region offset from the third region located immediately below the gate electrode on the upper surface of the second-conductivity-type region; Wherein the electrical resistance of a portion of the upper surface of the second conductivity type region between the third region and the source region is equal to the electrical resistance between the third region and the drain region. Thereby, the above object is achieved.

In a preferred embodiment, a second conductivity type impurity diffusion layer is provided in a portion of the semiconductor substrate between the first region and the source region.

In a preferred embodiment, the second conductivity type impurity diffusion layer has an impurity concentration lower than that of the source region. In a preferred embodiment, the second
The conductivity type impurity diffusion layer has a thickness smaller than the maximum thickness of the source region.

In a preferred embodiment, the second conductivity type impurity diffusion layer extends from the source region to the inside of the first region.

In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

The manufacturing method according to the present invention comprises a first conductive type semiconductor layer having an upper surface, a gate insulating film provided on the upper surface of the semiconductor layer, a gate electrode provided on the gate insulating film, An asymmetrical MOS having a second conductivity type source region and a second conductivity type drain region provided in a second region offset to the outside of the first region located immediately below the gate electrode on the upper surface of the semiconductor layer; Forming a gate insulating film on the semiconductor layer, forming the gate electrode on the gate insulating film, and forming the drain region in the semiconductor layer. Covering the portion with an implantation stop layer, implanting second conductivity type impurity ions into the semiconductor layer using the implantation stop layer and the gate electrode as a mask, removing the implantation stop layer, Game A step of providing a sidewall spacer on both sides of the electrode, the gate electrode and the sidewall spacer as a mask, the second conductivity type impurity ions are implanted into the semiconductor layer, a second conductive type source region and a second
Forming a conductivity type drain region, whereby the above object is achieved.

According to another manufacturing method of the present invention, there is provided a semiconductor substrate having an upper surface and including a first conductivity type region and a second conductivity type region in contact with the upper surface, and providing the semiconductor substrate in the second conductivity type region of the semiconductor substrate. A method of manufacturing an asymmetric MOS type semiconductor device comprising: a first conductivity type MOS transistor provided in the first conductivity type region; and a second conductivity type MOS transistor provided in the first conductivity type region of the semiconductor substrate. Forming a gate insulating film on the substrate, forming a gate electrode on the gate insulating film, forming a portion of the semiconductor substrate to be a drain region of the second conductivity type MOS transistor, Covering both of the regions with a first implantation stop layer; implanting second conductivity type impurity ions into the first conductivity type region using the first implantation stop layer and the gate electrode as a mask;
Removing the first implantation stop layer, covering the first conductivity type region with a second implantation stop layer, removing the first conductivity type impurity ions using the second implantation stop layer and the gate electrode as a mask. Implanting into the second conductivity type region, removing the second implantation stop layer, providing a sidewall spacer on a side surface of the gate electrode,
Covering the conductive type region with a third injection stop layer;
Using the implantation stop layer and the gate electrode as a mask, the second
Implanting impurity ions of the conductivity type into the first conductivity type region, thereby forming a source region and a drain region of the second conductivity type MOS transistor; removing the third implantation stop layer; Covering the one conductivity type region with a fourth implantation stop layer, and implanting first conductivity type impurity ions into the second conductivity type region using the fourth implantation stop layer and the gate electrode as a mask; 1 conductivity type M
Forming a source region and a drain region of the OS transistor, thereby achieving the above object.

As the fourth injection stop layer, the second injection stop layer
A layer having the same planar shape as the injection stop layer is used.

As the third injection stop layer, the second injection stop layer
A layer having a planar shape obtained by inverting the planar shape of the injection stop layer is used.

The electrostatic discharge protection circuit of the present invention has an input / output pad for inputting / outputting an electric signal, a terminal for supplying a predetermined potential, a drain connected to the input / output pad, A first Nc whose gate is connected to the terminal
a second Nc having a drain connected to the input / output pad and a source and a gate connected to the terminal.
and a hMOSFET, wherein each of the first and second NchMOSFETs includes a P-type semiconductor layer having an upper surface, a gate insulating film provided on the upper surface of the semiconductor layer, A gate electrode provided on the gate insulating film, an N-type source region provided in a second region of the upper surface of the semiconductor layer, which is offset outside a first region located immediately below the gate electrode, and An N-type drain region.
In regard to the above, an N-type impurity diffusion layer is provided in a portion of the upper surface of the semiconductor base layer between the first region and the source region, whereby the second NchMOSFE is formed.
With respect to T, the electrical resistance of a portion of the upper surface of the semiconductor layer between the first region and the source region is smaller than the electrical resistance between the first region and the drain region, The above object is achieved.

As for the first N-channel MOSFET, an N-type impurity diffusion layer is provided in a portion of the upper surface of the semiconductor base layer between the first region and the source region. First NchMOSFE
Regarding T, an electric resistance of a portion of the upper surface of the semiconductor layer between the first region and the source region may be smaller than an electric resistance between the first region and the drain region.

With respect to the first NchMOSFET, both the portion between the first region and the source region and the portion between the first region and the drain region on the upper surface of the semiconductor base layer are provided. An N-type impurity diffusion layer is provided, whereby the first NchMOSFE is formed.
Regarding T, even if the electric resistance of a portion between the first region and the source region on the upper surface of the semiconductor layer is set equal to the electric resistance between the first region and the drain region. Good.

According to another aspect of the present invention, there is provided a first electrostatic breakdown protection circuit having a power supply terminal for supplying a power supply voltage, a drain connected to the input / output pad, and a source and a gate connected to the power supply terminal. A Pch MOSFET, and a second Pch MOSFET having a drain connected to the input / output pad and a source and a gate connected to the power supply terminal, each of the first and second Pch MOSFETs having an upper surface. An N-type semiconductor layer, a gate insulating film provided on the upper surface of the semiconductor layer, a gate electrode provided on the gate insulating film, and a portion of the upper surface of the semiconductor layer located immediately below the gate electrode. A P-type source region and a P-type drain region provided in a fourth region offset to the outside of the third region, wherein the first region and the source in the upper surface of the semiconductor layer are provided. Electrical resistance of the portion between the frequency is equal to the electrical resistance between the first region and said drain region,
This achieves the sanity purpose.

The second Nch MOSFET and the second
May be connected to an output control circuit to output an output signal on the input / output pad.

[0035]

According to the MOS type semiconductor device of the present invention: 1) Since the drain side has a single drain structure,
The electric field strength of the current path where the amount of current is maximum and the electric field strength at the PN junction between the diffusion layer and the substrate are alleviated as compared with the LDD structure. For this reason, the ESD breakdown voltage increases.

2) Since a single-drain structure offset to the drain side is employed, the GIDL current is smaller than that in a case where a high concentration diffusion layer enters a normal gate end.

3) Since the LDD structure is adopted on the source side, the driving force is improved as compared with the conventional symmetric MOSFET having a single drain structure in which the source side is also offset.

In a CMOS semiconductor device, an NchMO
Using an asymmetric transistor for SFET, PchM
By using a transistor having an LDD structure as the OSFET, the number of masks for manufacturing can be reduced by one without changing the ESD breakdown voltage.

In the method of manufacturing a MOS type semiconductor device according to the present invention, the LDD injection mask used in common with the conventional S / D (source / drain) formation mask is separated. By making the pattern such that LDD implantation is not performed, the number of steps is not increased, and a special process is not used.
With the same number of masks as in the case where the SD protection transistor has an offset single drain structure, the I / O circuit and the ESD
An asymmetric MOSFET having a single drain structure with an offset on the drain side and an LDD structure on the source side, which is very suitable for a MOSFET that also serves as both a protection transistor, can be manufactured.

Further, in the pch MOSFET, S / D
The number of masks can be reduced by one by using the (source / drain) formation mask and the LDD implantation mask in common.

Further, not only an asymmetric MOSFET but also a symmetric MOSFET used in a normal logic circuit can be easily formed.

In the electrostatic discharge protection circuit according to the present invention, 1) the driving force of the I / O circuit is slightly reduced as compared with the case where both the ESD protection circuit and the I / O circuit have the LDD structure. The area of the / O circuit is slightly increased. However, since the ESD withstand voltage increases, the area of the ESD protection circuit can be reduced, so that the layout area can be reduced as a whole. In addition, since the driving force of the I / O circuit is increased as compared with the case where both have the offset single drain structure, the gate width of the transistor of the I / O circuit can be reduced. The area can be reduced.

2) The gate length of the ESD protection circuit transistor is longer than the gate lengths of the other transistors. Therefore, it is easy to form a pattern crossing the gate, which has conventionally been a problem when manufacturing an asymmetric MOSFET.

3) Since the gate width can be greatly reduced by the effect of 1), the parasitic effect due to the junction capacitance as the load capacitance at the time of input and the gate electrode at the time of output can be greatly reduced, and the I / O circuit can be reduced. , The delay time when driving is improved.

Further, in a CMOS structure, I / O
NchMO that doubles as circuit and ESD protection transistor
An asymmetric transistor is used for SFET, PchMOS
By using an LDD transistor for the FET, E
It is possible to reduce the number of masks required to realize this apparatus by one while maintaining the SD breakdown voltage at the same level.

[0046]

The present invention will be described below with reference to examples.

(Embodiment 1) The MOS transistor of this embodiment has a gate insulating film 101 provided on the upper surface of a P-type single crystal silicon substrate 100 and a gate electrode 102 provided on the gate insulating film 101. A sidewall spacer 103 provided on a side surface of the gate electrode 102, and an N-type source region 105a formed in the silicon substrate 100.
And an N-type drain region 105b.

In the present specification, for convenience of explanation, the upper surface of the silicon substrate 100 is divided into three regions: (1) the gate electrode 10
A first area located directly below 2;
A second region offset by about 0.10 μm from
(3) An intermediate area between the first area and the second area will be considered separately. Gate insulating film 101 and gate electrode 1
02 is located directly above the first area. Source area 1
05a and the drain region 105b are both provided in the second region. The side wall spacer 103
It is provided on an intermediate area between the first area and the second area.

The first region and the source region 105a of this embodiment
Between them, an N-type impurity diffusion region 104 is provided. More precisely, the impurity diffusion layer 104 extends from the source region 105a to the inside of the first region. This impurity diffusion region 104 has an impurity concentration (2 × 1) lower than that of the source region 105a (2 × 10 ²⁰ cm ⁻³ ).
0 ¹⁷ cm ⁻³ ) and a thickness (0.14 μm) thinner than the maximum thickness (0.20 μm) of the source region 105a.
have. Due to the presence of the impurity diffusion region 104, the electric resistance of the intermediate region between the first region and the source region is smaller than the electric resistance of the intermediate region between the first region and the drain region.

FIG. 1 shows a MOSFET formed on a single-crystal silicon substrate 100. Instead of the single-crystal silicon substrate 100, a single-crystal semiconductor layer and a polycrystalline semiconductor layer provided on an insulating substrate are provided. Alternatively, an amorphous semiconductor layer may be used.

Next, a method of manufacturing the asymmetric MOS type semiconductor device of FIG. 1 will be described with reference to FIG.

First, as shown in FIG. 3A, an oxide film (about 10 nm in thickness) and a conductive film (about 200 nm in thickness) are continuously formed on a P-type semiconductor substrate 300. Predetermined portions of the multilayer film composed of an oxide film and a conductive film are selectively etched, whereby the gate insulating film 3 is formed.
01 and the gate electrode 302 are formed. Etching is
This is performed by dry etching having strong anisotropy in a direction perpendicular to the substrate 300. In FIG. 3A, the gate electrode 302
Although the region other than the region immediately below (the first region) is described such that the upper surface of the substrate is exposed, an oxide film for the gate insulating film may be left.

Next, as shown in FIG. 3B, a photoresist 306 is applied, and the photoresist 306 is patterned so as to cover the drain side of the P-type semiconductor substrate 300 and the drain side of the gate electrode 302. .

As shown in FIG. 3C, using the gate electrode 302 and the photoresist 306 as a mask, an n-type impurity, for example, phosphorus ions is implanted at an energy of 40K.
Ion implantation is performed at an angle of 7 degrees with an implantation dose of 4 × 10 ¹³ cm ^{−2 at} eV to form an N-type low concentration diffusion layer 304.

As shown in FIG. 3D, after removing the photoresist 306, an insulating film (for example, an oxide film) serving as the gate side wall 303 is deposited to a thickness of about 150 nm. afterwards,
The insulating film is etched by dry etching having strong anisotropy in the vertical direction, so that a predetermined portion of the insulating film is left on the side surface of the gate electrode 302 and the gate sidewall 4 is removed.
To form

As shown in FIG. 3E, an N-type impurity such as arsenic ion is implanted at an energy of 80 KeV.
Ion implantation is performed at an implantation dose of about 6 × 10 ¹⁵ cm ⁻² to form an N-type high concentration diffusion layer 305.

When a plurality of MOSFETs including a MOSFET having the conventional LDD structure are simultaneously formed on the same substrate, LDD implantation should not be performed on the drain side of only some transistors having the structure shown in FIG. I just need. Then, an asymmetric MOSFET having an offset single-drain structure on the drain side and an LDD structure on the source side can be easily formed without particularly increasing the number of manufacturing steps and without using a special process. be able to. In particular, when manufacturing a semiconductor device in which a plurality of transistors are integrated on a single substrate, the asymmetric masking shown in FIG. A MOSFET can be manufactured.

NchMOS manufactured by the method of FIG.
NchMO with FET (invention) and conventional symmetric structure
For SFETs (conventional examples 1 and 2), the driving force was calculated using process / device simulations and compared.

Conventional example 1: Both source and drain are LD
D-structure Conventional example 2: Single-drain structure with offset for both source and drain Present invention 1: Single-drain structure with LDD for source and offset for drain The graph of FIG. 9 shows the saturation current of the NchMOSFET obtained by device simulation. The horizontal axis of the graph is the drain voltage, and the vertical axis is the drain current. The gate voltage is 3 V, the gate length is 0.5 μm, and the gate oxide film 10 n
The process simulation is performed under the condition of m.

As can be seen from FIG. 9, when the gate voltage and the drain voltage are 3 V, the saturation current I per unit gate width is obtained.
dsat is Idsat (conventional example 1) = 0.329 mA /
μm Idsat (conventional example 2) = 0.168 mA /
μm Idsat (Invention 1) = 0.259 mA /
μm, and the present invention has a driving force of about 21% as compared with the conventional example 1.
Although it decreases, it increases by 54% as compared with Conventional Example 2.

FIG. 10 shows the ESD breakdown voltage (experimental value) of the NchMOSFET obtained by the 200 pF surge test.
Of FIG. ESD breakdown voltage is MOSF
Since it is determined only by the structure on the drain side of the ET, the ESD withstand voltage of the present invention 1 and the ESD withstand voltage of the conventional example 2 (offset single drain structure) are the same. FIG. 10 shows that the ESD breakdown withstand voltage is proportional to the gate width, and the ESD breakdown withstand voltage of the present invention 1 and the conventional example 2 is twice or more that of the conventional example.

E per unit gate width obtained from FIG.
The SD breakdown voltage is as follows: ESD breakdown voltage (conventional example 1) = 0.53 V / μm ESD breakdown voltage (conventional example 2) = 1.14 V / μm ESD breakdown voltage (present invention 1) = 1.14 V / μm In the example, an ESD breakdown voltage almost equal to that of the conventional example 2 can be secured.
SD breakdown voltage increases.

In summary, according to the present embodiment, the driving force is reduced by about 21% as compared with the conventional example 1,
The D breakdown voltage increases about twice or more. Further, as compared with the conventional example 2, the ESD withstand voltage is the same, but the driving force is about 5 times.
Increase by 4%. The semiconductor device of the present invention is most suitable for an ESD protection transistor also serving as an I / O circuit. This will be described later in detail with reference to FIGS.

Embodiment 2 Another MOS type semiconductor device (complementary MOS semiconductor device) according to the present invention will be described with reference to FIG.

The complementary MOS type semiconductor device shown in FIG. 2 includes a P-type semiconductor substrate 200, an N-type well 201 provided on the P-type semiconductor substrate 200, a LOCOS 202, a P-type semiconductor substrate 200 for separating the P-type semiconductor substrate 200 and the N-type well 201. Type semiconductor substrate 2
00 and the gate oxide film 20 on one main surface of the N-type well 201.
3, a gate electrode 204 provided on the P-type semiconductor substrate 200, an N-type source low concentration diffusion layer 206 formed on the P-type semiconductor substrate 200,
N-type source / drain high concentration diffusion layer 208, N-type well 2
The P-type low-concentration diffusion layer 207, the P-type source / drain high-concentration diffusion layer 209, and the gate side wall 205 formed on the side wall of the gate electrode 204 are provided.

A characteristic of the embodiment shown in FIG.
While the chMOSFET has an asymmetric structure, P
The chMOSFET has a symmetric LDD structure. According to this embodiment, the asymmetric MOSF
As compared with the case where ET is employed, the driving force can be improved without reducing the ESD breakdown withstand voltage while reducing the number of masks required for the manufacturing process by one.

The reason why the ESD breakdown voltage does not decrease even if the Pch MOSFET has a symmetric LDD structure is as follows.

The channel resistance of the Pch MOSFET is Nc
ESD resistance is higher than channel resistance of hMOSFET.
The current during operation is higher than PchMO
It is difficult to flow through the SFET. For this purpose, PchMOSFE
Even if the ESD breakdown withstand voltage of T is lower than that of the NchMOSFET, the PchMOSFET hardly causes ESD breakdown,
The ESD breakdown voltage is determined by the NchMOSFET.

With reference to FIGS. 4A to 4E, a method of manufacturing the CMOS type semiconductor device shown in FIG. 2 will be described.

First, as shown in FIG. 4A, a gate oxide film 403 is formed to a thickness of about 10 nm on one main surface of a P-type semiconductor substrate 400 and an n-type well 401 to form a gate electrode 404. A conductive film is deposited to a thickness of about 200 nm, and a predetermined position of the multilayer film composed of the conductive film to be the gate oxide film 403 and the gate electrode 404 is selectively selectively vertically and strongly anisotropically dry-etched by a gate oxide film. 403
Etching is performed until the gate electrode 404 is formed.

As shown in FIG. 4B, a photoresist 410b is applied to cover the drain side of the P-type semiconductor substrate 400, the drain side of the gate electrode 404 on the P-type semiconductor substrate 400, and the N-type well 401. In this state, the photoresist 410b is selectively patterned. Further, using the gate electrode 404 and the photoresist 410b as a mask, n-type impurities, for example, phosphorus ions are implanted at an implantation energy of 40 KeV and an implantation dose of about 4E13 cm−2.
N-type source low concentration diffusion layer 406 by ion implantation at an angle of degrees
To form

As shown in FIG. 4C, after removing the photoresist 410b, a photoresist 410c is applied, and the photoresist 410c is patterned so as to cover the P-type semiconductor substrate 400. Further, using the gate electrode 404 and the photoresist 410c as a mask, a P-type impurity, for example, BF ₂ ion is implanted with an implantation energy 40.
Ion implantation is performed at an angle of 7 degrees with an implantation dose of about 4 × 10 ¹³ cm ^{−2 at} KeV to form a P-type low concentration diffusion layer 407.

As shown in FIG. 4D, after removing the photoresist 410c, an insulating film, for example, an oxide film to be the gate side wall 405 is deposited to a thickness of about 150 nm, and selectively strongly anisotropic dry etching in the vertical direction. Gate side wall 4
05 is left on the side surface of the gate electrode 404. Next, a photoresist 410d is applied, and the photoresist 410d is selectively patterned so as to cover the N-type well 401. Further, the gate electrode 404 and the photoresist 4
Using 10d as a mask, an N-type impurity, for example, arsenic ion is implanted at an energy of 80 KeV and an implanted dose of 6E15.
Ion implantation is performed at an angle of about 7 cm at about 7 degrees to form an N-type high concentration diffusion layer 408.

In the step (e), the photoresist 41
Od is removed, a photoresist 410e is applied, and the photoresist 410e is covered with the P-type semiconductor substrate 400.
e is selectively patterned. Further, the gate electrode 40
4 and a photoresist 410e as a mask, and implant P-type impurities, for example, BF ₂ ions at an implantation energy of 80 Ke.
V ions are implanted at an implantation dose of about 6 × 10 ¹⁵ cm ⁻² at an angle of 7 ° to form a P-type high concentration diffusion layer 409.

According to the manufacturing method of this embodiment, the S / D (source / drain) forming mask of FIG. 4E of Pch and the LDD implantation mask of FIG. 4C can be commonly used. Therefore, the number of masks can be reduced by one as compared with the case of using separate masks.

(Embodiment 3) An electrostatic breakdown protection circuit according to the present invention will be described with reference to FIG.

FIG. 5 shows a circuit configuration of a portion for inputting / outputting a signal between an internal circuit (not shown) and an external device. An input / output pad 500 for inputting / outputting a signal is electrically connected to an internal circuit (not shown) via an input gate 506.

A wiring connecting the input gate 506 and the input / output pad 500 includes a first Nch MOSFET 501n,
First Pch MOSFET 501p, Second NchMO
SFET 502n and second PchMOSFET 50
Each drain of 2p is connected.

The source and gate of the first Nch MOSFET 501n are connected to the ground terminal 504, and the first Pc
The source and the gate of the hMOSFET 501p are connected to the power supply terminal 505. First NchMOSFET5
01n and the first Pch MOSFET 501p are connected to the ES
Functions as a D protection transistor. Second NchMO
The source of the SFET 502n is connected to the ground terminal 504, and the source of the second Pch MOSFET 502p is connected to the power supply terminal 505. Also, the second NchMO
Each gate of the SFET 502n and the Pch MOSFET 502p is connected to a drive circuit 503 of the I / O circuit. By the operation of the drive circuit 503, the input / output pad 5
An output signal is output on 00. In other words, the second
NchMOSFET 502n and second PchMOSF
ET502p is an I / O that also serves as an ESD protection transistor.
Also functions as an / O circuit.

The characteristic of the circuit shown in FIG.
NchMOSFET 501n, first PchMOSF
The ET 501p, the second Nch MOSFET 502n, and the second Pch MOSFET 502p have a configuration as shown in FIG. In other words, these MOSFETs have a single drain structure offset to the drain side, and have an LDD structure on the source side.

Since the first Nch MOSFET 501n and the first Pch MOSFET 501p have an offset single drain structure, the ESD breakdown voltage is high and the GIDL current is small. Further, the second Nch
Since the MOSFET and the second PchMOSFET have an offset single-drain structure and an LDD structure on the source side, the driving force is large.

The present invention is compared with the conventional example in terms of the layout area and the delay time when driving the I / O circuit. The same transistor is used as the protection transistor and the output transistor in both the present invention and the conventional example.

Conventional example 1: Both source and drain are LD
D structure Conventional example 2: Single drain structure in which both source and drain are offset As described in the first embodiment, the saturation current value of the N / Pch MOSFET per unit gate width in the case of the gate voltage and the drain voltage of 3 V obtained from the simulation Ids
at is Idsat (conventional example 1, N / Pch) = 0.329 / 0.12
5 (mA / μm) Idsat (conventional example 2, N / Pch) = 0.168 / 0.06
4 (mA / μm) Idsat (the present invention, N / Pch) = 0.259 / 0.09
8 (mA / μm), while N / PchMOSFE observed from the experiment
The ESD breakdown voltage of T is: ESD breakdown voltage (conventional example 1) = 0.53 (V / μ
m) ESD breakdown voltage (conventional example 2) = 1.14 (V / μ)
m) ESD breakdown voltage (the present invention) = 1.14 (V / μ)
m). In the chip of Conventional Example 1 manufactured by using a standard 0.5 μm CMOS process, the layout area of the protection and output transistors is as follows: protection transistor area (conventional example 1) = 35200 (μm)
² ) Output transistor area (conventional example 1) = 9072 (μm
² ) and the total is protection + output transistor area (conventional example 1) = 44272 (μm
² ) This is the protection + output transistor area required for one pad.

On the other hand, on the basis of Conventional Example 1, the layout area required to obtain the same breakdown voltage and the same driving force is as follows:
In the present invention, the protection transistor area (the present invention) = 8960 (μm
² ) Output transistor area (this invention) = 11616 (μm
² ) Protection + area of output transistor (this invention) = 20576 (μm)
² ) and is reduced by about 53% as compared with Conventional Example 1.

On the other hand, on the basis of Conventional Example 1, the layout area required to obtain the same breakdown voltage and the same driving force is as follows:
In Conventional Example 2, the protection transistor area (Conventional Example 2) = 2816 (μm
² ) Output transistor area (conventional example 2) = 17776 (μm
² ) Protection + output transistor area (conventional example 2) = 20592 (μm
² ) is almost the same as the present invention. Therefore, the junction capacitance, which is the load capacitance at the time of input, is almost the same, and the delay time at the time of input does not change.

However, in the present invention, the gate width of the I / O circuit is reduced to 56% of that of the conventional example 2, so that the gate capacitance which is a load capacitance at the time of output is reduced by 44% and the RC delay time due to the gate electrode is reduced by 68%. Therefore, the delay time at the time of output can be greatly improved.

In the present invention, since the gate length of the ESD protection circuit transistor is longer than the gate lengths of the other transistors, it is easy to form a pattern that crosses the gate, which has been a problem when a conventional asymmetric MOSFET is manufactured.

In this embodiment, the first Nch MOSFET
501n, a first PchMOSFET 501p, a second NchMOSFET 502n, and a second PchMOS
All of the FETs 502p have an asymmetric structure as shown in FIG. However, the first NchMOSFET
501n and / or first Pch MOSFET 501p
As for the above, a MOSFET having an offset type single drain structure having no LDD structure may be used. First Nch MOSFET 501n and first Pc
This is because the hMOSFET 501p only needs to function as an ESD protection circuit, and does not require as high a driving force as the second Nch MOSFET 502n and the second Pch MOSFET 502p.

(Embodiment 4) Another main body protection circuit according to the present invention will be described with reference to FIG.

FIG. 6 shows a circuit configuration of a portion for inputting and outputting signals between an internal circuit (not shown) and an external device. The input / output pad 606 for inputting / outputting a signal is electrically connected to an internal circuit (not shown) via the input gate 606.

A wiring connecting the input gate 606 and the input / output pad 600 includes a first Nch MOSFET 601n,
First Pch MOSFET 601p, second NchMO
SFET 602n and second PchMOSFET 60
Each drain of 2p is connected.

The source and gate of the first Nch MOSFET 601n are connected to the ground terminal 604, and the first Pc
The source and the gate of the hMOSFET 601p are connected to the power supply terminal 606. First Nch MOSFET 6
01n and the first PchMOSFET 601p are connected to the ES
Functions as a D protection transistor. Second NchMO
The source of the SFET 602n is connected to the ground terminal 604, and the source of the second PchMOSFET 602p is connected to the power supply terminal 605. Also, the second NchMO
Each gate of the SFET 602n and the PchMOSFET 602p is connected to a drive circuit 603 of the I / O circuit. The second Nch MOSFET 602n and the second Pch
The MOSFET 602p functions as an I / O circuit that also serves as an ESD protection transistor.

The first NchMOSFET 601n and the second NchMOSFET 602n have a single drain structure in which the source has an LDD structure and the drain is offset. On the other hand, the first Pc
hMOSFET 601p and second PchMOSFET
602p has an LDD structure for both its source and drain.

Here, the Pch MOSFET 601 and p6
02p is constituted by a MOSFET having a symmetric LDD structure for the following reason. Sunachiwa, PchMO
The SFET has a relatively high channel resistance and an NchMO.
Since the current does not easily flow than the SFET, PchMOSF
This is because, even if the ESD breakdown withstand voltage of the ET is lower than that of the NchMOSFET, when the ESD protection circuit is configured by CMOS, the ESD breakdown hardly occurs in the PchMOSFET.

PchMOSFET 601 and p602p
Is constituted by a MOSFET having a symmetrical LDD structure, the number of masks required for manufacturing the main hall protection circuit of the present embodiment may be increased by at most one in comparison with the related art.

In this embodiment, the first NchMOS
The FET 501n is also a second Nch MOSFET 502n.
Similarly to FIG. 1, it has an asymmetric structure as shown in FIG. However, as the first Nch MOSFET 501n, a symmetric MOSFET having an offset type single drain structure having no LDD structure may be used. Since the first Nch MOSFET 501n only has to function as an ESD protection circuit, the second Nch MOSFET
This is because a higher driving force is not required as in ET502n.

[0097]

According to the present invention, the following effects can be obtained.

According to the MOS type semiconductor device of the present invention, 1) Since the drain side has a single drain structure,
Since the electric field strength of the current path where the amount of current is maximized and the electric field strength at the PN junction between the diffusion layer and the substrate are alleviated as compared with the LDD structure, the ESD breakdown voltage is increased.

2) Because of the single drain structure in which the drain side is offset, the GIDL current is smaller than that in a case where a high concentration diffusion layer enters a normal gate end.

3) Since the source side has the LDD structure,
The driving force is improved as compared with a symmetrical MOSFET having a single drain structure in which the source side is also offset.

Further, in the CMOS structure, Nc
hMOSFET is replaced with an asymmetric transistor, Pch
When the MOSFET is an LDD transistor, the number of masks can be reduced by one without changing the ESD breakdown voltage.

According to the method of manufacturing a MOS semiconductor device of the present invention, an LDD implantation mask, which has been used in common with a conventional S / D (source / drain) formation mask, is separately provided.
In some transistors, the pattern is such that LDD implantation is not performed on the drain side, so that the ESD protection transistor has an offset single drain structure without increasing the number of steps and without using a special process. With the same number of masks as in the above case, the asymmetrical MOSFE having an offset single drain structure on the drain side and an LDD structure on the source side, which is very suitable for a MOSFET serving as both an I / O circuit and an ESD protection transistor.
T can be made.

In the pchMOSFET, the number of masks can be reduced by one by using the S / D (source / drain) formation mask and the LDD injection mask in common.

In addition to the asymmetric MOSFET,
A symmetric MOSFET can be easily formed at the same time.

According to the MOS type semiconductor device of the present invention, 1) the driving power of the I / O circuit is slightly reduced as compared with the case where both the ESD protection circuit and the I / O circuit have the LDD structure. , I / O circuit area slightly increases. However, since the ESD breakdown voltage increases, the area of the ESD protection circuit can be reduced. As a result, the layout area can be reduced as a whole. In addition, the driving force of the I / O circuit increases as compared with the case where both have the offset single drain structure. As a result, I
Since the gate width of the transistor of the / O circuit can be reduced, the area of the I / O circuit can be reduced.

2) The gate length of the ESD protection circuit transistor is larger than the gate lengths of the other transistors, so that it is easy to form a pattern crossing the gate, which has conventionally been a problem when manufacturing an asymmetric MOSFET.

3) Since the gate width can be greatly reduced by the effect of 1), the parasitic effect due to the junction capacitance as the load capacitance at the time of input and the gate electrode at the time of output can be greatly reduced, and the I / O circuit can be reduced. , The delay time when driving is improved.

Further, in a CMOS structure, I / O
NchMO that doubles as circuit and ESD protection transistor
An asymmetric transistor is used for SFET, PchMOS
By using an LDD transistor for the FET, E
It is possible to reduce the number of masks required to realize this apparatus by one while maintaining the SD breakdown voltage at the same level.

Therefore, the MOS type semiconductor device of the present invention
This is a MOS type semiconductor device which realizes high integration of an integrated circuit, has a high electrostatic breakdown voltage, and has high speed and low power consumption.

Further, the method of manufacturing a MOS semiconductor device according to the present invention is a method of easily obtaining the MOS semiconductor device, and its industrial value is extremely high.

[Brief description of the drawings]

FIG. 1 is a sectional view of a MOS type semiconductor device according to the present invention.

FIG. 2 is a sectional view of another MOS type semiconductor device according to the present invention.

FIGS. 3A to 3E are process cross-sectional views of the method for manufacturing the semiconductor device of FIG. 1;

FIGS. 4A to 4E are process cross-sectional views of the method for manufacturing the semiconductor device of FIG. 2;

FIG. 5 is a plan view of another semiconductor device according to the present invention.

FIG. 6 is a plan view of still another semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view of a conventional MOS type semiconductor device.

FIG. 8 is a cross-sectional view of a conventional MOS type semiconductor device.

FIG. 9 is a graph showing the difference in saturation current between the present invention and the conventional example.

FIG. 10 is a graph showing the difference between the present invention and the conventional example in ESD breakdown voltage.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 P-type semiconductor substrate 101 Gate oxide film 102 Gate electrode 103 Gate side wall 104 N-type low concentration diffusion layer 105 N-type high concentration diffusion layer 200 P-type semiconductor substrate 201 N-type well 202 LOCOS 203 Gate oxide film 204 Gate electrode 205 Gate side wall 206 N-type low concentration diffusion layer 207 P-type low concentration diffusion layer 208 N-type high concentration diffusion layer 209 P-type high concentration diffusion layer 300 P-type semiconductor substrate 301 Gate oxide film 302 Gate electrode 303 Gate side wall 304 N-type low concentration diffusion layer 305 N-type high concentration diffusion layer 306 Photoresist 400 P-type semiconductor substrate 401 N-type well 402 LOCOS 403 Gate oxide film 404 Gate electrode 405 Gate side wall 406 N-type low concentration diffusion layer 407 P-type low concentration diffusion layer 408 N-type high concentration Diffusion layer 409 P-type high concentration Spreading layer 410b Photoresist 410c Photoresist 410d Photoresist 410e Photoresist 500 Input / output pad 501n The source used for the ESD protection circuit is LDD, the first NchMOSFET having a drain offset structure 501p The source used for the ESD protection circuit is LDD, and the drain is offset The source used in the I / O circuit also serving as the first Pch MOSFET 502n ESD protection circuit having the structure is LDD, and the drain is the second N having the offset structure.
chMOSFET 502p The source used in the I / O circuit also serving as the ESD protection circuit is an LDD source, and the drain is an offset-structured second P
chMOSFET 503 I / O circuit drive circuit 504 Ground terminal 505 Power supply voltage terminal 506 Input gate 600 Input / output pad 601n Source used for ESD protection circuit is LDD, Source used for first NchMOSFET 601p ESD protection circuit having offset structure, The source is an LDD source, and the drain is a second N-type drain having an offset structure, which is used for an I / O circuit also serving as a first Pch MOSFET 602n ESD protection circuit having an LDD structure.
chMOSFET 602p Second PchMOS having LDD structure for both source and drain used for I / O circuit also serving as ESD protection circuit
FET 603 I / O circuit driving circuit 604 Ground terminal 605 Power supply voltage terminal 606 Input gate 700 P-type semiconductor substrate 701 Gate oxide film 702 Gate electrode 703 Gate side wall 704 N-type high concentration diffusion layer 800 P-type semiconductor substrate 801 Gate oxide film 802 Gate electrode 803 Gate sidewall 804 N-type low concentration diffusion layer 805 N-type high concentration diffusion layer

Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/092 (72) Inventor Akira Hiroki 1006 Odakadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Akira Miyanaga Osaka Prefecture 1006 Kadoma Kadoma, Matsushita Electric Industrial Co., Ltd. (72) Inventor Atsushi Hori 1006 Kadoma, Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (56) References JP-A-59-2375 (JP, A JP-A-55-108770 (JP, A) JP-A-6-188412 (JP, A) JP-A-61-207051 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/78 H01L 27/092

Claims (14)

(57) [Claims] 1. A has a top surface, a semiconductor substrate including a first conductive type region and the second conductive type region in contact with the upper surface, a first conductivity type MOS provided in the second conductivity type region of the semiconductor substrate A complementary asymmetric MOS type semiconductor device comprising: a transistor; and a second conductivity type asymmetric MOS transistor provided in the first conductivity type region of the semiconductor substrate, wherein the second conductivity type asymmetric MOS transistor comprises: A gate insulating film provided on the first conductive type region, a gate electrode provided on the gate insulating film, and a first electrode located immediately below the gate electrode on an upper surface of the first conductive type region A second conductivity type source region and a second conductivity type drain region provided in a second region offset to the outside of the region, wherein a portion of the semiconductor substrate between the first region and the source region is , Impurity diffusion of the second conductivity type A layer, wherein the second conductivity type impurity diffusion layer extends from the source region to the inside of the first region, whereby the second conductivity type impurity diffusion layer is formed on the upper surface of the first conductivity type region. The electrical resistance of a portion between the first region and the source region is smaller than the electrical resistance between the first region and the drain region, and the first conductivity type MOS transistor is provided in the second conductivity type region. A gate insulating film provided thereon, a gate electrode provided on the gate insulating film, and an upper surface of the second conductivity type region, which is offset to an outside of a third region located immediately below the gate electrode. A first conductivity type source region and a first conductivity type drain region provided in a fourth region; and a portion of the upper surface of the second conductivity type region between the third region and the source region. The electrical resistance between the third region and the drain region. Equal to, complementary asymmetric MO
S-type semiconductor device. Wherein said second conductivity type impurity diffusion layer has a lower impurity concentration than the impurity concentration of the source region, complementary asymmetric MOS semiconductor device according to claim 1. 3. The second conductivity type impurity diffusion layer has a thickness smaller than a maximum thickness of the source region.
2. The complementary asymmetric MOS semiconductor device according to 1. 4. The method according to claim 1, wherein the first conductivity type is a P-type, and the second conductivity type is a P-type.
The complementary asymmetric M according to claim 1 , wherein the conductivity type is N-type.
OS type semiconductor device. 5. The second conductive type asymmetric MOS transistors, between the drain region and the first region is not diffused layer of the second conductivity type impurities are present, complementary of claim 1 Type asymmetric MOS type semiconductor device. 6. A semiconductor substrate having an upper surface and including a first conductivity type region and a second conductivity type region in contact with the upper surface, and a first conductivity type MOS provided in the second conductivity type region of the semiconductor substrate.
A method for manufacturing a complementary asymmetric MOS semiconductor device comprising a transistor and a second conductivity type asymmetric MOS transistor provided in the first conductivity type region of the semiconductor substrate, comprising: a gate on the semiconductor substrate; Forming an insulating film; forming a gate electrode on the gate insulating film; forming a portion of the semiconductor substrate to be a drain region of the second conductivity type asymmetric MOS transistor and the second conductivity type region; A step of covering both with a first implantation stop layer, and a second conductivity type impurity diffusion formed in the first conductivity type region by using the first implantation stop layer and the gate electrode as a mask. Implanting such that the layer extends into the region immediately below the gate electrode; removing the first implantation stop layer; and implanting the first conductivity type region with a second implantation stop. Covering with a layer, using the second implantation stop layer and the gate electrode as a mask, implanting first conductivity type impurity ions into the second conductivity type region, and removing the second implantation stop layer. Providing a sidewall spacer on a side surface of the gate electrode; covering the second conductivity type region with a third implantation stop layer; using the third implantation stop layer and the gate electrode as a mask, Implanting impurity ions into the first conductivity type region, thereby forming source and drain regions of the second conductivity type asymmetric MOS transistor; removing the third implantation stop layer; Covering the conductivity type region with a fourth implantation stop layer; and implanting first conductivity type impurity ions into the second conductivity type region using the fourth implantation stop layer and the gate electrode as a mask. Comprising forming a source region and a drain region of the first conductivity type MOS transistor, a by Les method of the complementary asymmetric MOS device. As claimed in claim 7 wherein said fourth injection stop layer, using the layers having the same planar shape as the second injection stop layer, the manufacturing method according to claim 6. As claimed in claim 8 wherein said third injection stop layer, using a layer having a planar shape obtained by inverting the planar shape of the second injection stop layer, the manufacturing method according to claim 6. 9. The second conductive type asymmetric MOS transistor according to claim 6 , wherein no impurity ions of the second conductive type are implanted between the drain region and the region located immediately below the gate electrode. Manufacturing method. 10. An input / output pad for inputting / outputting an electric signal, a terminal for supplying a predetermined potential, a drain connected to the input / output pad, and a source and a gate connected to the terminal. An electrostatic discharge protection circuit comprising: a first NchMOSFET; a second NchMOSFET having a drain connected to the input / output pad and a source and a gate connected to the terminal; Each of the NchMOSFETs includes: a P-type semiconductor layer having an upper surface; a gate insulating film provided on the upper surface of the P-type semiconductor layer; a gate electrode provided on the gate insulating film; An N-type source region and an N-type drain region provided in a second region of the upper surface which is offset to the outside of the first region located immediately below the gate electrode. An N-type impurity diffusion layer extending from the source region to the inside of the first region on a portion of the upper surface of the P-type semiconductor layer between the first region and the source region. Is provided, whereby the electric resistance of the portion of the upper surface of the P-type semiconductor layer between the first region and the source region is reduced with respect to the second NchMOSFET. A power supply terminal for supplying a power supply voltage, a drain connected to the input / output pad, and a source and a gate connected to the power supply terminal. First PchMOSFE connected to terminal
T, a second PchMOSFE having a drain connected to the input / output pad and a source and a gate connected to the power supply terminal.
And T having a complementary structure , wherein each of the first and second PchMOSFETs includes an N-type semiconductor layer having a top surface; A gate insulating film provided on the upper surface; a gate electrode provided on the gate insulating film; and an offset outside the third region located directly below the gate electrode on the upper surface of the N-type semiconductor layer. And a P-type source region and a P-type drain region provided in the fourth region. The electric current of a portion between the third region and the source region on the upper surface of the N-type semiconductor layer is provided. An electrostatic discharge protection circuit, wherein a resistance is equal to an electric resistance between the third region and the drain region. 11. The first Nch MOSFET also includes an N-type impurity diffusion layer in a portion of the upper surface of the P-type semiconductor layer between the first region and the source region, Thereby, the first NchM
For an OSFET, the electrical resistance of a portion of the upper surface of the P-type semiconductor layer between the first region and the source region is:
The electrostatic discharge protection circuit according to claim 10 , wherein the electric resistance is smaller than an electric resistance between the first region and the drain region. For the method according to claim 11 wherein said first NchMOSFET, between the portion between the first region and the source region of said upper surface of the P-type semiconductor layer, and the first region and the drain region Are provided with an N-type impurity diffusion layer, whereby the first Nch
With respect to the MOSFET, an electric resistance of a portion of the upper surface of the P-type semiconductor layer between the first region and the source region is set to be equal to an electric resistance between the first region and the drain region. The electrostatic discharge protection circuit according to claim 10 , wherein: 13. The second NchMOSFET and the second PchMOSFET are connected to an output control circuit, and output an output signal on the input / output pad.
ESD protection circuit according to 10. 14. The electrostatic discharge protection circuit according to claim 10 , wherein in the second NchMOSFET, no diffusion layer of an N-type impurity exists between the drain region and the first region.