JP2878336B2 - Phased lock loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] For example, regarding a phased lock loop circuit used in a magnetic tape device, a clock synchronized with input data even when a change in recording density due to a tape speed fluctuation between writing and reading is added. A phase comparator that compares the phase of the synchronized signal and the synchronization signal, a charge pump that generates a control voltage by the phase difference output of the phase comparator, A phase locked loop circuit comprising: an amplitude clamp circuit that clamps an amplitude level of the control voltage; and a voltage control oscillator that oscillates a synchronization signal having a frequency corresponding to the control voltage. Select the first amplitude clamp circuit that constitutes one of the circuits,
A switch circuit for selecting a second amplitude clamp circuit forming the other of the amplitude clamp circuits in accordance with a write signal from U; and when writing, the amplitude of the control voltage is limited to a predetermined clamp level by the second amplitude clamp circuit. Then, at the time of reading, the control voltage is limited to a clamp level higher than the clamp level at the time of writing by the first amplitude clamp circuit.

[Industrial Application Field] The present invention relates to a phased lock loop circuit used for a magnetic tape device, for example.

In a phased lock loop circuit (PLL circuit) used in a data demodulation unit of a magnetic tape device, the width of a control voltage input to a voltage-controlled oscillator in the PLL circuit can be changed during a read-after-write (hereinafter, referred to as a read-after-write). At the time of reading) and at the time of normal reading (hereinafter referred to as reading).

For this reason, even if the recording speed changes due to a change in the medium speed at the time of writing, if the change is within an allowable range, it can be read normally at the time of writing, but at the time of reading, the medium is further added to the change of the recording density. When the speed fluctuation is added, it exceeds the change in the control voltage, so that the PLL circuit cannot correctly synchronize with the input and may not be able to perform data demodulation correctly.

Therefore, it is necessary to reliably synchronize with the input even when the change force at the time of reading is added to the change in the recording density at the time of writing.

[Prior Art] FIG. 3 shows a PLL in a data demodulation unit of a magnetic tape device.
Indicates the positioning of the circuit.

In FIG. 3, reference numeral 1 denotes a head, and the head 1 reads data from the recording medium 2 and writes data on the recording medium 2. Reference numeral 3 denotes an amplifier, and the amplifier 3 amplifies data read by the head 1. From the read data amplified by the amplifier 3, a peak pulse is generated by the pulse shaping circuit 4. The PLL circuit 5 outputs a synchronous clock synchronized with the peak pulse based on the input of the peak pulse generated by the pulse shaping circuit 4 and the synchronous clock output from the PLL circuit 5. The data demodulation circuit 6 demodulates the peak pulse from the pulse shaping circuit 4 with the synchronous clock from the PLL circuit 5,
The demodulated data is output to the processor 7.

 Next, FIG. 4 shows an internal configuration of the PLL circuit 5.

In FIG. 4, 5A is a phase comparator that compares the phase of the peak pulse and the synchronous clock to output a phase difference, 5B is a charge pump that generates a control voltage based on the phase difference, and 5C is an amplitude level of the control voltage. An amplitude clamp circuit for clamping, 5D is a filter for cutting unnecessary high frequency noise, and 5E is a voltage controlled oscillator for generating a synchronous clock having a frequency corresponding to the control voltage.

One amplitude clamp circuit 5C is provided between the charge pump 5B and the voltage-controlled oscillator 5E, and the width in which the control voltage can be changed is the same as that during writing and during reading.

[Problems to be Solved by the Invention] However, in such a conventional PLL circuit, when the running speed of the tape changes when writing data to the magnetic tape, the recording density of the written data is also reduced. It changes according to the change in running speed, and at the time of reading, the tape speed change at the time of reading is added to the tape speed change at the time of writing.

For this reason, if a similar tape speed fluctuation occurs when reading written data due to fluctuations in the depth clamp speed of the amplitude clamp level of the control voltage of the PLL circuit during writing, the amplitude of the control voltage is clamped. As a result, the PLL circuit cannot output a synchronous clock synchronized with the input data.

The present invention has been made in view of such a conventional problem, and outputs a clock synchronized with input data even when a change in recording density due to a tape speed fluctuation between writing and reading is added. It is an object of the present invention to provide a PLL circuit that can perform the operation.

[Means for Solving the Problems] FIG. 1 is an explanatory view of the principle of the present invention.

In FIG. 1, a phase comparator 11 for comparing the phase of a signal to be synchronized with a synchronization signal, and a charge pump 12 for generating a control voltage based on the phase difference output of the phase comparator 11
And a voltage-controlled oscillator 14 that oscillates a synchronization signal having a frequency corresponding to the control voltage, and an amplitude clamp circuit that clamps the amplitude level of the control voltage. Selecting a first amplitude clamp circuit 20 that constitutes one of the amplitude clamp circuits;
A switch circuit 15 for selecting a second amplitude clamp circuit 17 that constitutes the other of the amplitude clamp circuits by a write signal from the MPU is provided. The amplitude is limited, and at the time of reading, the first amplitude clamp circuit 20 limits the control voltage to a clamp level larger than the clamp level at the time of writing.

[Operation] In the present invention, at the time of writing, the switch circuit switches to the second amplitude clamp circuit and disconnects the first amplitude clamp circuit. At the time of reading, the switch circuit switches to the first amplitude clamp circuit. 2 is disconnected.

Therefore, the amplitude of the control voltage is limited to a small clamp level at the time of writing, and the amplitude of the control voltage is limited to a clamp level larger than the clamp level at the time of reading.

Therefore, the control voltage falls within the clamp level of the read amplitude clamp circuit even when the tape speed fluctuations at the time of writing and at the time of reading are added. That is,
The PLL circuit can output a synchronous clock correctly synchronized with the input data, and the reading is performed correctly.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

 FIG. 2 shows an embodiment of the present invention.

First, the configuration will be described. In FIG. 2, reference numeral 11 denotes a phase comparator to which a peak pulse (a synchronized signal) generated by a pulse shaping circuit and a synchronous clock (a synchronous signal) are input.
The phase comparator 11 compares the phase of the peak pulse with the phase of the synchronous clock. Reference numeral 12 denotes a charge pump. The charge pump 12 generates a control voltage by its pumping action based on the phase difference output of the phase comparator 11. Reference numeral 13 denotes a filter, and the filter 13 cuts unnecessary high frequency noise of the control voltage. 14 is a voltage controlled oscillator,
The voltage control oscillator 14 outputs a synchronous clock having a frequency corresponding to the control voltage to a data demodulation circuit (not shown).

Reference numeral 15 denotes a switch circuit. The switch circuit 15 rewrites the contact to the a side by a write signal from the MPU 16 and the b side by a read signal.

Reference numeral 17 denotes a second amplitude clamp circuit (hereinafter referred to as a write amplitude clamp circuit) provided on the side a. The write amplitude clamp circuit 17 includes one diode 18 in the forward direction and one in the reverse direction with respect to the GND level. Has 19

Reference numeral 20 denotes a first amplitude kump circuit (hereinafter referred to as a read amplitude clamp circuit) connected to the b side. The read amplitude clamp circuit 20 includes two diodes 21 in the forward and reverse directions with respect to the GND level. , 22,23,24.

 Next, the operation will be described.

At the time of writing, when a write signal (H level) of the MPU 16 is output to the switch circuit 15, the switch circuit 15 is switched to the a side, the write amplitude clamp circuit 17 is connected, and the read amplitude clamp circuit 20 is disconnected.

The write amplitude clamp circuit 17 has one diode 18 and 19 in the forward direction and one diode in the reverse direction, and the control voltage is equivalent to one step of the voltage drop of the diodes 18 and 19 (about 0.7 V).
V), it changes between + 0.7V and -0.7V. Assuming that the change in the tape speed with respect to the change in the control voltage for one diode is 1, the allowable speed change during writing is ± 1.

Next, when the MPU 16 outputs a read signal (L level) to the switch circuit 15 during reading, the switch circuit 15 is switched to the b side, the read amplitude clamp circuit 20 is connected, and the write amplitude clamp circuit 17 is disconnected. It is.

The read amplitude clamp circuit 20 has two diodes 21, 22, 23, and 24 in the forward and reverse directions, and the control voltage is clamped to two steps of voltage drop (about 1.4 V). Between + 1.4V and -1.4V. The change in the tape speed with respect to the change in the control voltage for two diodes is 2.

That is, during reading, the allowable speed change is ± 2. Accordingly, it is possible to cope with a speed change of ± 2 obtained by adding a speed change of ± 1 at the time of reading to a speed change of ± 1 at the time of writing. As a result, a synchronous clock that is correctly synchronized with the input data can be output during reading, and reading can be performed correctly.

In this embodiment, since the amplitude level of the control voltage with respect to the speed fluctuation at the time of writing is reduced, there is also an advantage that the writing quality is improved.

[Effects of the Invention] As described above, according to the present invention, the amplitude clamp circuit is divided into the write amplitude clamp circuit and the read amplitude clamp circuit, and the amplitude of the control voltage is changed between at the time of writing and at the time of reading. Since the level is changed, even when a change in recording density due to a change in tape speed between writing and reading is added, a clock that is correctly synchronized with input data can be output, and reading can be performed correctly.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating a data demodulation unit, and FIG. 4 is a diagram illustrating a conventional example. In the figure, 11: phase comparator, 12: charge pump, 13: filter, 14: voltage controlled oscillator, 15: switch circuit, 16: MP
U, 17: amplitude clamp circuit for writing (second amplitude clamp circuit), 18, 19, 21 to 24: diode, 20: amplitude clamp circuit for reading (first amplitude clamp circuit).

Claims (1)

(57) [Claims] 1. A phase comparator for comparing a phase of a synchronized signal with a synchronization signal, a charge pump for generating a control voltage by a phase difference output of the phase comparator, and an amplitude clamp for clamping an amplitude level of the control voltage. And a voltage controlled oscillator oscillating a synchronization signal having a frequency corresponding to the control voltage, wherein a first amplitude clamp constituting one of the amplitude clamp circuits by a read signal from an MPU is provided. Select the circuit and MPU
A switch circuit for selecting a second amplitude clamp circuit that constitutes the other of the amplitude clamp circuits according to a write signal from the control circuit, and when writing, the amplitude of the control voltage is limited to a predetermined clamp level by the second amplitude clamp circuit. A phase locked loop circuit for limiting a control voltage to a clamp level larger than a clamp level at the time of writing by the first amplitude clamp circuit at the time of reading.