JPH03136413A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To output a clock correctly synchronously with an input data even when a change in recording density due to tape speed fluctuation at write and read is accumulated by varying a level of a control voltage with the write state and the read state. CONSTITUTION:A 1st amplitude clamp circuit 20 and a 2nd amplitude clamp circuit 17 having a different clamp level from that of the 1st amplitude clamp circuit 20. Then the 2nd amplitude clamp circuit 17 is selected at the write by a switch circuit 15 and the 1st amplitude clamp circuit 20 is selected at write. Then the level of the control voltage is limited to a small clamp level at write and the amplitude of the control voltage is limited to a large clamp level at write. Thus, even when a change in recording density due to tape speed fluctuation at write and read is accumulated, a synchronizing clock correctly synchronously with an input data is outputted and read is implemented correctly.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a phased-lock loop circuit used in a magnetic tape device, even when changes in recording density due to changes in tape speed during writing and reading are added, a clock synchronized with input data can be used. A phase comparator that compares the phases of a synchronized signal and a synchronized signal, and a charge pump that generates a control voltage based on the phase difference output of the phase comparator. A phased-locked loop circuit comprising: an amplitude clamp circuit that clamps the amplitude level of the control voltage; and a voltage controlled oscillator that oscillates a synchronization signal with a frequency corresponding to the control voltage; An amplitude clamp circuit;
A second amplitude clamp circuit having a different ramp level from the first amplitude clamp circuit, and a switch circuit (15) for switching between the first amplitude clamp circuit and the second amplitude clamp circuit. did.

[Field of Industrial Application] The present invention relates to a phased-lock loop circuit used in, for example, a magnetic tape device.

In a phased-locked loop circuit (PLL circuit) used in the data demodulation section of a magnetic tape device, the range in which the control voltage input to the voltage controlled oscillator in the PLL circuit can change is determined by the width during read/after write (
It is the same for both the write time (hereinafter referred to as write time) and the normal read time (hereinafter referred to as read time).

Therefore, even if the recording density changes due to fluctuations in the media speed during writing, if the change is within the allowable range, during writing,
The data can be read normally, but when the media speed variation is added to the recording density variation during reading, the PLL circuit will not be able to properly synchronize with the input because it will exceed the control voltage variation. , data demodulation could not be performed correctly.

Therefore, it is necessary to reliably synchronize with the input even if the changing force during reading is added to the change in recording density during writing.

[Prior art] Figure 3 shows a PLL in a data demodulation section of a magnetic tape device.
Shows the position of the circuit.

In FIG. 3, 1 is a head, and the head 1 reads data from a recording medium 2 and also writes data to the recording medium 2. 3 is an amplifier, and amplifier 3 is connected to head 1.
amplify the data read by From the read data amplified by the amplifier 3, a peak pulse is generated by the pulse shaping circuit 4. The PLL circuit 5 receives the peak pulse generated by the pulse shaping circuit 4 and the synchronous clock outputted from the PLL circuit 5, and outputs a synchronous clock synchronized with the peak pulse. The data demodulation circuit 6 demodulates the peak pulse from the pulse shaping circuit 4 using the synchronous clock from the PLL circuit 5 and outputs the demodulated data to the processor 7.

Next, FIG. 4 shows the internal configuration of the PLL circuit 5.

In Fig. 4, 5A is a phase comparator that compares the phases of the peak pulse and the synchronization clock and outputs a phase difference, 5B is a charge pump that generates a control voltage based on the phase difference, and 5C is a phase comparator that generates a control voltage based on the phase difference. 5D is a filter that cuts unnecessary high-frequency noise; and 5E is a voltage-controlled oscillator that generates a synchronized clock with a frequency corresponding to the control voltage.

1 between the charge pump 5B and the voltage controlled oscillator 5E.
Two amplitude clamp circuits 5C are provided, and the width in which the control voltage can change is the same during writing and reading.

[Problems to be Solved by the Invention] However, in such a conventional PLL circuit, when the running speed of the tape changes when writing data to the magnetic tape, the recording density of the written data also changes from the tape. It changes according to the change in running speed, and when reading, the change in tape speed during reading is added to the change in tape speed during writing.

Therefore, if a tape speed variation occurs at the limit of the amplitude clamp level of the control voltage of the PLL circuit during writing, and a similar tape speed variation occurs when reading the written data, the amplitude clamp level of the control voltage This causes a problem in that the PLL circuit cannot output a synchronized clock synchronized with the input data.

The present invention was made in view of these conventional problems, and is capable of outputting a clock synchronized with input data even when changes in recording density due to variations in tape speed during writing and reading are added. The purpose of the present invention is to provide a PLL circuit that can perform the following steps.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 11 is a phase comparator that compares the phases of the synchronized signal and the synchronizing signal, 12 is a charge pump that generates a control voltage based on the phase difference output of the phase comparator 11, and 14 is a charge pump that responds to the control voltage. 20 is a first amplitude clamp circuit; 26 is a first amplitude clamp circuit 20;
A second amplitude clamp circuit 15 having a clamp level different from that of the first amplitude clamp circuit 15 is a switch circuit for switching between the first amplitude clamp circuit 20 and the second amplitude clamp circuit 17.

[Function] In the present invention, when writing, the switch circuit switches to the second amplitude clamp circuit and disconnects the first amplitude clamp circuit, and when reading, the switch circuit switches to the first amplitude clamp circuit and disconnects the first amplitude clamp circuit. 2. Disconnect the amplitude clamp circuit.

Therefore, during writing, the amplitude of the control voltage is limited to a small ramp level, and during reading, the amplitude of the control voltage is limited to a larger ramp level than the clamp level during writing.

Therefore, even if the tape speed fluctuations during writing and reading are added, the control voltage remains within the clamp level of the reading amplitude clamp circuit. That is, P
The LL circuit can output a synchronized clock that is correctly synchronized with the input data, so that reading is performed correctly.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

First, to explain the configuration, in FIG. 2, 11 is a phase comparator into which the peak pulse (synchronized signal) generated by the pulse shaping circuit and the synchronized clock (synchronized signal) are input.
The phase comparator 11 compares the phases of the peak pulse and the synchronization clock. 12 is a charge pump, and the charge pump 12 is based on the phase difference output of the phase comparator 11.
The pump action generates a control voltage.

13 is a filter, and the filter 13 cuts unnecessary high frequency noise of the control voltage. Reference numeral 14 denotes a voltage controlled oscillator, and the voltage controlled oscillator 14 outputs a synchronous clock having a frequency corresponding to the control voltage to a data demodulation circuit (not shown).

15 is a switch circuit, and the switch circuit 15 is an MPU.
The contact is switched to the a side by a write signal from 16, and to the b side by a read signal.

17 is a second amplitude clamp circuit (hereinafter referred to as a write amplitude clamp circuit) provided on the a side, and the write amplitude clamp circuit 17 has diodes 18 . It has 19.

20 is a first amplitude clamp circuit (hereinafter referred to as a reading amplitude clamp circuit) connected to the b side, and the reading amplitude clamp circuit 20 includes two diodes 21 in the forward direction and in the reverse direction with respect to the GND level. .22, 23.24.

Next, the operation will be explained.

During writing, when the MPU 16 outputs a write signal (H level) to the switch circuit 15, the switch circuit 15
The write amplitude clamp circuit 17 is connected and the read amplitude clamp circuit 20 is disconnected.

The write amplitude clamp circuit 17 has one diode 18, one in the forward direction and one diode 19 in the reverse direction, and the control voltage is clamped to one stage voltage drop (approximately 0.7 V) of the diodes 18 and 19. +0.7 by
It changes between V ~ -〇, 7v. Assuming that the change in tape speed with respect to the change in control voltage for one stage of diode is 1, the permissible speed change during writing is ±1.

Next, at the time of reading, the MPU 16 outputs a read signal (L level).
When this is output to the switch circuit 15, the switch circuit 15 is switched to the b side, the reading amplitude clamp circuit 20 is connected, and the writing amplitude clamp circuit 17 is disconnected.

The reading amplitude clamp circuit 20 includes two diodes 21 . in the forward direction and two in the reverse direction. 22. 23.24, and the control voltage is two steps of voltage drop (approximately 1
．． +1.4v to -1 by being clamped to 4V)
, 4v.

The change in tape speed with respect to the change in control voltage for two stages of diodes is 2.

That is, during reading, the allowable speed change is ±2. Therefore, it is possible to cope with a speed change of ±2, which is the sum of the speed change ±1 during writing and the speed change ±1 during reading. As a result, a synchronous clock that is correctly synchronized with the input data can be output even during reading, and reading can be performed correctly.

Note that in this embodiment, since the amplitude level of the control voltage with respect to speed fluctuations during writing is made small, there is also the advantage of improving the writing quality.

[Effects of the Invention] As described above, according to the present invention, the amplitude clamp circuit is divided into a writing amplitude clamp circuit and a reading amplitude clamp circuit, and the amplitude of the control voltage is adjusted between writing and reading. Since the level was changed,
Even when changes in recording density due to variations in tape speed during writing and reading are added, a clock that is correctly synchronized with input data can be output, and reading can be performed correctly.

[Brief explanation of the drawing]

1 is a diagram illustrating the principle of the present invention, 2rgA is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing a data demodulation section, and FIG. 4 is a diagram showing a conventional example. In the figure, 1... Phase comparator, 2... Charge pump, 3... Filter, 4... Voltage controlled oscillator, 5... Switch circuit, 6... MPU. 7... Writing amplitude clamp circuit (second amplitude clamp circuit), 18.19.21-24... Diode, 20...
A reading amplitude clamp circuit (first amplitude clamp circuit).

Claims (1)

[Claims] A phase comparator (11) that compares the phases of a synchronized signal and a synchronizing signal, and a charge pump (12) that generates a control voltage based on the phase difference output of the phase comparator (11).
an amplitude clamp circuit that clamps the amplitude level of the control voltage; and a voltage controlled oscillator (14) that oscillates a synchronization signal with a frequency corresponding to the control voltage.
In the phased-locked loop circuit, the amplitude clamp circuit includes a first amplitude clamp circuit (2
0) and a second amplitude clamp circuit (17) having a different clamp level from the first amplitude clamp circuit (20).
), the first amplitude clamp circuit (20), and the second amplitude clamp circuit (20);
A phased lock loop circuit comprising: a switch circuit (15) for switching an amplitude clamp circuit (17);