JP2877374B2 - Multiprocessor control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] In a data processing system in which clusters constituting a tightly coupled multiprocessor are loosely coupled to each other, a machine check is performed when a system storage device shared between clusters is provided. The purpose of the multiprocessor controller for effective execution is to make it possible for other clusters to recognize that an error has occurred in accessing the system storage device, and to prevent erroneous control from occurring. A cluster having at least a device, one or more main processing devices, and a storage control device that mediates data transfer between the main storage device and the main processing device; In the created data processing system, each of the above clusters A shared system storage device to be accessed is provided, and each of the clusters individually includes a system storage mover for performing control in accessing the system storage device, and the system storage mover comprises: When an error occurs in response to the access by the exclusive control command performed by the main processing unit in the cluster to the system storage device, the main processing unit in the accessed cluster is notified of the error. At the same time, a signal notifying means for notifying the main processing device in another cluster of this fact is provided.

[Industrial applications]

The present invention enables a machine check when a system storage device shared between clusters is provided in a data processing system in which clusters forming a multiprocessor control device, particularly, tightly coupled multiprocessors are loosely coupled to each other. To a multiprocessor control device for executing the program.

A system storage device (SSU) shared by a plurality of clusters loosely coupled via a database or the like is provided, and the system storage device is used as high-speed temporary storage means or exclusive information storage means between systems.

[Conventional technology]

FIG. 1 is a block diagram showing the principle of the present invention. Since the conventional configuration corresponds to a configuration in which the signal notifying means 9 shown in FIG. 1 does not exist, the conventional configuration will be described with reference to FIG. Will be described.

In the figure, 1 is a cluster, 2 is a database, 3 is a system storage device, 4 is a main processing unit, 5 is a channel processor, 6
Denotes a storage control device, 7 denotes a main storage device, and 8 denotes a system storage mover.

In each cluster 1-i, the main processing unit 4-ij forms a tightly coupled multiprocessor, and the processing proceeds while accessing the main storage unit 7-ij via the storage control unit 6-i. Each cluster 1-i is provided with a channel processor 5-
Access the database 2 via i.

Then, a system storage device 3-k shared between the clusters 1-i is provided. The system storage mover 8-i belonging to each cluster 1-i stores its own cluster 1-i
Of the main storage device 4-ij and the like in the system storage device 3-k.

The system storage device 3-k is constituted by a semiconductor storage device, and (i) exclusive information of a database;
(Ii) Resident database / data set, (iii) transaction information, etc. are set.

By having such a system storage device 3-k, not only high-speed access is possible and transaction processing performance is improved, but also when one cluster 1-0 goes down, the cluster 1-0 performs processing. There is a great advantage that the transaction can be recovered at high speed by the other cluster 1-1. The system storage device 3-k is
Since it is used for such a purpose, it is generally duplicated. For exclusive control of the system storage device 3-k itself, an access method similar to a CDS instruction (compare double and swap instruction) generally used as an exclusive control instruction of the main storage device 7 is employed.

FIG. 3 is a schematic diagram of a conventional system storage device machine check circuit. In the figure, reference numerals 8-0 indicate a system storage mover, 4-00 indicates one main processing unit in the cluster 1-0, 10 indicates a machine check interception code, and 11 indicates a state control logic corresponding to the occurrence of an interrupt. State machines representing circuits, 12-00 and 12-01 are AND logic units, CPU00 is main processing unit 4-00, and CPU01 is main processing unit 4-01.
Is represented. 13, 14, and 15 represent flags, respectively.

Now, the main processing unit 4-00 is the system storage unit (SSU) 3
Assume that an error occurs in the system storage unit (SSU) at the time of accessing −k. In this case, the flag 13 and the flag 14 are set, and the AND logic
An error is reported to main processor 4-00 via 12-00. As a result, a machine check interception code 10 is created, and the state machine 11 is activated to generate a machine check interrupt. Main processing unit 4-
00 reads out the code 10 in the interrupt processing and stores the code 10 in a fixed address of the main storage device 7 so that the software recognizes the cause of the machine check interrupt. The software correspondingly responds to the system storage (SS
U) When the error of 3-k is recognized, the system storage device (SSU) 3-k is disconnected.

[Problems to be solved by the invention]

In the case of the data processing system as described above, that is, in the case of the system in which the signal notifying means 9 shown in FIG. 1 does not exist, it has been found that the following inconvenience occurs. That is, for example, when the cluster 1-0 executes the CDS instruction on the system storage device 3-k, the main device 3-0
It is assumed that the writing to the conventional device 3-1 has succeeded but the writing to the conventional device 3-1 has succeeded. FIG. 4 illustrates this state. In FIG. 4, "0" indicates an empty state, "4" indicates a state in which cluster 1-0 is reserved,
“8” indicates a state in which the cluster 1-1 reserves.

Under the state of FIG. 4, the cluster 1-0 disconnects the system storage device 3-0 as a result of the machine check process, and the process in which the interrupt has occurred is continued using the system storage device 3-1.

At this time, as shown in the state of FIG. 4, a CDS instruction is issued from the other cluster 1-1 to the same address, and the CDS instruction is issued immediately after the CDS instruction by the cluster 1-0. It is assumed that -0 is executed before disconnection, and that the CDS instruction by the cluster 1-0 also successfully accesses the main system storage device 3-0.

In this case, as shown in FIG. 4, the reserve information in the system storage device 3-k by the cluster 1-1 becomes undesired. At this point, cluster 1
Both −0 and the cluster 1-1 operate assuming that exclusive control has been performed on the address area. As a result, the equivalence of the duplicated system storage device 3-k is broken.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent another cluster from recognizing that an error has occurred in accessing a system storage device, thereby preventing erroneous control from occurring.

[Means for solving the problem]

 FIG. 1 shows a principle configuration diagram of the present invention.

In the figure, 1 is a cluster, 2 is a database, 3 is a system storage device, 4 is a main processing unit, 5 is a channel processor, 6
Is a storage controller, 7 is a main storage, 8 is a system storage mover, and 9 is a signal notifying means, which is provided in the present invention. Indicates that there is an access error.

In each cluster 1-i, the main processing unit 4-ij constitutes a tightly coupled multiprocessor, and the processing proceeds while accessing the main storage unit 7-ij via the storage control unit 6-i.
Each cluster 1-i accesses the database 2 via the channel processor 5-i.

Then, a system storage device 3-k shared between the clusters 1-i is provided. The system storage mover 8-i belonging to each cluster 1-i stores its own cluster 1-i
Of the main storage device 4-ij and the like in the system storage device 3-k.

In the present invention, the system storage mover 8-i is provided with signal notification means 9-i. That is, conventionally, in the system storage mover 8-i, (i) a flag is set in response to an access to the system storage device 3-k from the main processing device 4-ij belonging to the own cluster 1-i, ii) When an error occurs in response to the access to the system storage device 3-k, a flag relating to the system storage device error is set, and (iii) an error occurs in the main processing device 4-ij that has accessed the current operation. However, in the present invention, (iv) not only to the main processing unit, for example, 4-00, which has made the current access, but also to the signal processing unit 9-0. The above error is also notified to the other main processing units 4-01 in the cluster 1-0. Also within the cluster 1-1, the system storage mover 8-1 knows the above error and sends, via the signal notifying means 9-1, to the main processing units 4-10 and 4-11 which are not currently accessing. Also notify the above error.

(Operation)

In the case of the present invention, each system storage mover 8-0,
8-1 recognizes that an error has occurred when the system storage device 3-k is accessed, and sends all the data belonging to its own cluster via the signal notifying means 9-0 and 9-1. Notify the main processing units 4-0j and 4-1j.

As a result, unlike the conventional case, the equivalence of the duplicated system storage devices is not broken.

〔Example〕

FIG. 2 is a schematic diagram of a system memory device machine check circuit in the case of the present invention. The reference numerals in the figure correspond to those in FIG. 3, and represent AND logic units that output logic "1" when one of the input signals 16-00 and 16-01 is logic "0".

The main processing unit 4-00 shown is a system storage unit (SSU)
Consider a case where an error occurs as a result of accessing 3-k based on, for example, a CDS instruction. In this case, the flag 13 and the flag 14 both become logic "1", and the notification from the AND logic unit 12-00 to the main processing unit 4-00 is the conventional case (FIG. 3). ) Is the same. However, in the case of the present invention, since the illustrated flag 15 is logic "0", the other main processing unit CPU01 which is not currently accessed, that is, 4-01, is not accessed via the AND logic unit 16-01. , An error is notified. That is, although not shown, the logic "1" is also set in the main processing unit 4-01 at a position corresponding to the mark * in the machine check interception code (MCIC) 10 shown in FIG.

Of course, although not shown, the system storage mover 8
Even at -1, the flag corresponding to the flag 13 shown in FIG. 2 becomes logic "1". As a result, the AND logic units 16-10, 16 corresponding to the AND logic units 16-00, 16-01 shown in FIG.
From -11 (not shown), the occurrence of the error is also notified to each of the main processing units 4-10 and 4-11 in the cluster 1-1.

〔The invention's effect〕

As described above, according to the present invention, in all so-called main processing units, for example,
At the time of access by the CDS instruction, it is possible to know that an error has occurred, and the equivalence in a duplicated system storage device is not broken.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a schematic diagram of a system storage device machine check circuit in the case of the present invention, FIG. 3 is a schematic diagram of a conventional system storage device machine check circuit, and FIG. FIG. 2 is an explanatory diagram illustrating a problem of the invention. In the figure, 1 is a cluster, 2 is a data base, 3 is a system storage device, 4 is a main processing unit, 5 is a channel processor, 6 is a storage controller, 7 is a main storage device, 8 is a system storage mover, 9 Represents signal notification means.

Claims (3)

(57) [Claims] 1. A cluster comprising at least a main storage device, one or more main processing devices, and a storage control device that mediates data transfer between the main storage device and the main processing device. In addition, in a data processing system in which a plurality of the clusters are provided, a shared system storage device that is commonly accessed by each of the clusters is provided, and each of the clusters accesses the system storage device. And a system storage mover for executing the control in the cluster, and the system storage mover responds to an access by an exclusive control instruction performed on the system storage device by the main processing unit in the cluster. When an error occurs, notify the main processing unit in the accessing cluster of the error. And a signal notifying means for notifying the main processing device in another cluster of this fact. 2. The multiprocessor control device according to claim 1, wherein a plurality of clusters provided in said data processing system are connected via a database. 3. The multiprocessor control device according to claim 1, wherein the connection of the plurality of clusters is a loose connection.