JP2876844B2 - Output voltage correction circuit for IC tester driver - Google Patents

Output voltage correction circuit for IC tester driver

Info

Publication number
JP2876844B2
JP2876844B2 JP3235768A JP23576891A JP2876844B2 JP 2876844 B2 JP2876844 B2 JP 2876844B2 JP 3235768 A JP3235768 A JP 3235768A JP 23576891 A JP23576891 A JP 23576891A JP 2876844 B2 JP2876844 B2 JP 2876844B2
Authority
JP
Japan
Prior art keywords
output
voltage
input terminal
input
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3235768A
Other languages
Japanese (ja)
Other versions
JPH0552908A (en
Inventor
優一 岩本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ando Electric Co Ltd
Original Assignee
Ando Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric Co Ltd filed Critical Ando Electric Co Ltd
Priority to JP3235768A priority Critical patent/JP2876844B2/en
Publication of JPH0552908A publication Critical patent/JPH0552908A/en
Application granted granted Critical
Publication of JP2876844B2 publication Critical patent/JP2876844B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、ICテスタ用ドライ
バの出力電圧を設定電圧と等しくするための出力電圧補
正回路についてのものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output voltage correction circuit for making an output voltage of an IC tester driver equal to a set voltage.

【0002】[0002]

【従来の技術】次に、従来技術によるドライバの出力電
圧補正回路の構成を図2により説明する。図2の1と2
は増幅器、3はドライバ、31と32はドライバ3の出
力レベル補正用の可変抵抗器、4はスイッチ、5は電圧
測定器である。
2. Description of the Related Art Next, the configuration of a conventional driver output voltage correction circuit will be described with reference to FIG. 1 and 2 in FIG.
Is an amplifier, 3 is a driver, 31 and 32 are variable resistors for correcting the output level of the driver 3, 4 is a switch, and 5 is a voltage measuring device.

【0003】図2の1Aは増幅器1の入力端子、2Aは
増幅器2の入力端子、3Aはドライバ3の入力端子、3
Bはドライバ3の出力端子、3Cと3Dはドライバの入
力端子である。入力端子3Aが正論理のとき、ドライバ
3の出力端子3Bには入力端子3Cの電圧が出力され、
入力端子3Aが負論理のとき、ドライバ3の出力端子3
Bには入力端子3Dの電圧が出力される。
In FIG. 2, 1A is the input terminal of the amplifier 1, 2A is the input terminal of the amplifier 2, 3A is the input terminal of the driver 3, 3
B is an output terminal of the driver 3, and 3C and 3D are input terminals of the driver. When the input terminal 3A has positive logic, the voltage of the input terminal 3C is output to the output terminal 3B of the driver 3,
When the input terminal 3A has a negative logic, the output terminal 3
The voltage at the input terminal 3D is output to B.

【0004】入力端子3Aが正論理のときのドライバ3
の出力端子3Bと、入力端子3Aが負論理のときのドラ
イバ3の出力端子3Bには、それぞれオフセット誤差と
ゲイン誤差が含まれる。そこで、入力端子3Aが正論理
のときのドライバ3の出力端子3Bのオフセット誤差を
可変抵抗器31で補正し、入力端子3Aが負論理のとき
のドライバ3の出力端子3Bのオフセット誤差を可変抵
抗器32で補正する。スイッチ4をオンにすると、出力
端子3Bの電圧が電圧測定器5で測定される。ICテス
タでは、入力端子1Aと入力端子2Aの電圧はプログラ
マブルであり、数百msの間にいろいろな電圧が設定さ
れるので、ゲイン誤差については補正されていない。
When the input terminal 3A has a positive logic, the driver 3
The output terminal 3B of the driver 3 and the output terminal 3B of the driver 3 when the input terminal 3A has a negative logic include an offset error and a gain error, respectively. Therefore, the offset error of the output terminal 3B of the driver 3 when the input terminal 3A has the positive logic is corrected by the variable resistor 31, and the offset error of the output terminal 3B of the driver 3 when the input terminal 3A has the negative logic is changed by the variable resistor. The correction is performed by the detector 32. When the switch 4 is turned on, the voltage of the output terminal 3B is measured by the voltmeter 5. In the IC tester, the voltages of the input terminal 1A and the input terminal 2A are programmable, and various voltages are set within several hundred ms, so that the gain error is not corrected.

【0005】例えば、入力端子3Aが正論理のとき入力
端子1Aに5Vを加えると、出力端子3Bの電圧は5V
になるはずであるが、実際にはオフセット誤差とゲイン
誤差により出力端子3Bの電圧は4.98Vなどにな
り、入力端子3Aが負論理のとき入力端子2Aに−5V
を加えると、出力端子3Bの電圧は−5Vになるはずで
あるが、実際にはオフセット誤差とゲイン誤差により出
力端子3Bの電圧は−4.98Vなどになる。同様に、
入力端子3Aが正論理のとき入力端子1Aに0Vを加え
ると、出力端子3Bの電圧は0Vになるはずであるが、
実際には−0.02Vなどになり、入力端子3Aが負論
理のとき入力端子2Aに0Vを加えると、出力端子3B
の電圧は0Vになるはずであるが、実際には+0.02
Vなどになる。
For example, when 5 V is applied to the input terminal 1A when the input terminal 3A is positive logic, the voltage of the output terminal 3B becomes 5V.
However, in practice, the voltage of the output terminal 3B becomes 4.98 V or the like due to the offset error and the gain error. When the input terminal 3A is negative logic, -5V is applied to the input terminal 2A.
Is added, the voltage of the output terminal 3B should be -5V. However, the voltage of the output terminal 3B becomes -4.98V or the like due to an offset error and a gain error. Similarly,
When 0V is applied to the input terminal 1A when the input terminal 3A is in positive logic, the voltage of the output terminal 3B should be 0V.
Actually, it becomes -0.02 V, and when 0 V is applied to the input terminal 2A when the input terminal 3A has a negative logic, the output terminal 3B
Should be 0V, but actually +0.02
V and so on.

【0006】[0006]

【発明が解決しようとする課題】図2では、ドライバ3
の出力レベルを可変抵抗器31または可変抵抗器32で
補正するので、短時間では補正することができず、ゲイ
ン誤差は補正されていない。この発明は増幅器1と増幅
器2にそれぞれ帰還抵抗を接続し、帰還抵抗に補正電流
を流して増幅器1と増幅器2の出力電圧を補正すること
によりドライバ3の出力電圧を補正し、端子3Bの電圧
が入力端子1Aの電圧又は入力端子2Aの電圧になるよ
うにすることを目的とする。
In FIG. 2, the driver 3
Is corrected by the variable resistor 31 or the variable resistor 32, the correction cannot be performed in a short time, and the gain error is not corrected. According to the present invention, a feedback resistor is connected to each of the amplifiers 1 and 2, and a correction current is supplied to the feedback resistors to correct the output voltages of the amplifiers 1 and 2, thereby correcting the output voltage of the driver 3 and the voltage of the terminal 3B. Is the voltage of the input terminal 1A or the voltage of the input terminal 2A.

【0007】[0007]

【課題を解決するための手段】この目的を達成するため
に、この発明では、入力端子1Aに加えられた電圧を増
幅し、入力端子1Bと出力間に帰還抵抗11が接続され
る増幅器1と、入力端子2Aに加えられた電圧を増幅
し、入力端子2Bと出力間に帰還抵抗12が接続される
増幅器2と、増幅器1の出力が入力端子3Cに加えら
れ、増幅器2の出力が入力端子3Dに加えられ、入力端
子3Aに正論理が加えられたとき、入力端子3Cの電圧
が出力端子3Bに出力され、入力端子3Aに負論理が加
えられたとき、入力端子3Dの電圧が出力端子3Bに出
力されるドライバ3と、増幅器1の帰還抵抗11に流す
電流を制御し、増幅器1の出力電圧を制御する電流出力
型のD/A変換器6と、増幅器2の帰還抵抗12に流す
電流を制御し、増幅器2の出力電圧を制御する電流出力
型のD/A変換器7と、D/A変換器6の入力6A又は
D/A変換器7の入力7Aの設定を制御し、ドライバ3
の出力端子3Bの電圧を入力端子1Aの電圧又は入力端
子2Aの電圧と等しくする制御手段8と、オフセット誤
差補正時のD/A変換器6の入力6AとD/A変換器7
の入力7Aの最終設定値21と、ゲイン誤差補正時のの
D/A変換器6の入力6AとD/A変換器7の入力7A
の最終設定値22とを記憶する記憶装置9とを備える。
In order to achieve this object, according to the present invention, an amplifier 1 in which a voltage applied to an input terminal 1A is amplified and a feedback resistor 11 is connected between the input terminal 1B and an output is provided. , Amplifying the voltage applied to the input terminal 2A, the amplifier 2 having a feedback resistor 12 connected between the input terminal 2B and the output, the output of the amplifier 1 being applied to the input terminal 3C, and the output of the amplifier 2 being the input terminal. 3D, when the positive logic is applied to the input terminal 3A, the voltage of the input terminal 3C is output to the output terminal 3B, and when the negative logic is applied to the input terminal 3A, the voltage of the input terminal 3D is changed to the output terminal. 3B, a current output type D / A converter 6 for controlling the current flowing through the feedback resistor 11 of the amplifier 1 to control the current flowing through the feedback resistor 11 of the amplifier 1, and flowing through the feedback resistor 12 of the amplifier 2 Control the current and amplifier A D / A converter 7 of the current output type for controlling the output voltage of, controls the configuration of the input 7A of the input 6A or D / A converter 7 of the D / A converter 6, the driver 3
Control means 8 for making the voltage at the output terminal 3B equal to the voltage at the input terminal 1A or the voltage at the input terminal 2A, the input 6A of the D / A converter 6 at the time of offset error correction and the D / A converter 7
Of the input 7A, the input 6A of the D / A converter 6 and the input 7A of the D / A converter 7 when the gain error is corrected.
And a storage device 9 for storing the final set value 22 of the above.

【0008】[0008]

【作用】次に、この発明によるICテスタ用ドライバの
出力電圧補正回路の構成を図1により説明する。図1の
6と7は電流出力型のD/A変換器、8は制御手段、9
は記憶装置、11は増幅器1の出力と入力端子1B間に
接続される帰還抵抗、12は増幅器2の出力と入力端子
2B間に接続される帰還抵抗であり、その他は図2と同
じものである。
Next, the configuration of the output voltage correction circuit of the IC tester driver according to the present invention will be described with reference to FIG. In FIG. 1, 6 and 7 are current output type D / A converters, 8 is control means, 9
Is a storage device, 11 is a feedback resistor connected between the output of the amplifier 1 and the input terminal 1B, 12 is a feedback resistor connected between the output of the amplifier 2 and the input terminal 2B, and the others are the same as those in FIG. is there.

【0009】増幅器1の入力端子1Aに加えられた電圧
は、D/A変換器6の出力電流と帰還抵抗11の積の電
圧が加算されて、ドライバ3の入力端子3Cに加えら
れ、ドライバ3の入力3Aが正論理のとき出力端子3B
に出力される。制御手段8は、ドライバ3の出力端子3
Bをスイッチ4を通して電圧測定器5が測定した結果と
入力端子1Aに加えられた電圧とが等しくなるようにD
/A変換器6の入力6Aを変えながらD/A変換器6の
入力6Aの設定値を決め、補正をする。
The voltage applied to the input terminal 1A of the amplifier 1 is added to the voltage of the product of the output current of the D / A converter 6 and the feedback resistor 11, and is added to the input terminal 3C of the driver 3. Output terminal 3B when input 3A of
Is output to The control means 8 controls the output terminal 3 of the driver 3
B so that the voltage measured by the voltmeter 5 through the switch 4 is equal to the voltage applied to the input terminal 1A.
The set value of the input 6A of the D / A converter 6 is determined while changing the input 6A of the / A converter 6, and correction is performed.

【0010】次に、具体的な補正手順を説明する。第1
段階では、入力端子1Aに電圧を加え、入力6Aに初期
値を設定する。第2段階では、ドライバ出力端子3Bの
電圧を測定する。第3段階では、入力端子1Aと出力端
子3Bの電圧を比較し、等しくない場合には第4段階へ
と進み、入力端子1Aと出力端子3Bの電圧が等しくな
ったとき、補正が完了となる。第4段階では、入力6A
の現在の設定を増減し、入力6Aを再設定し、第3段階
へ戻す。
Next, a specific correction procedure will be described. First
In the stage, a voltage is applied to the input terminal 1A, and an initial value is set to the input 6A. In the second stage, the voltage of the driver output terminal 3B is measured. In the third stage, the voltages of the input terminal 1A and the output terminal 3B are compared. If they are not equal, the process proceeds to the fourth stage. When the voltages of the input terminal 1A and the output terminal 3B become equal, the correction is completed. . In the fourth stage, input 6A
Is increased or decreased, the input 6A is reset, and the process returns to the third stage.

【0011】入力端子1Aの電圧が0Vのときに最終的
に決められたD/A変換器6の入力6Aの設定値21
は、オフセット誤差補正時の設定値として記憶装置9に
記憶され、入力端子1Aの電圧が例えば5Vのときに最
終的決められたD/A変換器6の入力6Aの設定値22
はゲイン誤差補正時の設定値として記憶装置9に記憶さ
れる。
When the voltage at the input terminal 1A is 0 V, the final set value 21 of the input 6A of the D / A converter 6 is determined.
Is stored in the storage device 9 as a set value at the time of offset error correction, and the set value 22 of the input 6A of the D / A converter 6 which is finally determined when the voltage of the input terminal 1A is, for example, 5V
Is stored in the storage device 9 as a set value at the time of gain error correction.

【0012】次に、入力端子1Aに0〜5Vの範囲の電
圧が加えられたときの入力6Aの設定値23は、記憶装
置9のオフセット誤差補正時の設定値21とゲイン誤差
補正時の設定値22の2点の間を直線近似とみなして制
御手段8が演算することにより出力端子3Bの電圧を入
力端子1Aの電圧と同じにすることができる。入力端子
2A側も同様にして、ドライバ3の電圧を補正する。
Next, when a voltage in the range of 0 to 5 V is applied to the input terminal 1A, the set value 23 of the input 6A becomes the set value 21 for the offset error correction of the storage device 9 and the set value 21 for the gain error correction. The voltage at the output terminal 3B can be made the same as the voltage at the input terminal 1A by calculating the control unit 8 by regarding the two points of the value 22 as linear approximation. Similarly, the input terminal 2A corrects the voltage of the driver 3.

【0013】[0013]

【発明の効果】この発明によれば、2個の増幅器にそれ
ぞれ帰還抵抗を接続し、帰還抵抗に補正電流を流して2
個の増幅器の出力電圧を補正することによりドライバの
出力電圧を補正しているので、出力端子の電圧を入力端
子1Aの電圧又は入力端子2Aの電圧と同じににするこ
とができる。また、制御手段と記憶装置を使用している
ので、プログラマブルな出力電圧の設定のすべてについ
て補正をすることができる。
According to the present invention, a feedback resistor is connected to each of the two amplifiers, and a correction current is supplied to the feedback resistors.
Since the output voltage of the driver is corrected by correcting the output voltages of the amplifiers, the voltage of the output terminal can be made equal to the voltage of the input terminal 1A or the voltage of the input terminal 2A. Further, since the control means and the storage device are used, it is possible to correct all the settings of the programmable output voltage.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明によるICテスタ用ドライバの出力電
圧補正回路である。
FIG. 1 is an output voltage correction circuit of an IC tester driver according to the present invention.

【図2】従来技術によるICテスタ用ドライバの出力電
圧補正回路である。
FIG. 2 is an output voltage correction circuit of a conventional IC tester driver.

【符号の説明】[Explanation of symbols]

1 増幅器 2 増幅器 3 ドライバ 4 スイッチ 5 電圧測定器 6 D/A変換器 7 D/A変換器 8 制御手段 9 記憶装置 DESCRIPTION OF SYMBOLS 1 Amplifier 2 Amplifier 3 Driver 4 Switch 5 Voltage measuring device 6 D / A converter 7 D / A converter 8 Control means 9 Storage device

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の入力端子(1A)に加えられた電圧を
増幅し、第2の入力端子(1B)と出力間に帰還抵抗(11)が
接続される第1の増幅器(1) と、 第3の入力端子(2A)に加えられた電圧を増幅し、第4の
入力端子(2B)と出力間に帰還抵抗(12)が接続される第2
の増幅器(2) と、 第1の増幅器(1) の出力が第5の入力端子(3C)に加えら
れ、第2の増幅器(2)の出力が第6の入力端子(3D)に加
えられ、第7の入力端子(3A)に正論理が加えられたと
き、第5の入力端子(3C)の電圧が出力端子(3B)に出力さ
れ、第7の入力端子(3A)に負論理が加えられたとき、第
6の入力端子(3D)の電圧が出力端子(3B)に出力されるド
ライバ(3) と、 第1の増幅器(1) の帰還抵抗(11)に流す電流を制御し、
第1の増幅器(1) の出力電圧を制御する電流出力型の第
1のD/A変換器(6) と、 第2の増幅器(2) の帰還抵抗(12)に流す電流を制御し、
第2の増幅器(2) の出力電圧を制御する電流出力型の第
2のD/A変換器(7) と、 第1のD/A変換器(6) の入力(6A)又は第2のD/A変
換器(7) の入力(7A)の設定を制御し、ドライバ(3) の出
力端子(3B)の電圧を第1の入力端子(1A)の電圧又は第3
の入力端子(2A)の電圧と等しくする制御手段(8) とを備
えることを特徴とするICテスタ用ドライバの出力電圧
補正回路。
A first amplifier (1) which amplifies a voltage applied to a first input terminal (1A) and has a feedback resistor (11) connected between a second input terminal (1B) and an output. Amplifying the voltage applied to the third input terminal (2A), and connecting the feedback resistor (12) between the fourth input terminal (2B) and the output.
The output of the first amplifier (1) is applied to a fifth input terminal (3C), and the output of the second amplifier (2) is applied to a sixth input terminal (3D). When positive logic is applied to the seventh input terminal (3A), the voltage of the fifth input terminal (3C) is output to the output terminal (3B), and negative logic is applied to the seventh input terminal (3A). When the voltage is applied, the voltage of the sixth input terminal (3D) is output to the output terminal (3B), and the current flowing to the feedback resistor (11) of the first amplifier (1) is controlled. ,
A current output type first D / A converter (6) for controlling the output voltage of the first amplifier (1) and a current flowing to the feedback resistor (12) of the second amplifier (2);
A current output type second D / A converter (7) for controlling the output voltage of the second amplifier (2); and an input (6A) or a second input / output of the first D / A converter (6). The setting of the input (7A) of the D / A converter (7) is controlled, and the voltage of the output terminal (3B) of the driver (3) is changed to the voltage of the first input terminal (1A) or the third terminal.
A control means (8) for making the voltage equal to the voltage of the input terminal (2A) of the IC tester.
【請求項2】 第1の入力端子(1A)に加えられた電圧を
増幅し、第2の入力端子(1B)と出力間に帰還抵抗(11)が
接続される第1の増幅器(1) と、 第3の入力端子(2A)に加えられた電圧を増幅し、第4の
入力端子(2B)と出力間に帰還抵抗(12)が接続される第2
の増幅器(2) と、 第1の増幅器(1) の出力が第5の入力端子(3C)に加えら
れ、第2の増幅器(2)の出力が第6の入力端子(3D)に加
えられ、第7の入力端子(3A)に正論理が加えられたと
き、第5の入力端子(3C)の電圧が出力端子(3B)に出力さ
れ、第7の入力端子(3A)に負論理が加えられたとき、第
6の入力端子(3D)の電圧が出力端子(3B)に出力されるド
ライバ(3) と、 第1の増幅器(1) の帰還抵抗(11)に流す電流を制御し、
第1の増幅器(1) の出力電圧を制御する電流出力型の第
1のD/A変換器(6) と、 第2の増幅器(2) の帰還抵抗(12)に流す電流を制御し、
第2の増幅器(2) の出力電圧を制御する電流出力型の第
2のD/A変換器(7) と、 第1のD/A変換器(6) の入力(6A)又は第2のD/A変
換器(7) の入力(7A)の設定を制御し、ドライバ(3) の出
力端子(3B)の電圧を第1の入力端子(1A)の電圧又は第3
の入力端子(2A)の電圧と等しくする制御手段(8) と、 オフセット誤差補正時の第1のD/A変換器(6) の入力
(6A)と第2のD/A変換器(7) の入力(7A)の最終設定値
(21)と、ゲイン誤差補正時の第1のD/A変換器(6) の
入力(6A)と第2のD/A変換器(7) の入力(7A)の最終設
定値(22)とを記憶する記憶装置(9) とを備えることを特
徴とするICテスタ用ドライバの出力電圧補正回路。
2. A first amplifier (1) in which a voltage applied to a first input terminal (1A) is amplified, and a feedback resistor (11) is connected between the second input terminal (1B) and an output. Amplifying the voltage applied to the third input terminal (2A), and connecting the feedback resistor (12) between the fourth input terminal (2B) and the output.
The output of the first amplifier (1) is applied to a fifth input terminal (3C), and the output of the second amplifier (2) is applied to a sixth input terminal (3D). When positive logic is applied to the seventh input terminal (3A), the voltage of the fifth input terminal (3C) is output to the output terminal (3B), and negative logic is applied to the seventh input terminal (3A). When the voltage is applied, the voltage of the sixth input terminal (3D) is output to the output terminal (3B), and the current flowing to the feedback resistor (11) of the first amplifier (1) is controlled. ,
A current output type first D / A converter (6) for controlling the output voltage of the first amplifier (1) and a current flowing to the feedback resistor (12) of the second amplifier (2);
A current output type second D / A converter (7) for controlling the output voltage of the second amplifier (2); and an input (6A) or a second input / output of the first D / A converter (6). The setting of the input (7A) of the D / A converter (7) is controlled, and the voltage of the output terminal (3B) of the driver (3) is changed to the voltage of the first input terminal (1A) or the third terminal.
Control means (8) for making the voltage equal to the voltage at the input terminal (2A) of the first D / A converter (6) at the time of offset error correction
(6A) and the final setting value of the input (7A) of the second D / A converter (7)
(21), the final setting value (22) of the input (6A) of the first D / A converter (6) and the input (7A) of the second D / A converter (7) at the time of gain error correction An output voltage correction circuit for an IC tester driver, comprising: a storage device (9) for storing the following.
JP3235768A 1991-08-23 1991-08-23 Output voltage correction circuit for IC tester driver Expired - Fee Related JP2876844B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3235768A JP2876844B2 (en) 1991-08-23 1991-08-23 Output voltage correction circuit for IC tester driver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3235768A JP2876844B2 (en) 1991-08-23 1991-08-23 Output voltage correction circuit for IC tester driver

Publications (2)

Publication Number Publication Date
JPH0552908A JPH0552908A (en) 1993-03-02
JP2876844B2 true JP2876844B2 (en) 1999-03-31

Family

ID=16990954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3235768A Expired - Fee Related JP2876844B2 (en) 1991-08-23 1991-08-23 Output voltage correction circuit for IC tester driver

Country Status (1)

Country Link
JP (1) JP2876844B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3435077B2 (en) 1998-09-16 2003-08-11 株式会社鷺宮製作所 Bellows pressure operated valve

Also Published As

Publication number Publication date
JPH0552908A (en) 1993-03-02

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