JP2874816B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a nitride film is formed as an interlayer insulating film between conductive layers.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device in which a nitride film is formed between conductive layers, for example, a nonvolatile RAM cell (A), and a transistor used in a peripheral circuit, for example, a medium-voltage transistor ( The following method is used to form B) and the 5V transistor (C).

As shown in FIG. 5A, an N ^- well is formed in a portion where a PMOS type medium voltage transistor and a 5V transistor are formed, and then an element isolation region 2 is formed on a silicon substrate 1. By forming the non-volatile RA
Active regions for forming M, medium voltage transistors, and 5V transistors are secured. Then, a resist 3a is applied on the silicon substrate 1 by a photolithography process, and ions are implanted into a portion to be the impurity diffusion layer 4 of the nonvolatile RAM memory cell.

Then, as shown in FIG. 5B, annealing is performed at about 900 ° C. for about 20 minutes to form an impurity diffusion layer 4 of the nonvolatile RAM memory cell, and a gate is formed on the entire surface of the silicon substrate 1. An SiO ₂ film 5 as an oxide film is formed. Then, a part of the SiO ₂ film 5 on the impurity diffusion layer 4 is removed by etching by applying a resist 3b by a photolithography process.

Then, as shown in FIG. 5C, after the resist 3b is peeled off, an SiO ₂ film 5a as a tunnel oxide film is formed again on the portion of the SiO ₂ film 5 which has been etched away. Then, a first polysilicon is deposited on the SiO ₂ films 5 and 5a, and is doped with phosphorus as an N ⁺ -type impurity, and then the first polysilicon is patterned into a desired pattern by a photolithography process using a resist 3c. To form gate electrodes 6a to 6e.

After the resist 3c is peeled off, FIG.
As shown in the figure, the N ⁻ well of the medium-breakdown-voltage transistor and the 5V-system transistor are masked by a photolithography process using the resist 3d, and in the non-volatile RAM cell, the gate electrodes 6a to 6c are used as a mask. Phosphorous at 60 keV, 1 × 10 ¹³ /
Implantation is performed at a concentration of cm ² to form impurity diffusion layers 4 respectively.

After removing the resist 3d again, FIG.
As shown in (e), the gate electrodes 6a to 6e are formed.
Is oxidized to form a film on each of the gate electrodes 6a to 6e.
SiO _TwoA film 7 is formed, and SiO_TwoS on film 7
An iN film 8 is deposited. Next, the resist 3e and the used photoresist are used.
The non-volatile RAM is formed by the photolithography process.
Masking only the region to be
The SiN film 8 is formed only in the region where the V-type transistor is formed.
After the etching removal, the resist 3e is peeled off.

Then, as shown in FIG. 6 (f), an SiO ₂ film is deposited on the entire surface of the silicon substrate 1 on which the gate electrodes 6a to 6e, the SiO ₂ film 7, the SiN film 8 and the like are formed, and is dry-etched. Then, sidewalls 9 are formed on the gate electrodes 6a to 6e by HF cleaning, respectively, and a SiO ₂ film (not shown) is formed on the gate electrodes 6a to 6e by thermal oxidation. Next, a contact hole 10 reaching the silicon substrate 1 is formed on the impurity diffusion layer 4 between the gate electrode 6b and the gate electrode 6c of the nonvolatile RAM cell by a photolithography process using the resist 3f.

Further, as shown in FIG. 7 (g), after depositing a second polysilicon on the entire surface of the silicon substrate 1, doping with phosphorus which is an N ⁺ -type impurity, a resist 3g is used. The second polysilicon is etched into a desired pattern by a photolithography process to form the lower electrode 11 of the capacitor. Then
As shown in FIG. 7H, boron ions are implanted into the N ^- well of the 5V transistor by a photolithography process using a resist 3h.

Further, as shown in FIG. 7I, boron ions are further implanted into other regions of the 5V transistor by a photolithography process using a resist 3i. Then, after removing the resist 3i, FIG.
As shown in (j), the SiO ₂ film 12 is formed as a capacitor insulating film on the lower electrode 11 by oxidizing the second polysilicon which is the lower electrode 11 of the capacitor. The SiN film 13 is deposited. Next, by a photolithography process using the resist 3j, the SiN film 13 other than on the non-volatile RAM cell is removed by etching.

Further, as shown in FIG. 8 (k), the SiO ₂ film 5 on the 5V transistor is etched away by a photolithography process, and a SiO ₂ film 16 is formed as a gate oxide film. Then, FIG.
As shown in (l), a third surface is formed on the entire surface of the silicon substrate 1.
After the polysilicon 14 is deposited, after doping with phosphorus which is an N ⁺ -type impurity, a WSi 15 is laminated and patterned into a desired shape, and the upper electrode of the capacitor and the gate electrodes 6f and 6g of the 5V transistor are respectively formed. Form.

[0012]

In the above method for manufacturing a semiconductor device, the gate electrode 6a is formed on the silicon substrate 1.
~ 6e, and then an SiO ₂ film 7 as an interlayer insulating film
And a SiN film 8 are laminated. Then, the Si other than the region where the capacitor lower electrode 11 as the second conductive layer is formed is formed.
After the N film 8 is removed by etching in a photolithography process using the resist 3, polysilicon is laminated and etched into a desired pattern to form the capacitor lower electrode 11.

However, the resist 3 used in these steps must be removed with a sulfuric acid boiler each time. When a SiN film is formed on the silicon substrate 1, the SiN film is formed with a sulfuric acid boiler. Since the film is reduced, there has been a problem that, after the formation of the SiN film, these steps must be reduced as much as possible. SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and has as its object to provide a method of manufacturing a semiconductor device capable of suppressing a decrease in a nitride film formed as an interlayer insulating film.

[0014]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a nonvolatile RAM cell region having a capacitor and a peripheral circuit region having a MOS transistor. Forming a gate electrode of the nonvolatile RAM and a gate electrode of the MOS transistor at the same time by patterning a first conductive layer formed on a semiconductor substrate via an insulating film; Sequentially stacking a second conductive layer, patterning the second conductive layer, and patterning the lower electrode of the capacitor of the nonvolatile RAM simultaneously with the patterned second conductive layer as a mask; And a step of etching the semiconductor device.

In the method of manufacturing a semiconductor device according to the present invention, a semiconductor substrate having an electrode formed of a first conductive layer is used. As the semiconductor substrate, those usually used as a substrate can be used, but a silicon substrate is preferable. Further, as the first conductive layer, polysilicon or silicide such as W or Ti, which is usually used as the conductive layer, or polycide can be used.
When using polysilicon, a known method, for example,
It is preferable to stack by the CVD method or the like so as to have a thickness usually used as an electrode. Further, the method of patterning the polysilicon into a desired shape can be performed by a known etching method.

Further, at least a SiN film is formed as an interlayer insulating film formed in the present invention.
A laminated structure such as a ₂ / SiN film may be used. At this time, it is preferable to stack the SiN film by a known method, for example, a CVD method or the like so as to have a film thickness usually used as an insulating film. Further, the second conductive layer laminated on the nitride film as the interlayer insulating film is not particularly limited, and is usually polysilicon or a silicide such as W or Ti, or polycide used as the conductive layer. Can be used. When the second conductive layer is patterned into a desired shape, the nitride film is simultaneously etched. The method can be performed by a known etching method.

[0017]

According to the method described above, the first conductive layer formed on the semiconductor substrate via the insulating film is patterned to form the gate electrode of the nonvolatile RAM and the M layer.
Simultaneously forming a gate electrode of an OS transistor, sequentially laminating a nitride film and a second conductive layer on the entire surface, and patterning the second conductive layer to form the nonvolatile R
Etching the nitride film using the patterned second conductive layer as a mask at the same time as patterning the capacitor lower electrode of the AM, so that the first conductive layer is patterned, and the nitride film is an interlayer insulating film. Patterning and patterning of the second conductive layer need not be performed, respectively, and the removal of the unnecessary portion of the nitride film is performed simultaneously with the patterning of the second conductive layer. And the number of HF clean steps is reduced by one.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a conventional semiconductor device in which a nonvolatile RAM cell, a medium voltage transistor and a 5V transistor are formed will be described with reference to the drawings. As shown in FIG. 1A, an N ^- well is formed at a portion where a PMOS type medium voltage transistor and a 5V transistor are formed.
Next, a non-volatile RAM (A) having a capacitor is formed by forming an element isolation region 2 on a silicon substrate 1,
Active regions for forming the medium voltage transistor (B) and the 5V transistor (C) are secured.
Then, a resist 3a is applied on the silicon substrate 1 by a photolithography process, and, for example, P and As are formed on a portion to be the impurity diffusion layer 4 of the nonvolatile RAM memory cell.
Is ion-implanted.

Next, as shown in FIG. 1 (b), in order to form the impurity diffusion layer 4 of the nonvolatile RAM memory cell having the capacitor, at about 900 ° C. in a nitrogen gas atmosphere.
For about 400 to 500 minutes. Next, an SiO ₂ film 5 as a gate oxide film is formed on the entire surface of the silicon substrate 1 at about 300 to 400 °. Then, the impurity diffusion layer 4
A part of the upper SiO ₂ film 5 is removed by etching using a resist 3b by a photolithography process.

[0020] Then, after removing the resist 3b, as shown in FIG. 1 (c), again to form a SiO ₂ film 5a is a tunnel oxide film on the etched portions of the SiO ₂ film 5. Then, a first polysilicon is deposited on these SiO ₂ films 5 and 5a to a thickness of about 3000 °,
After doping with phosphorus, which is an N ⁺ -type impurity, the first polysilicon is etched into a desired pattern using a resist 3c by a photolithography process to form gate electrodes 6a to 6e.

After the resist 3c is peeled off, FIG.
As shown in the above, the photolithography process
N of breakdown voltage transistor^-Well and 5V transistor
And a gate electrode in a nonvolatile RAM cell.
6a, 6b, and 6c as masks, for example, a silicon-based
Phosphorous at 60 keV, 1 × 10¹³ions / cm ^Two
To form impurity diffusion layers 4 respectively.

After removing the resist 3d again, FIG.
As shown in (e), the polysilicon forming the gate electrodes 6a to 6e is oxidized, and the respective gate electrodes 6a to 6e are oxidized.
e, a SiO ₂ film 7 having a thickness of about 100 ° is formed, and a SiN film 8 having a thickness of about 200 ° is deposited on the SiO ₂ film 7. Then, as shown in FIG. 2F, these gate electrodes 6a to 6e, SiO ₂ film 7, SiN film 8
An SiO ₂ film having a thickness of about 300 ° is deposited on the entire surface of the silicon substrate 1 on which the gate electrodes 6a to 6e are formed by dry etching and HF cleaning. Further, the gate electrode 6a is thermally oxidized.
An SiO ₂ film (not shown) of about 10 to 30 ° is deposited on SiN of up to 6 e. Next, the silicon substrate 1 is formed on the impurity diffusion layer 4 between the gate electrode 6b and the gate electrode 6c of the nonvolatile RAM cell by a photolithography process.
Is formed.

Further, as shown in FIG. 3 (g), a second film having a thickness of about 2500 ° is formed on the entire surface of the silicon substrate 1.
After the polysilicon is deposited, the N ⁺ -type impurity is doped with phosphorus, and then the second polysilicon is etched into a desired pattern using a resist 3f by a photolithography process to form the capacitor lower electrode 11. I do. Simultaneously with the patterning of the second polysilicon, the SiN film 8 laminated other than the portion masked by the resist 3f is removed by etching.

Next, as shown in FIG. 3 (h), 5 V
Boron ions in the N ^- well of
Inject keV and about 1 × 10 ¹² ions / cm ² . Further, as shown in FIG. 3I, boron ions are similarly implanted into other regions of the 5V transistor using a resist 3h by a photolithography process.

After the resist 3h is removed, the second polysilicon forming the capacitor lower electrode 11 is oxidized to form a capacitor insulating film on the capacitor lower electrode 11 as shown in FIG. As film thickness 1
A SiO ₂ film 12 of about 00 ° is formed.
A SiN film 13 having a thickness of about 140 ° is deposited on the _second film 12. Next, the SiN film 1 other than on the non-volatile RAM cell is formed by a photolithography process using the resist 3i.
3 is removed by etching.

Further, as shown in FIG. 8 (k), the SiO ₂ film 5 on the 5V transistor is removed by etching by a photolithography process, and a SiO ₂ film 16 having a thickness of about 170 ° is formed as a gate oxide film. To form Next, as shown in FIG. 8 (l), after a third polysilicon 14 is deposited on the entire surface of the silicon substrate 1 at about 1500 °, phosphorus as an N ⁺ -type impurity is implanted, and WS
i15 is stacked at about 2500 ° and patterned into a desired shape to form a capacitor upper electrode and gate electrodes 6f and 6g of a 5V transistor, respectively.

In such a method of manufacturing a semiconductor device, the gate electrodes 6 a to 6 formed on the silicon substrate 1 are formed.
After the SiN film 8 is formed on e, polysilicon is further laminated, and the capacitor lower electrode 11 is patterned. At this time, the SiN film 8 is simultaneously etched to form the gate electrodes 6a, 6a formed on the nonvolatile RAM.
An SiN film 8 is formed only on b as an interlayer insulating film.
Therefore, the number of steps of patterning the SiN film 8 into a desired shape by using a resist as a mask is reduced by one time, and the number of steps of boiling sulfuric acid for removing the resist can be reduced by one time. The reduction in the thickness of the SiN film 8 due to the clean process can be suppressed.

[0028]

According to the present invention, by patterning a first conductive layer formed on a semiconductor substrate via an insulating film, the gate electrode of the nonvolatile RAM and the M
Simultaneously forming a gate electrode of an OS transistor, sequentially laminating a nitride film and a second conductive layer on the entire surface, and patterning the second conductive layer to form the nonvolatile R
Etching the nitride film using the patterned second conductive layer as a mask at the same time as patterning the capacitor lower electrode of the AM, so that the first conductive layer is patterned, and the nitride film is an interlayer insulating film. It is not necessary to perform patterning of the second conductive layer and patterning of the second conductive layer, and the unnecessary portion of the nitride film can be removed simultaneously with the patterning of the second conductive layer. Therefore, the number of times of the sulfuric acid boil process for removing the resist used for patterning can be reduced by one, and the manufacturing process can be simplified, and the thickness of the nitride film can be suppressed. Therefore, a highly reliable semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a conventional method for manufacturing a semiconductor device.

FIG. 7 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a conventional method for manufacturing a semiconductor device.

FIG. 8 is a schematic cross-sectional view of a main part showing a manufacturing process for describing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate (semiconductor substrate) 6a to 6e gate electrode (first conductive layer) 8 SiN film (nitride film) 11 capacitor lower electrode (second conductive layer)

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/105 H01L 27/108 H01L 21/8242 H01L 27/04 H01L 21/822

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a nonvolatile RAM cell region having a capacitor and a peripheral circuit region having a MOS transistor, comprising: forming a first conductive layer formed on a semiconductor substrate via an insulating film; Forming a gate electrode of the nonvolatile RAM and a gate electrode of the MOS transistor simultaneously by patterning; sequentially stacking a nitride film and a second conductive layer on the entire surface; Patterning the non-volatile RAM
Etching the nitride film using the patterned second conductive layer as a mask at the same time as patterning the capacitor lower electrode.