JP2874096B2 - Exposure data generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding an exposure data generation method, it is possible to suppress an increase in processing time of chip exposure data when a part of functional blocks are replaced,
An object of the present invention is to provide an exposure data generation method that also improves compatibility, lays out exposure data of a plurality of functional blocks in a rectangular area corresponding to an exposure plane of an exposure target chip, and generates exposure data of one chip. A data extraction region is provided around the exposure data of the functional block, which is a layout unit that can be replaced in the exposure data generation method, and the data extracted by the data extraction region is used as reference data, and the proximity effect is provided for each of the functional blocks. It is configured to perform correction.

[Industrial applications]

The present invention relates to an exposure data generation method, and particularly to an exposure data generation method when a large-scale integrated circuit is configured by combining a plurality of functional blocks (cells).

In recent years, large-scale integrated circuits, especially ASICs (application-specific I
Building block approach has been adopted in the design of C).

[Conventional technology]

The building blocks are selected from among various types of functional blocks (for example, CPU blocks, RAM blocks, ROM blocks, etc.) that are preliminarily made into libraries, and are appropriately laid out to obtain a desired large-scale integrated circuit. It has the feature of high circuit design productivity.

The information on the function blocks extracted from the library is given in the form of exposure data. Then, the exposure data of one chip is created by combining the exposure data of each functional block.

[Problems to be solved by the invention]

However, in such a conventional exposure data generation method, for example, when replacing some of the functional blocks, it is necessary to recreate all of the chip exposure data. For this reason, a great deal of processing time is required for reconstructing the chip exposure data, which causes problems such as an increase in manufacturing cost and a long delivery time. Further, it is necessary to match the rules (pattern rules) of the exposure data of each functional block, and there is a problem that compatibility is lacking.

The present invention has been made in view of such a problem, and when a part of functional blocks are replaced, it is possible to suppress an increase in processing time of chip exposure data and to improve exposure data with improved compatibility. It aims to provide a generation method.

[Means for solving the problem]

In order to achieve the above object, an exposure data generation method according to the present invention lays out exposure data of a plurality of functional blocks in a rectangular area corresponding to an exposure plane of a chip to be exposed, and generates exposure data of one chip. In the exposure data generation method, a data extraction region is provided around exposure data of the functional block, which is a replaceable layout unit, and data extracted by the data extraction region is used as reference data, and a proximity effect is generated for each of the functional blocks. It is configured to perform correction.

[Action]

According to the present invention, when one functional block, which is a layout unit such as a CPU block, a RAM block, and a ROM block, is replaced, a part of the exposure data of another functional block adjacent to this functional block, that is, extracted by a data extraction area. Using the obtained data, the proximity effect correction is performed on the exposure data of the one functional block.

Therefore, it is not necessary to re-create the exposure data of the entire chip, so that an increase in data processing time can be suppressed.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 9 show an embodiment of the exposure data generating method according to the present invention.

FIG. 1 is a schematic diagram of a chip exposure data generation process using a building-dig block format technique.

In this figure, reference numeral 1 denotes a library unit, and the library unit 1 performs exposure data generation processing 2I to 2X on design data of functional blocks (for example, CPU, memory, I / O... Exposure data I to X are stored in data holding devices 3I to 3X.

2 (a) to 2 (e) are views showing examples of the exposure data I to X, wherein a solid line indicates a field line which defines a field area of the exposure data, and a broken line indicates a subfield constituting the field area. A subfield line that defines an area is shown. The hatched area indicates a pattern group (eg, CPU, memory, I / O) of each functional block.
/ O etc.). That is, the exposure data of each functional block is composed of a plurality of subfield areas. In this embodiment, it is not necessary to unify the field size and the subfield size of each exposure data in the library. That is, it is not necessary to unify the respective exposure data pattern rules.

Referring again to FIG. 1, reference numeral 2 denotes a chip exposure data generation processing unit. The chip exposure data generation processing unit 2 appropriately combines various types of functional blocks in a library to obtain chip exposure data of a desired large-scale integrated circuit device. The processing steps are roughly divided into rectangular area setting processing P ₁ , layout processing P ₂ , data extraction area setting processing and correction processing P ₃ , pattern data rearrangement and compression processing P ₄ , and the like. Includes processing.

 Hereinafter, each process will be described.

P ₁ is a process for setting a rectangular area corresponding to the exposure plane of the chip to be exposed. That is, the chip to be exposed is a chip serving as a base of a large-scale integrated circuit device based on specification requirements, and the exposure plane is a functional block arrangement area (also referred to as an internal area) of the chip. FIG. 3 shows a chip to be exposed. Reference numeral 4 denotes a peripheral portion of the chip (a portion where an I / O buffer and input / output pads are formed), and reference numeral 5 denotes an internal area.
The internal area 5 corresponds to the rectangular area. In this process, the exposure data of the peripheral portion 4 and the internal region 5 (however, there is no internal pattern data at this stage) are created.

The exposure data of each functional block extracted from P ₂ library, in a rectangular area set by P ₁ (inner region 5) is a process of laying. The layout is performed by designating an arrangement reference point and an arrangement frame size for each functional block in the internal area 5. FIG. 4 is a diagram showing an example in which arrangement reference points (a) to (e) and the size of an arrangement frame (shown by a broken line) are designated. In this example, each functional block corresponds to FIGS. 2 (a) to 2 (e).

FIG. 5 is a diagram showing a situation in the internal area 5 where the layout has been completed in accordance with the designation of the arrangement reference point and the arrangement frame.

P _{3 In} this process, roughly two processes are performed. One of them is a data extraction area setting process _P3a , and the other is a correction process _P3b .

(P _3a ) In a process of setting a data extraction region of a predetermined width for data extraction around each laid out functional block, for example, when attention is paid to a functional block D in FIG. , A data extraction area Da having a predetermined width L is provided. FIG. 7 is an enlarged view of a portion F in FIG. The predetermined width L of the data extraction area Da is
Determined in consideration of the magnitude of the proximity effect. That is, in general, when a proximity pattern is drawn on a chip using a charged particle beam, the pattern actually drawn is slightly enlarged due to forward scattering in the resist and back scattering on the substrate surface (proximity effect). ). The predetermined width L is a range in which the proximity effect spreads (in other words, the magnitude of the proximity effect).
Should be determined in consideration of the above. For example, it is preferable to set L to about 3 to 5 μm. Of course, this value differs depending on the type of the exposure apparatus.

(P _3b ) The correction process is a process including a so-called proximity effect correction for appropriately reducing the size of the pattern or increasing or decreasing the irradiation amount in consideration of the distance between the adjacent patterns and the like. When performing the above-described correction for one functional block, the partial data (data in the data extraction area) of another functional block adjacent to the functional block extracted by the data extraction area is corrected reference data, That is, it is included in data such as other pattern dimensions close to the pattern to be referred to when determining the dimension of the correction target pattern. Thus, the pattern correction of the peripheral portion of the functional block during the correction process can be performed by the proximity correction also by the pattern of the peripheral portion of another adjacent functional block.

P _{4 In} this process, the pattern data in one functional block is rearranged or compressed. This is because the proximity effect correction of the pattern in the peripheral portion of one functional block requires that the other patterns in the block need to be similarly corrected.

When the above processes P _{1 to} P ₄ are completed, corrected exposure data of one functional block is obtained. When P ₃ and P ₄ are repeatedly executed by the number of functional blocks,
Exposure data for the entire chip is completed.

As described above, in the present embodiment, one data extraction area is provided around a functional block, which is a layout unit such as a CPU block, a RAM block, and a ROM block, and data in this data extraction area (that is, other adjacent functions) are provided. Block data) is used as reference data for proximity effect correction. Therefore, when some functional blocks are replaced, only the exposure data in that block needs to be corrected. An increase in the time required for the entire exposure data generation process can be suppressed. Also, for each functional block in the library, there is no need to match the field size and subfield size of the exposure data,
Various pattern rule function blocks can be used, and compatibility can be improved.

FIG. 8 is an example in which functional blocks 1 to 3 are laid out without gaps in all the internal regions of the chip. Also in the case of this layout, a data extraction area is set around each functional block. FIG. 9 is a diagram showing a data extraction area a of a predetermined width L set around one functional block as a representative. That is, in this layout example, for example, when a functional block is modified or revised, the functional blocks adjacent to the functional block,.
,... Are extracted by the data extraction area a, and the proximity effect correction is performed on the pattern data of the peripheral portion of the functional block using the extracted data. Therefore, since it is only necessary to correct the data of one functional block (in this case), it is not necessary to recreate the exposure data of the entire chip, and it is possible to suppress an increase in data processing time. Further, as shown by the broken line in FIG. 9, the subfield size (and, of course, the field size) of each functional block may be different.
Compatibility with functional blocks of various sizes can also be improved.

〔The invention's effect〕

According to the present invention, it is necessary to recreate all of the chip exposure data in the case of replacing, correcting, and revising some functional blocks from a plurality of functional blocks, which are layout units such as a CPU block, a RAM block, and a ROM block. Therefore, it is possible to suppress an increase in exposure data generation processing time. In addition, the field size and the subfield size of each functional block do not need to be matched, so that compatibility can be improved.

[Brief description of the drawings]

1 to 9 are diagrams showing an embodiment of an exposure data generating method according to the present invention. FIG. 1 is a schematic diagram of the whole process, and FIGS. FIG. 3 is a diagram showing the rectangular region, FIG. 4 is a diagram showing an arrangement reference and an arrangement frame specified in the rectangular region, FIG. 5 is a diagram showing functional blocks laid out in the rectangular region, FIG. 6 is a diagram showing a data extraction area around one of the functional blocks, FIG. 7 is an enlarged view of a portion F in FIG. 6, FIG. 8 is a diagram in which the functional blocks are laid out without gaps, FIG. FIG. 4 is a diagram showing a data extraction area around one of the functional blocks. 5 ... internal area (rectangular area), Ea, a ... data extraction area.

Claims (1)

(57) [Claims] 1. An exposure data generating method for laying out exposure data of a plurality of functional blocks in a rectangular area corresponding to an exposure plane of a chip to be exposed and generating exposure data of one chip. A method for generating exposure data, comprising: providing a data extraction area around exposure data of a certain functional block; and using the data extracted by the data extraction area as reference data to perform proximity effect correction for each of the functional blocks. .