JP2937221B2 - Circuit partitioning method for parallel circuit simulation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit partitioning method for parallel circuit simulation used for designing an electronic circuit of a large-scale LSI, and more particularly to a circuit partitioning method for increasing the parallelism of parallel circuit simulation and shortening the simulation time. .

[0002]

2. Description of the Related Art As a conventional circuit dividing technique for parallel circuit simulation, for example, Japanese Patent Application No. 63-23921 is disclosed.
As described in the specification attached to No. 8, while retaining the circuit having the hierarchical structure in the original hierarchical structure, the nest disassembly method and the like are used from the subgroup referred to by the top parent circuit, The division process of dividing into two is applied to the one having the largest simulation prediction time from the partial circuit group, and the number of generated partial circuit groups reaches the number of processors in the parallel simulation, or the parallel simulation processing prediction time It was to be repeated until it was saturated.

[0003] As a conventional technique for dividing a circuit in a parallel circuit simulation, a hierarchical level is arranged in one layer regardless of the original circuit structure, a structure of a parent circuit and a partial circuit referred to by the parent circuit is formed, and initial clustering and hierarchical clustering are performed. ,
The process of dividing a partial circuit into two using level-based cluster exchange was repeated until the number of partial circuits reached the number of processors.

[0004]

However, in the circuit dividing technique of the first conventional parallel circuit simulation described above, in the case of a circuit having a hierarchical structure, the circuit is divided while maintaining the hierarchical structure. Therefore, for nodes that span multiple partial circuits, that is, nodes in the parent circuit, the nodes that span between the partial circuits of the original circuit are preserved as they are, and further division creates a new shared node, As a result, the number of nodes in the parent circuit may increase.

In the above-described second conventional circuit dividing technique of the parallel circuit simulation, all the partial circuits are referred to by one parent circuit. The number of nodes extending between them, that is, the number of nodes of the parent circuit becomes large.

Therefore, in the conventional parallel circuit simulation, after the calculation by the parallel processing of the partial circuits allocated to each processor, the calculation of the parent circuit referring to the partial circuit is performed by one processor, so that the nodes of the parent circuit are calculated. The high score has a serious problem that the time of non-parallel processing in the parallel simulation occupies a large proportion, impairs the overall parallelism, and prevents the simulation time from being shortened by the parallel simulation.

It is an object of the present invention to provide a circuit division method for parallel circuit simulation in which the simulation time is reduced in view of the above-mentioned drawbacks.

[0008]

According to the present invention SUMMARY OF], it divides the original circuit structure to the structure of the newly parent circuit and partial circuit, before
The partial circuit so that the parent circuit refers to the partial circuit.
Means for aligning the hierarchy of the
A large partial circuit is divided, and the partial circuit
Means for repeatedly dividing until the number of
The number of subcircuits referenced by the circuit reaches a predetermined number.
A new circuit between the parent circuit and the plurality of partial circuits.
In addition, a means for creating an intermediate parent circuit for hierarchical
During the simulation, each of the plurality of partial circuits
And the intermediate parent circuit.
And assigning one parent circuit to each processor.
And a parallel circuit simulation circuit division method characterized by having stages .

Further, according to the present invention, in the circuit division method of the parallel simulation, the uppermost parent circuit refers to an intermediate parent circuit below the uppermost parent circuit, and the intermediate parent circuit refers to an intermediate parent circuit thereunder. Alternatively, a circuit division method for a parallel circuit simulation having a hierarchical structure referring to partial circuits can be obtained.

That is, in the circuit division method of the parallel circuit simulation according to the present invention, the hierarchy levels are aligned to one hierarchy. In a flat circuit having no hierarchical structure, a power supply element is raised to a parent circuit, and other elements form one partial circuit. In a circuit having a hierarchical structure, the layers are raised and aligned so as to be referenced by one parent circuit while preserving the lowest level partial circuit. In addition, the circuit division method of the parallel circuit simulation of the present invention repeatedly divides the largest existing partial circuit into two parts, and when the number of partial circuits referred to by the parent circuit reaches a certain number, a new division is performed by the next division. With reference to the two created partial circuits, a new intermediate parent circuit referenced from the conventional parent circuit is created. Thereafter, the processing is performed until the number of intermediate parent circuits becomes constant for each division. Further, the partial circuit is divided, and when the number of referring to the child circuits in the intermediate parent circuit reaches a certain number, a new intermediate parent circuit is similarly created in the next division, and the process is repeated. As a result, the highest-level parent circuit refers to the intermediate parent circuit below it, the intermediate parent circuit refers to the intermediate parent circuit or child circuit therebelow, and the partial circuit at the highest level, the so-called child circuit, includes transistors and resistors. A divided circuit having a hierarchical structure composed of elements such as the above is generated. At the time of the parallel simulation, one child circuit corresponding to the number of processors is provided for each processor, and one parent circuit is also provided for each processor, and the simulation is performed.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the flow of processing of a circuit division method of a parallel circuit simulation as one embodiment of the present invention.

First, in the pre-processing 2, of the data of the circuit diagram data input 1, for a flat circuit having no hierarchical structure, the power supply element is raised to the parent circuit, and the other elements form one partial circuit. In a circuit having a hierarchical structure, one partial circuit is formed by a plurality of partial circuits at the lowest level, and the hierarchy is raised so as to be sandwiched by one parent circuit, and one layer is formed to align the layers. Here, a circuit portion other than the created parent circuit is referred to as a child circuit.

Next, in update processing 3, the largest child circuit among the existing child circuits is selected and set as a division target. The child circuit selected in the update processing 3 performs two divisions in the division processing 4. The two circuits created by the division processing 4 are newly set as child circuits.

If the number of child circuits referred to by the parent circuit that refers to the newly created child circuit in the hierarchical processing 5 becomes larger than a certain number, two newly created child circuits are created. An intermediate parent circuit that refers only to the circuit is created, and the intermediate parent circuit is hierarchized so that the conventional parent circuit refers to the intermediate parent circuit.

In the termination determination processing 6, if the number of child circuits is equal to the number of processors, each of the child circuits is regarded as a partial circuit, which is referred to by a parent circuit or an intermediate parent circuit,
The result output 7 is performed in such a manner that the number of circuits referred to in the parent circuit is within a certain number. In other cases, the process returns to the update process 3 to continue the division.

FIG. 2 is a diagram showing division and hierarchization of the circuit division system of the present invention. In particular, the number of processors is four,
The number of circuits referred to by the parent circuit is two. First, a child circuit S2 including all elements such as transistors referred to by the parent circuits S1 and S1 is formed by preprocessing. This child circuit S
2 is divided into two to form child circuits S4 and S5.

At this time, the parent circuit S3 is
4 and S5, the node that affects the simulation time of the parent circuit S3 is a common node of the child circuits S4 and S5.
The large child circuit S4 of the two child circuits S4 and S5 is divided to create child circuits S7 and S8. Thereby, the parent circuit S6
Will refer to the three child circuits S7, S8, S9, so that an intermediate parent circuit S11 is newly created, and the child circuits S12, S12,
With reference to S13, it is made to be referred to by the parent circuit S10.

The intermediate parent circuit S11 includes child circuits S12 and S1.
3 and the child circuits S12 and S13 have an external node that is shared with the child circuit S14 and is also a node in the parent circuit S10. The simulation time of the intermediate parent circuit S11 is greatly affected by the number of nodes shared by the child circuits S12 and S13. In this way, the child circuit S14 is also divided,
Layering is performed, and an intermediate parent circuit S19 and child circuits S20, S2
Make one. As a result, the number of child circuits reaches four, the number of processors, and the process is terminated.

FIG. 3 shows an example of a system configuration of a parallel circuit simulation including the processing flow of the circuit division system of FIG. First, in the EWS 8, a circuit diagram input 11 is performed, and circuit connection data 12 is created. Next, circuit connection data 1
2, the controller 9 uses the circuit division 13, that is, the circuit division method of the parallel circuit simulation of the present invention, and performs the processing of FIG. 1 to generate the circuit division file 14. In the parallel circuit simulator 10, parallel compilation 15 is performed, object data is created, the object data is subjected to parallel circuit simulation 16, and a result file 17 is output to the controller 9. Finally EWS the result file 17
8 and display 18.

Next, as a second embodiment, an example in which the circuit division method of the parallel circuit simulation of the present invention is applied to an actual circuit having 6974 transistors will be described.

FIG. 4 shows a circuit structure as a result of actually applying the circuit dividing method. The division was performed with the number of processors being eight and the circuit referenced by the parent circuit being up to two. Eight child circuits 26 to 33 in the fourth layer,
Four intermediate parent circuits 22 to 25 in the hierarchy and two intermediate parent circuits 2 in the second hierarchy referring to two intermediate parent circuits in the third hierarchy at a time.
0, 21, and the first reference to the intermediate parent circuit of the second hierarchy
It takes the form of a parent circuit 19 in the hierarchy.

In the parallel circuit simulation, one child circuit 26 to 33 is assigned to each processor, and one intermediate parent circuit 20 to 25 and one parent circuit 19 are assigned to each processor. The flow of the simulation is as follows. First, the child circuits are processed in parallel, and after the processing of the two referenced child circuits is completed, the intermediate parent circuit of the third hierarchy performs the processing. Further, the process of the intermediate parent circuit of the second hierarchy is performed from the end of the two referenced intermediate parent circuits, and the processing of the parent circuit is performed when all the intermediate parent circuits of the second hierarchy are completed.

Therefore, the simulation time of the parallel circuit simulation is a total of eight processing times of the child circuit, the third-layer intermediate parent circuit referring to it, and the processing time of the second-layer intermediate parent circuit and parent circuit referencing it. Of the largest. The processing time of the parent circuit and the intermediate parent circuit varies depending on the number of nodes 34 to 40 of the parent circuit 19 and the intermediate parent circuits 20 to 25. Experiments have shown that the number of external nodes of the intermediate parent circuit hardly affects the processing time as compared with the internal nodes of the parent circuit and the intermediate parent circuit. Therefore, in order to reduce the processing time of the parallel simulation, it is effective to reduce the number of internal nodes of the parent circuit and the intermediate parent circuit.

When the processing time excluding the child circuit processing of the circuit of FIG. 4 is represented by the number of nodes, the parent circuit 19, the intermediate parent circuits 21, 25
Of the internal nodes 31 + 12 + 14 = 57 is the largest as compared with the sum of the other parent circuit and the two intermediate parent circuits, and 57 + α
Is the processing time. Here, α corresponds to the processing time given by the external node of the external node of the intermediate parent circuit. or,
In this circuit division, if the hierarchical circuit is not performed and one parent circuit refers to eight child circuits, the number of internal nodes of the parent circuit is 9
Eight, which is equivalent to the processing time of the parent circuit as it is. α
Is smaller than 98-57 = 41, and the hierarchical structure reduces the processing time of the parent circuit.

FIG. 5 is a table of the total simulation time when hierarchization is not performed. The upper part shows the time of the circuit of FIG. 4, and the lower part shows the time of another circuit having 8353 transistors.
The simulation time could be reduced by hierarchization for both circuits.

[0027]

As described above, according to the present invention, the hierarchical processing is performed while performing the circuit division.
This has the effect of keeping the number of nodes of the intermediate parent circuit as small as possible.

Further, as the number of processors of the parallel circuit simulator increases, the number of times of circuit division increases, and the number of shared nodes between child circuits after the completion of all circuit divisions increases. The former parent circuit becomes a structure consisting of one parent circuit and multiple intermediate parent circuits,
Since the number of nodes is small, that is, the processing time is short, and the nodes can be distributed to different processors and parallel processing can be performed, so that the overall time of the parallel circuit simulation is shortened. In the circuit of Example 2, which has 6974 transistors, the simulation overall time is reduced by 12% due to the hierarchical structure. Another circuit having 8353 transistors has a total simulation time of about 8 processors when divided into a hierarchical structure as in the second embodiment, which is about one time longer than that of one parent circuit that is not hierarchized. It showed a 22% reduction.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a flow of a process according to an embodiment of the present invention.

FIG. 2 is a diagram showing division and hierarchization of the embodiment shown in FIG. 1;

FIG. 3 is a system configuration diagram of a parallel circuit simulation according to the embodiment of FIG. 1;

FIG. 4 is a diagram showing an example applied to an actual circuit having 6974 transistors according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating an overall simulation time when a circuit is hierarchized and when a circuit is not hierarchized;

[Explanation of symbols]

1 Circuit connection data input 2 Preprocessing 3 Update processing 4 Division processing 5 Hierarchical processing 6 Termination judgment processing 7 Result output 8 EWS 9 Controller 10 Parallel circuit simulator 11 Circuit diagram input 12 Circuit connection data 13 Circuit division 14 Circuit division file 15 Parallel Compile 16 Parallel circuit simulation 17 Result file 18 Display 19 Parent circuit 20, 21, 22, 23, 24, 25 Intermediate parent circuit 26, 27, 28, 29, 30, 31, 32, 33 Child circuit 34, 35, 36, 37,38,39,40 number of nodes

Continuation of the front page (56) References JP-A-1-250173 (JP, A) JP-A-2-87279 (JP, A) JP-A-4-273582 (JP, A) Masahiko Koike, 4 others, " Prototype of Parallel Circuit Simulation Machine, "Information Processing Society of Japan Research Report (CA-68), Information Processing Society of Japan, 1987, Vol. 87, No. 78, p. 49-56 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 JICST file (JOIS)

Claims (2)

(57) [Claims] [Claim 1] by dividing the original circuit structure to the structure of the newly parent circuit and partial circuit, to refer to the parent circuit the partial circuit
Means for aligning the hierarchy of the partial circuits, and dividing the largest existing partial circuit among the partial circuits,
Repeat until the partial circuit reaches a predetermined number of processors
Means for performing division by dividing by a predetermined number of partial circuits referenced by the parent circuit.
When the number reaches the number of
Means for creating a new intermediate parent circuit in between and hierarchizing the plurality of partial circuits during parallel simulation.
Allocate one by one to the processor and
Assign one path and one parent circuit to the processor
Parallel circuit simulation circuit division method characterized by having a Teru means. 2. The circuit partitioning method for parallel simulation according to claim 1, wherein the uppermost parent circuit refers to a lower intermediate parent circuit, and the intermediate parent circuit is a lower intermediate parent circuit or a part thereof. A circuit division method for parallel circuit simulation, characterized by having a hierarchical structure for referring to circuits.