JP2859222B2 - Frame converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame conversion apparatus, and more particularly to a frame conversion apparatus for controlling generation of a frame pulse when a predetermined number of fixed short cells including delay fluctuations received in an ATM network are transferred in a frame. About.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing an example of a conventional system for absorbing delay fluctuations caused by an ATM network.

Referring to FIG. 3, in this conventional system, a cell generator 31 sends out a cell input 301 having a fixed generation interval t to an ATM network 32, and outputs the cell input 301 to the ATM network 32.
The cell input 301 which has received the delay variation from inside arrives at the delay variation absorption buffer 33 as the cell input 302 with the cell generation interval t disturbed. Thereafter, reading is started from the delay fluctuation absorbing buffer 33 at a period T, and the cell output 303 is output. The frame pulse circuit 34 includes the delay fluctuation absorbing buffer 3
Then, a frame pulse 304 having a period of nT is output using the read start signal from the trigger signal 3 as a trigger.

[0004]

In this conventional system,
Since the cell read cycle of the delay fluctuation absorbing buffer 33 is set to a fixed cycle T and the frame pulse is set to a fixed cycle nT, it takes a long time to transfer when the change width of the cell is small.
There is a problem that transmission efficiency cannot be improved.

An object of the present invention is to detect a cell fluctuation arriving at a delay fluctuation absorption buffer and automatically switch a frame pulse period according to the delay fluctuation width of the cell.
An object of the present invention is to provide a frame conversion device capable of improving transmission efficiency.

[0006]

According to the present invention, an ATM is provided.
Means for counting the number of fixed short cells including delay fluctuations of cell input, detecting and monitoring a cycle until the number of cells reaches a predetermined number, and automatically switching a frame pulse cycle based on the result. A featured frame conversion device is obtained.

[0007] Further, a cell number detecting means for counting the number of fixed short cells including a delay variation of the input of the ATM cell, and a cycle until the detection result of the cell number detecting means reaches the predetermined number is detected. Frame period detecting means, frame pulse period selecting means for determining and selecting the frame pulse period from the period detection result, and frame pulse generating means for switching the frame pulse period to the selected frame pulse period A frame conversion device characterized by the following is obtained.

Further, the cell number detecting means comprises a header discriminating circuit and a first counter, the frame cycle detecting means comprises a second counter and a first selector, and the frame pulse cycle selecting means comprises a second counter and a first selector. 2, the frame pulse generating means is formed by a frame pulse switching circuit, and the cell output and frame pulse output synchronizing means is formed by a delay fluctuation absorbing buffer. After resetting the fluctuation absorbing buffer and the first and second counters, the frame pulse switching circuit sets an initial period nT after resetting, starts communication, and inputs cells from the ATM network to the delay fluctuation absorbing buffer. When arriving, the header identification circuit indicates that the input cell has arrived. Detects and outputs an arrival signal to the first counter, and the second counter counts up each time a cell arrives, and starts counting up again from 0 when the count value reaches the predetermined number, The second counter starts counting up after being reset when the count number of the first counter is “1”, and the first selector determines that the count number of the first counter is “n”. Only the count number is selected, and a predetermined number n of cycles f is detected. The comparator compares the detected predetermined number of cells f with the initial cycle nT, and when the cycle fluctuates, the cycle f Is selected by the second selector to output a switching signal and data to the frame pulse switching circuit.

Further, a frame pulse conversion device is provided in which the delay fluctuation absorbing buffer is an elastic memory.

[0010]

Next, the present invention will be described with reference to the drawings.

First, the operation of the present invention will be described.
In the present invention, since the frame period is detected by the number of counts by the cell number detecting means, there is no need to detect or absorb the delay variation width of each cell.

Since the frame pulse is automatically corrected by the frame pulse generating means and the frame pulse selecting means, the frame transfer can be performed at an optimum transfer rate.

FIG. 1 is a block diagram showing an embodiment of a frame conversion device according to the present invention, and FIG. 2 is a diagram for explaining a frame pulse cycle timing in the present embodiment.

Referring to FIG. 1, a frame pulse converting apparatus including frame pulse generating means for packing fixed short cells including delay fluctuations received in an ATM network into a fixed number of frame pulses according to an embodiment of the present invention,
A header identification circuit 11 and a counter 12 serving as a cell number detecting means for counting the number of fixed short cells including the delay variation of the input cell 101 of the cell, and a cycle until the detection result of the cell number detecting means reaches a predetermined number. A counter 13 and a selector 14 as a frame cycle detecting means for detecting, a selector 15 and a comparator 16 as a frame pulse cycle selecting means for determining and selecting a frame pulse cycle from the cycle detection result, and a frame pulse cycle are selected. A frame pulse switching circuit 17 as a frame pulse generating means for switching to a frame pulse cycle, a cell output 103 and a frame pulse output 10
4 and a delay fluctuation absorbing buffer 18 as a synchronizing means.

The delay fluctuation absorbing buffer 18 is realized by using an elastic memory (ES).

Next, the operation of this embodiment will be described with reference to FIG.

As shown in FIG. 2, the first cell and the n-th cell are monitored, an arrival cycle fi (i = 1, 2 in the figure) of a predetermined number n of cells is detected, and a frame pulse is detected. By determining the period and switching the frame pulse period, it is possible to improve the transmission efficiency according to the delay variation.

Next, a specific operation of the present embodiment will be described. First, before starting communication, a reset signal 1 is output.
In step 05, the delay fluctuation absorbing buffer 18 is reset to be empty. The counters 12 and 13 are also reset to "0". Further, after the frame pulse switching circuit 17 is reset, the initial period nT is set.

When the cell input 101 arrives at the delay fluctuation absorbing buffer 18 from the ATM network after the start of communication, the header identification circuit 11 detects the arrival of the cell input 101 and outputs the cell input 102 of the arrival signal to the counter 12. .

The counter 12 counts up each time the cell input 102 arrives, and starts counting up again from "0" when the count value reaches a predetermined number n.

The counter 13 is reset when the count number of the counter 12 is "1", and starts counting up.

The selector 14 selects only the count number when the count number of the counter 12 is "n", and detects a predetermined number n of the periods fi. Cycle fi of the detected number of predetermined cells
And the initial setting period nT are compared by the comparator 16. When the result is fi> nT or fi <nT (when the period fluctuates), the period fi is selected by the selector 15, and the switching signal 106 and the switching signal 106 are transmitted to the frame pulse switching circuit 17. Data 1
07 is output.

[0023]

As described above, the present invention counts the number of fixed short cells including the delay fluctuation of the input of the ATM cell, detects and monitors the cycle until the number of cells reaches a predetermined number, and obtains the result. A means for automatically switching the period of the frame pulse based on the number of fixed short cells including the delay fluctuation of the input of the ATM cell; Frame period detecting means for detecting a cycle until the number of frames is reached, and frame pulse cycle selecting means for determining and selecting a frame pulse cycle from the cycle detection result,
Frame pulse generating means for switching the cycle of the frame pulse to the selected frame pulse cycle, the cell number detecting means further comprises a header discriminating circuit and a first counter, and the frame cycle detecting means comprises a second frame cycle detecting means. The frame pulse period selecting means is constituted by a second selector and a comparator, the frame pulse generating means is constituted by a frame pulse switching circuit, and the synchronizing means of the cell output and the frame pulse output is constituted by a delay. The delay pulse buffer, the first and second counters are reset before starting communication, and the initial period nT is set after the reset, and the communication is started. Enter delay fluctuation absorption buffer from ATM network When a cell arrives, the header identification circuit detects the arrival of the input cell and outputs an arrival signal to the first counter. The second counter counts up each time a cell arrives, and the count value reaches a predetermined number. When it reaches, the counter starts counting up again from 0, and the second counter
After the counter is reset when the count number of the counter is "1", it starts counting up. The first selector selects only the count number when the count number of the first counter is "n". The cycle f is detected by the second selector, and the cycle f is selected by the second selector when the cycle f is changed by comparing the detected cycle f of the predetermined number of cells with the initial cycle nT. And the delay fluctuation absorbing buffer is an elastic memory, so that the transmission efficiency can be improved in accordance with the periodic fluctuation received from the ATM network.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a frame conversion device according to the present invention.

FIG. 2 is a diagram for explaining a frame pulse cycle timing in the present embodiment.

FIG. 3 is a diagram showing an example of a conventional method for absorbing delay fluctuations caused by an ATM network.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Header identification circuit 12, 13 Counter 14, 15 Selector 16 Comparator 17 Frame pulse switching circuit 18, 33 Delay absorption buffer 31 Cell generator 32 ATM network 34 Frame pulse circuit 101, 102, 301, 302 Cell input 103, 303 Cell output 104, 304 Frame pulse output 105 Reset signal 106 Switching signal 107 Data

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/28 H04L 12/56 H04L 7/00 H04L 7/08

Claims (4)

(57) [Claims] 1. The method according to claim 1, wherein the number of fixed short cells including the delay fluctuation of the input of the ATM cell is counted, and a period until the number of cells reaches a predetermined number is detected and monitored. A frame conversion device comprising switching means. 2. A cell number detecting means for counting the number of fixed short cells including a delay variation of an input of the ATM cell, and a period until a detection result of the cell number detecting means reaches the predetermined number. Frame period detecting means, frame pulse period selecting means for determining and selecting the frame pulse period from the period detection result, and frame pulse generating means for switching the frame pulse period to the selected frame pulse period The frame conversion device according to claim 1, wherein: 3. The cell number detecting means comprises a header discriminating circuit and a first counter, the frame cycle detecting means comprises a second counter and a first selector, and the frame pulse cycle selecting means comprises 2, the frame pulse generating means is constituted by a frame pulse switching circuit, the cell output and frame pulse output synchronizing means is constituted by a delay fluctuation absorbing buffer, and the delay is controlled before starting communication. After resetting the fluctuation absorbing buffer and the first and second counters, the frame pulse switching circuit sets an initial period nT after resetting, starts communication, and inputs cells from the ATM network to the delay fluctuation absorbing buffer. Upon arrival, the header identification circuit detects the arrival of the input cell. The second counter outputs an arrival signal to the first counter, and the second counter counts up each time a cell arrives. When the count value reaches the predetermined number, the second counter starts counting up from 0 again. The second counter starts counting up after being reset when the count number of the first counter is "1", and the first selector operates when the count number of the first counter is "n". Only the count number is selected, a predetermined number n of cycles f is detected, and the comparator compares the detected predetermined number of cells f with the initial cycle nT, and when the cycle fluctuates, the cycle f 3. The frame pulse conversion device according to claim 2, wherein a switching signal and data are output to the frame pulse switching circuit by being selected by a second selector. 4. The frame conversion device according to claim 3, wherein said delay fluctuation absorbing buffer is an elastic memory.