SU1734241A1 - Data transceiver for integrated ring communications network - Google Patents

Abstract

SUMMARY OF THE INVENTION: The device comprises a receiver 1, a clock extraction unit 2, a counter 3, first and second shift registers 4 and 5, a ring shift register 6, a decoder for the beginning of the slot 7, a decoder for the address of the receiver 8, a decoder for the switching type 9 signals, a memory block 10, write signal generator 11, transmitter 12, multiplexer 13, buffer memory block 14, read signal generator 15, signal decoder 16 Ignore, signal decoder 17 Signal end, receiver 18 address register, source state register 19, element t OR 20, counter 21 time slots and the control unit 22. The increase in throughput is achieved by providing the reception and transmission of information in the switching modes of channels, messages, and 1-2-3-4-5-20-6-21-19 packets. 1-7-3-22-15-13, 1-8-11-10, 1-9-20, 1-16-20, 1-17-20, 1-12-13-18. 2 Il. - Yo

Description

The invention relates to radio engineering and communication and can be used in communication networks that use quasi-simultaneous channel switching, switching messages, or packet switching when transmitting information.

The purpose of the invention is to increase throughput by providing the possibility of receiving and transmitting information in the modes of switching channels, messages and packets.

FIG. Figure 1 shows the electrical circuit diagram of a device for transmitting and receiving information for an integrated ring network; in fig. 2 is a timing diagram of a signal generated by a device;

The device for receiving and transmitting information for an integrated ring network contains a receiver 1, a sync signal extraction unit 2, a counter 3, first and second shift registers 4 and 5, a shift ring register 6, a decoder 7 for the start of the channel interval, a decoder for the recipient address 8, a decoder 9 switching type signals, memory block 10, shaper 11 write signals, transmitter 12, multiplexer 13, buffer memory block 14, read signal shaper 15, signal decoder 16 Ignore signal, signal decoder 17 End of operation register 18 address by etter, state register 19, an OR gate 20, the source, the counter 21 timeslots v the control unit 22.

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00. &Amp; | y 4

The information reception and transmission device for the integrated ring telecommunication network operates as follows.

In the standby mode (initial state), the clock signals are fed from the network to the input of receiver 1, using block 2, which are fed to the counting input of counter 3 working modulo VKi (where VKi is the number of clock pulses one channel of the network). Thus, the counter 3 at its first output generates the sync pulses of the beginning of the time slots, which are fed to the sync input of the first register 4, which has bits (where Vki is the number of time slots in one communication network exchange cycle). At the output of the first register 4, the beginning of the cycle pulses (NC) are formed. These pulses, together with the pulses of the beginning of the time intervals, arrive at the second register 5, which has K bits, as a result of which the previously occupied channel interval is released, if it does not transmit the End or End of work signals, and during the K cycles no or information The signals from the output of the second register 5 through the element OR 20 are fed to the information input of the ring register 6 and set to zero bit corresponding to the current channel interval. The ring register B provides the storage of the state of the channel interval during the exchange of information on the communication network. In all reception-transmission devices on the communication network, the initial phase of the beginning of the cycle pulses is made at the moment of receiving or the first after the information signal is turned on, which contains the signal for the start of the channel interval detected by the decoder 7. The output of the latter in this case is a pulse setting Reset counter 3 to the initial state.

In the Response mode, the device receiving and transmitting information works as follows. After the decoder 7 selects the pulse of the start of the channel interval and sets the counter 3 to the initial state at the output of the receiver 1, the received from the communication network signal of the recipient's address (AP), which is selected by the decoder 8, is restored. a switching type signal (STK), the selection of which is performed by the decoder 9. In the event that information is transmitted in a channel switching or switching mode in a given time slot

messages, the signal of the switching type has the form of a logical one. If information is transmitted in a given channel interval in the packet switching mode, then

the signal of the switching type has the form of logical 0. From the output of the decoder 9, the signal corresponding to the type of switching in this channel interval, through the element OR 20, is written into the corresponding

0 to this channel interval, the bit of the ring register 6. If the received signal of the recipient's address does not match the address of this receiving and transmitting device, the decoder 8 does not generate signals for detecting information and registering it, since it is addressed to another device (subscriber). If the received signal of the recipient's address coincides with the address of the present device of reception and transmission, then at the output of the decoder 8 a signal is generated that triggers the driver 11, which generates from the clock signals from block 2 signals recording information from the receiver 5 output 1 block 10, from which the information signals are read by the receiver,

After the address is detected by the decoder 8, if it coincides with the signal from

0 of the second output of counter 3, as well as on the condition that the subscriber has information in this channel interval, and the type of information of the subscriber coincides with the type of information transmitted in this channel

5, block 22 generates an information frame formation resolution signal in multiplexer 13, which, under the influence of signals from the output of shaper 15, alternately reads the subscriber state signal from register 19 to input re0 of sensor 12, the receiver's address signal from register 18 and directly information signals from block 14. In this case, the signal from the output of block 22 interrupts the connection

5 receiver 1 with a transmitter, which allows replacing the information received by this device with the information of the corresponding subscriber. After the transmission of information from block 14 is completed, when the channel interval is completed by block 22, the blocking signal is removed from the control input of transmitter 1 and its communication with receiver 12 is restored.

This will continue until

5, a packet containing in the service part the signal Reject or End of Work will not be received. When these signals are detected by decoders 16 or 17, respectively, the signal from the output of one of them through the element OR 20 is set to

zero bit corresponding to the current channel interval in the ring register 6, which means the release of this channel interval and disconnection of subscribers.

In the Call mode, the device operates as follows.

The code of the called subscriber (recipient), coming from the subscriber's terminal device, is recorded in register 18. At the same time, the control field (PU) signals of the packet are recorded at another input of the device, and the channel address signal is input to the input of block 22. After This begins waiting for a free channel interval, the beginning of which corresponds to the beginning of the zero signal at the output of the ring register 6. Information is recorded in the latter through the OR element 20 from the decoder 9 after analyzing the Pe code the commutation switch transmitted in the control field of each packet (channel interval) and shifted by one bit with each pulse of the beginning of the channel interval formed by the counter 3. Since the number of bits in the ring register 6 is equal to the number of channel intervals in one cycle of information exchange on the network , then information about the state of all channel intervals in the previous cycle will circulate in it. As soon as a signal is received from the ring register 6 at the output of block 22, indicating that this channel interval is free, the control input of the transmitter will be sent through block 22, a signal prohibiting the retransmission of signals from the receiver 1, and the information input the transmitter 12 through the multiplexer 13 will begin to receive the packet header from registers 18 and 19, and then the information part of the packet from block 14. Thus, the entire information packet will be transmitted to the communication line, and at the moment of its transmission start, the current bit of the first register 4 will be recorded as logical 1 according to the signal from the output of block 22, which ensures the formation of a signal the beginning of the cycle at the moment of the beginning of the transmission of the first and subsequent packets in this channel interval, i.e. The device, when transmitting information in the modes of switching channels and switching messages, autonomously establishes the beginning of a cycle and synchronizes other devices for receiving and transmitting an integrated communication network.

If the information is transmitted in the circuit-switched mode, then after the first packet is transmitted, the signal is Channel request

the output of block 22 will be cleared, and in the first register 4 the signal of logical 1 will be recorded only once. This ensures that the time position of the channel interval in which the packet was transmitted is stored. Since the first register 4 contains bits and is looped, and its shift occurs by one bit with each pulse from the output of counter 3, the logical 1 written into it will circulate with a period of 1 cycle, which will provide packet cyclical transmission will be transmitted only in one channel interval.

If the subscriber of the device operates in the message switching mode, then after the first packet is transmitted, the channel request signal from the first input of block 22 is not removed and when the next free time intervals occur, they are occupied, i.e. transmitting packets to them, as described above, and simultaneously writing logical 1 to the corresponding bits of the first register 4, Therefore, in this mode several units will circulate in the first register 4, the number and phase position of which will correspond to the number and phase position in the channel cycle the intervals occupied by this device.

If in the process of transmission the previously occupied channel intervals are released, they will also be occupied by this device, since the Channel Request signal is not removed in this mode in register 19.

The number of time slots. Which can be occupied during a cycle by a subscriber operating in the message switching mode, is determined by the counter 2 according to information received from the ring register 6. As soon as the number of remaining free time slots reaches the specified value, the channel request signal is removed in register 19, the subsequent free space of the ate channel intervals will stop.

In the packet switching mode, under logical 1, the first register 4 is not recorded, therefore no cycles are formed and a new free channel interval is searched for and transmitted for each packet.

Claims (1)

Claims An information transmission and reception device for an integrated ring communication network, comprising a receiver and a transmitter, to the control input of which the first output of the control unit is connected, the sync pulse allocation unit and the receiver address decoder, the inputs of which are combined and connected to the receiver output, as well as a memory block and a block of buffer memory, characterized in that, in order to increase throughput by providing the possibility of receiving and transmitting information in the modes of switching channels of messages and signals, the decoder of the beginning of the channel interval, the decoder of signals such as switching, the decoder of the signal Hang-up, the decoder of the signal End of operation, serially connected counter, the first and second shift registers, the OR element, the ring shift register, channel interval counter, source status register and multiplexer, register source addresses, read signal shaper and write signal shaper, the output of which sub-keys to the control input of the memory unit, whose information input is combined with the inputs channel start slot, signal decoder of the switching type, signal decoder Ignore and signal decoder End of operation and connected to the output of the receiver, another output of which is connected to the first information input of the transmitter, to the second information input of which the output of the multiplexer is connected, to the second and third inputs of which are connected outputs according to the address register the recipient and the buffer memory block, and the control input of the multiplexer is connected to the output of the read signal generator, the synchronization input of which is combined with the synchronization inputs of the write signal generator and the counter and connected to the output of the sync signal allocation unit, the output of which is connected to the second outputs of the channel interval counter, the second shift register and the ring shift register, the output of which is connected to The first output of the control unit, the second input of which is connected to the output of the recipient address decoder and the control inputs of the recording signal generator and the read signal generator, another control input of which is connected to the second output of the control unit, the third output and the third input are connected respectively to the second input and the output of the first register, the second output of the source status register is connected to the fourth input of the control unit, to the fifth input of which the additional counter output is connected, and Exit Decoder type switching signals, and the decoder descrambler End End of the signal of the signal are connected respectively to the second, third and fourth inputs of the OR element. FIG. 2