JP3641400B2 - ATM traffic shaping device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an ATM traffic shaping apparatus, and more particularly to an ATM traffic shaping apparatus that performs traffic shaping control of cells output from an ATM switch having an UTOPIA level 2 interface that is an ATM standard interface.
[0002]
[Prior art]
The UTOPIA level 2 interface is an interface for connecting an ATM layer function and a plurality of PHY (Physical Layer) functions.
[0003]
In an ATM (Asynchronous Transfer Mode) communication network, cell traffic shaping (cell transmission interval control) at the entrance of a VP / VC network in order to design and guarantee its resources for each virtual path (VP) or virtual channel (VC). Need to do.
[0004]
In the conventional ATM traffic shaping device, cells are written once in the cell storage memory, and the cells are read from the cell storage memory again at a constant period, thereby making the cell transmission intervals uniform. Specifically, an ideal scheduled transmission time is obtained from the arrival time of the input cell by scheduling control for the cell input to the ATM traffic shaping device. Then, by address search control using a memory such as a CAM (Content Addressable Memory), a free space address in the cell storage memory corresponding to the scheduled transmission time or the closest transmission time thereafter is searched. Write the input cell to the empty area. Reading from the cell storage memory is sequentially read from the storage memory according to the current transmission time.
[0005]
[Problems to be solved by the invention]
However, the conventional ATM traffic shaping device has a problem that the size of hardware (H / W) increases because a cell storage memory for storing cells and a memory for performing scheduling control and address search are required. . There is also a problem that the cell delay increases because the cell is once written in the cell storage memory. Further, there is a problem that the input cell burst length is limited depending on the cell storage memory size in order to realize the shaping.
[0006]
Therefore, an object of the present invention is to reduce the size of hardware such as memory and further increase cell delay by performing shaping using handshake control of an ATM switch having a UTOPIA level 2 interface without performing scheduling control or address search. Is to prevent. Another object of the present invention is to obtain shaping performance that does not depend on traffic conditions such as input cell speed and burst length.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a cell detection means for detecting to which terminal a cell output from an ATM switch is directed, and a cell for the terminal detected by the cell detection means within a predetermined time. And a response signal returning means for returning a response signal according to the comparison result to the ATM switch, and corresponding to the response signal, An ATM traffic shaping device is configured to receive a cell output from the ATM switch at a terminal.
[0008]
According to the present invention, by performing shaping using the handshake control of an ATM switch having a UTOPIA level 2 interface without performing scheduling control or address search, it is possible to reduce the hardware scale such as memory and further increase the cell delay. It becomes possible to prevent. It is also possible to obtain shaping performance that does not depend on traffic conditions such as input cell speed and burst length.
[0009]
Specifically, referring to FIG. 1, the ATM traffic shaping device 10 according to the present invention uses the handshake control for an ATM switch 11 having a UTOPIA level 2 interface to output cells ( (TxDATA) shaping is performed. That is, provided for each UTOPIA address (TxADDR), according to the shaping rate setting 6, the available signal 7 (AVE0 to N; N is a positive integer; FIG. 1 shows the case of N = 30) (N + 1) A selectable output control circuit 2, a selector 4 that selects one of the (N + 1) available signals 7 in the polling control from the ATM switch 11, and outputs it to the ATM switch 11 as a TxCLAV signal, and the ATM switch 11 The cell detection circuit 1 detects which UTOPIA address the output cell belongs to.
[0010]
Referring to FIG. 2, the available output control circuit 2 performs UP count when the up (UP) / down (DOWN) counter 21 detects the corresponding cell output from the ATM switch 11, and sets the shaping rate setting 6. DOWN count is performed at a set cycle. When the counter value T is less than the available output threshold Ath, the available signal 7 is enabled to request a cell from the ATM switch 11, and when the counter value T exceeds the available output threshold Ath, the available signal 7 is disabled. In this case, control is performed such that no cell request is made.
[0011]
In other words, in the present invention, UTOPIA level 2 handshake control is used, and shaping is performed by dynamically enabling or disabling the TxCLAV signal so that the output cell rate from the ATM switch 11 matches the set shaping cell rate. Control is in progress.
[0012]
Further, since shaping control is performed in units of UTOPIA addresses, VP shaping can be realized by assigning a UTOPIA address and a virtual path (VP) on a one-to-one basis, and VC shaping can be realized by assigning a virtual channel (VC).
[0013]
Furthermore, by assigning the UTOPIA address and the PHY device on a one-to-one basis and shaping them below the PHY transmission capacity, it is possible to eliminate the need for back pressure control from the PHY device to the ATM switch.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of the best mode of an ATM traffic shaping apparatus according to the present invention. Referring to the figure, the ATM traffic shaping device 10 includes a TxSOC signal, a TxENB signal, and a Uxpia level 2 signal output from an ATM switch 11 having a UTOPIA level 2 interface, which is an ATM interface standardized by the ATM forum. From the TxADDR signal, it is detected which TxADDR (hereinafter referred to as UTOPIA address) the cell output from the ATM switch 11 belongs to, and the corresponding cell reception signal 3 (# 0 to #N) corresponding to the UTOPIA address is output. When the cell detection circuit 1 and the output available signal 7 are set to the “Hi (high)” level, that is, valid at the set shaping rate 6 period, and the corresponding cell reception signal 3 output from the cell detection circuit 1 is detected, the available signal 7 (# 0 The available output control circuit 2 (# 0 to #N) that disables #N) at the "Lo (low)" level, and (N + 1) number of available signals 7 (# 0 to #N) with the UTOPIA address as the selection signal 5 ) And a selector 4 that outputs to the ATM switch 11 as a TxCLAV signal.
[0015]
Next, the configuration of the available output control circuit 2 will be described. FIG. 2 is a configuration diagram of the available output control circuit 2. Referring to the figure, the available output control circuit 2 divides the CLK (clock), and the shaping rate setting 6 for setting the frequency dividing number M (M is a positive integer) of the frequency dividing counter 20. The frequency division number M and the counter value L of the frequency division counter 20 (L is a positive integer) are compared, and if they coincide, a comparator 22 that outputs a coincidence pulse 25 and the coincidence pulse 25 are input. UP / DOWN counter 21 that counts down and counts up when cell reception signal 3 is input, and does not count down when its counter value T (T is 0 or a positive integer) is 0; The comparator 23 that compares the counter value T of the UP / DOWN counter 21 with the set available output threshold value Ath, and is set when the comparison result of the comparator 23 is “T <Ath”. Re a Aberaburu signal 7 as Hi level, that is valid, configured to include a S-R circuit 24 the Aberaburu signal 7 is reset when the comparison result is "T ≧ Ath" and Lo level or disabled.
[0016]
Next, handshake control on the Tx side (direction in which cells are transmitted from the ATM switch 11) of the UTOPIA level 2 interface used in the present invention will be described with reference to FIG. FIG. 4 is a configuration diagram of an ATM switch and a plurality of PHYs for explaining the UTOPIA level 2 interface.
[0017]
Usually, the UTOPIA level 2 interface is used as a connection interface between an ATM layer chip 11 such as an ATM switch and a plurality of PHYs 31 (31-0 to 31-N). TxDATA is 8-bit parallel (7 ... 0) ATM cell data of 53 clocks per cell length, TxSOC signal is a cell pulse signal indicating the head of the cell with a “Hi” level of 1 clock width, and TxENB is the validity of the cell data. An enable signal indicated by “Lo” level and a TxADDR signal are addresses representing each PHY 31. In either case, multiple outputs are made from the ATM switch 11 to the PHY 31. The TxCLAV signal indicates whether or not the cell data of the PHY 31 indicated by TxADDR by polling can be received, and indicates that reception is possible at the “Hi” level.
[0018]
Next, the operation of the UTOPIA level 2 interface will be described. FIG. 5 is a timing chart showing the operation of the UTOPIA level 2 interface. Referring to the figure, the ATM switch 11 polls the PHY 31 by outputting a TxADDR signal (0 to 10) every other clock. Now, when the TxADDR signal is 0 and 1, the TxCLAV signal is “Hi” at the next clock timing (clocks 43 and 45), which is PHY # 0 (31-0) and PHY # 1 (31− 1) indicates that cell reception is possible.
[0019]
When the polling period (clock 1 to clock 53) ends, the ATM switch 11 determines to which PHY 31 the cell is output (clock 54: PHY selection). When PHY # 0 is selected, the TxADDR signal is set to 0 and the TxENB signal is set to “Hi” in the clock 54, and the cell data of the PHY # 0, that is, the TxDATA signal and the TxSOC signal are output at the next clock timing (clock 1). In PHY # 0, 0 (clock 54) is indicated in TxADDR, and at the next clock timing (clock 1), “Hi” is output to TxSOC and “Lo” is output to TxENB. Receive. In the UTOPIA level 2 interface, the time required to output one cell data, that is, one cell time is 54 clocks including the polling period and the PHY selection period.
[0020]
Next, the operation of the present invention will be described with reference to FIG. The available output control circuit 2 (# 0 to #N; in this embodiment, N = 30 as an example) is provided in units of TxADDR (hereinafter referred to as UTOPIA address). FIG. 3 is a diagram showing the relationship between the UTOPIA address and various tables. In the figure, (a) shows the relationship between the UTOPIA address and the VP table, (b) shows the relationship between the UTOPIA address and the VC table, and (c) shows the relationship between the UTOPIA address and the PHY table. ing. As shown in the UTOPIA address-VP table in FIG. 5A, the UTOPIA address and the shaping unit VP are assigned one-to-one. Thereby, the available signal 7 (# 0 to #N) output from each available output control circuit 2 indicates the availability signal 7 of each VP unit in the polling control of the ATM switch 11, that is, whether or not the cell can be received. In the example of FIG. 6A, since UTOPIA address 0 is assigned to VP5, the available signal 07 (# 0) indicates the VP5 available signal. Similarly, the available signal 07 (# 1) indicates the VP6 available signal. The polling control outputs a TxCLAV signal to the ATM switch 11 by selecting one from the available signals 7 (# 0 to #N) using the UTOPIA address as a selection signal of the selector 4.
[0021]
As a result of polling, when a cell of the UTOPIA address determined in the ATM switch 11 is output, the cell detection circuit 1 detects which UTOPIA address corresponds to the cell, ie, which VP cell, and the corresponding available output control circuit. 2, corresponding cell reception signal 3 (# 0 to #N) is output.
[0022]
As described above, by performing output control of the available signal 7 in units of VP, a cell output request or suppression of the VP can be made to the ATM switch 11, and shaping in units of VP can be performed.
[0023]
Next, the operation of each available output control circuit 2 will be described with reference to FIG. The UP / DOWN counter 21 constantly compares the number of coincidence pulses 25 generated at the set shaping rate 6 with the number of corresponding cell reception signals 3. When the counter value T of the UP / DOWN counter 21 is less than the available output threshold Ath, it is considered that the cell output rate from the ATM switch 11 is smaller than the set shaping rate 6, and the SR circuit 24 is set and the available signal 7 is set. Is requested and a cell is requested from the ATM switch 11. When the counter value T becomes equal to or greater than the available output threshold Ath, it is considered that the cell output rate from the ATM switch 11 is larger than the set shaping rate 6, and the SR circuit 24 is reset to disable the available signal 7, The cell output rate from the switch 11 is suppressed. The smaller the value of the available output threshold Ath (minimum value = 1), the higher the shaping accuracy.
[0024]
FIG. 6 is a timing chart showing the operation of the available output control circuit 2. The figure shows the operation of the available output control circuit 2 when the available output threshold Ath is “2”. Referring to the figure, the coincidence pulse 25 is output to the UP / DOWN counter 21 at the time interval of 6 cells with the shaping rate setting 6, and the cells A, B, C and D of the shaping target VP are burst to the ATM switch 11. It is input with.
[0025]
First, in the polling cycle (1), since the counter value T = 0 of the UP / DOWN counter 21 is not counted down by the coincidence pulse 25 (1). Since T <Ath, the available signal 7 becomes “Hi”, that is, becomes valid. When the cell A is output from the ATM switch 11 by polling at this time, the UP / DOWN counter 21 counts up and the counter value T = 1. Even when the counter value T = 1, since T <Ath, the available signal 07 remains “Hi” (polling cycle (2)).
[0026]
Next, when cell B is output by polling in the polling cycle (2), the counter value T = 2. At this time, since T ≧ Ath, the available signal 7 is “Lo”, that is, invalid, and no cell is output during this period (polling cycle (3)).
[0027]
Next, when the counter value T is counted down to 1 by the coincidence pulse 25 (2), T <Ath and the available signal 7 becomes valid (polling cycle (4)). When the cell C is output by polling at this time, the counter value T = 2 and the available signal 7 becomes invalid (polling cycle (5)).
[0028]
In the polling cycle (8), the available signal 7 is valid. However, since there is no shaping target cell in the ATM switch 11, the cell is not output, and the DOWN count is advanced by the coincidence pulse 25 (4). = 0.
[0029]
In the polling cycles (9) and (10), since the shaping target cell is input into the ATM switch 11, the cells E and F are output as a result of polling (polling cycles (10) and (11)). . Thereafter, the same operation is performed. With this control, the cells output from the ATM switch can be shaped in UTOPIA address units, that is, in VP units.
[0030]
Further, as shown in the UTOPIA address-VC table in FIG. 3B, shaping in units of VC can be performed by assigning the UTOPIA address and the VC one to one.
[0031]
【Example】
Next, examples of the present invention will be described. 7 and 8 are block diagrams showing an example of an interface between a conventional ATM switch and a plurality of PHYs. When the ATM layer chip (ATM switch) 11 and the PHY 31 are connected on a one-to-one basis, a UTOPIA level 1 (Lev1) interface that is a standard interface defined by the ATM Forum is used. When a plurality of PHYs 31 having the UTOPIA level 1 interface are connected to the ATM switch 11, a level conversion circuit for converting the UTOPIA level 2 interface on the ATM switch 11 side to the UTOPIA level 1 interface on the PHY 31 side as shown in FIG. 70 is required. In this level conversion circuit 70, it is necessary to select a TxCLAV signal 71 (# 0 to #N) indicating whether or not a cell can be received from each PHY 31 by the selector 72 according to polling from the ATM switch 11 and to output it to the ATM switch 11. . At this time, as described in the operation of the UTOPIA level 2 interface in FIG. 5, the TxCLAV signal 71 of the corresponding PHY 31 must be returned at the clock timing next to the UTOPIA address (TxADDR) output from the ATM switch 11. For this reason, when the clock frequency is large or when the connection distance between the ATM switch 11 and the PHY 31 is long, the timing margin between the clock and the TxCLAV signal 71 is lost, and control may not be performed normally.
[0032]
Further, as shown in FIG. 8 in another configuration example, when an ATM layer chip 82 having a UTOPIA level 1 interface for performing processing such as an OAM function is interposed between the ATM switch 11 and the PHY 31, the ATM switch 11 polls the PHY 31. Cannot be performed because of the ATM layer chip 82, and the TxCLAV signal 81 (# 0 to #N) of each PHY 31 cannot be output to the ATM switch 11.
[0033]
As shown in the above two configuration examples, when the PHY TxCLAV signal cannot be output to the ATM switch, that is, when the back pressure control cannot be performed from the PHY to the ATM switch, the cell pool of the input buffer provided in the PHY Since cells are output from the ATM switch regardless of the amount, there is a problem that the input buffer overflows. In such a configuration and situation, the method of the present invention can be applied.
[0034]
Next, the application method will be described. First, as shown in FIG. 3 (C) UTOPIA address-PHY table, the UTOPIA address and each PHY 31 (# 0 to #N) are assigned one-to-one. Then, in the shaping rate setting 6 (# 0 to #N) in FIG. 1, the transmission capacity speed (logical speed) of the assigned PHY 31 is set. Further, the same value as the FULL threshold value of the input buffer of the PHY 31 is set to the available output threshold value Ath shown in FIG. Thereby, shaping can be performed within the logical speed of PHY31. Further, the available output control circuit 2 virtually implements an input buffer of the PHY 31 and can perform back pressure control on the ATM switch 11 using the available signal 7.
[0035]
Next, the operation of the available output control circuit 2 will be described with reference to FIG. The coincidence pulse 25 represents a cell output from the input buffer of the PHY 31 to the transmission path, and the corresponding cell reception signal 3 represents a cell input from the ATM switch 11 to the input buffer of the PHY 31. Therefore, the UP / DOWN counter 21 represents the amount of accumulated cells in the input buffer of the PHY 31. When the counter value T is equal to or greater than the threshold value Ath, it is considered that the cell accumulation amount of the input buffer has become FULL, and the back pressure control can be performed on the ATM switch 11 by invalidating the available signal 7. .
[0036]
【The invention's effect】
According to the present invention, the ATM traffic shaping device detects a cell to which a cell output from an ATM switch is directed to a terminal, and a cell for the terminal detected by the cell detection unit within a predetermined time. And a response signal returning means for returning a response signal corresponding to the comparison result to the ATM switch, and corresponding to the response signal. Since the cell output from the ATM switch is received by the terminal, by performing shaping using the handshake control of the ATM switch having the UTOPIA level 2 interface without performing scheduling control or address search, Reduce the size of hardware such as memory, and prevent the increase in cell delay It can become. It is also possible to obtain shaping performance that does not depend on traffic conditions such as input cell speed and burst length.
[0037]
Specifically, the first effect is that a cell storage memory for storing cells and a memory for performing scheduling control and address search are not required, and the H / W scale can be reduced. The reason is that using UTOPIA level 2 handshake control, the TxCLAV signal is dynamically enabled or disabled so that the output cell rate from the ATM switch matches the set shaping cell rate. This is because.
[0038]
The second effect is that both VP and VC are provided as shaping units, and a mixture thereof can be realized. The reason is that, since shaping control is performed in units of UTOPIA addresses, VP shaping can be realized by assigning UTOPIA addresses and VPs one to one, and VC shaping can be realized by assigning VCs.
[0039]
A third effect is that back pressure control from the PHY device to the ATM switch can be made unnecessary. This is because, since shaping control is performed in units of UTOPIA addresses, a PHY input buffer is virtually realized by assigning UTOPIA addresses and PHYs one-to-one, and shaping is performed in units of PHYs.
[0040]
The fourth effect is that shaping can be realized without limitation of the input cell burst length to be shaped. The reason for this is that in the shaping using the cell storage memory, the condition of the input cell burst length that can realize the shaping depends on the cell storage memory size. This is because in this method, since no cell storage memory is used, shaping can be realized regardless of the condition of the input cell burst length.
[0041]
The fifth effect is that the cell delay due to shaping does not increase. The reason for this is that in shaping using a cell storage memory, the cell delay is increased because the cell is once written in the cell storage memory. However, in this method, since the cell storage memory is not used for shaping, the delay does not increase. It is.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of the best mode of an ATM traffic shaping apparatus according to the present invention.
FIG. 2 is a configuration diagram of an available output control circuit 2;
FIG. 3 is a diagram illustrating a relationship between a UTOPIA address and various tables.
FIG. 4 is a configuration diagram of an ATM switch and a plurality of PHYs for explaining a UTOPIA level 2 interface;
FIG. 5 is a timing chart showing the operation of the UTOPIA level 2 interface.
FIG. 6 is a timing chart showing the operation of the available output control circuit 2;
FIG. 7 is a configuration diagram of an example of an interface between a conventional ATM switch and a plurality of PHYs.
FIG. 8 is a configuration diagram of an example of an interface between a conventional ATM switch and a plurality of PHYs.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Cell detection circuit 2 Available output control circuit 4 Selector 10 ATM traffic shaping apparatus 11 ATM switch 20 Frequency division counter 21 UP / DOWN counter 22, 23 Comparator 24 SR circuit

Claims (9)

Cell detection means for detecting to which terminal the cell output from the ATM switch is directed, the number of cells for the terminal detected by the cell detection means within a predetermined time, and preset for the terminal A response signal returning means for comparing a predetermined threshold value and returning a response signal corresponding to the comparison result to the ATM switch, and a cell output from the ATM switch at the terminal in response to the response signal An ATM traffic shaping device. 2. The response signal returning means returns a response signal indicating that reception is possible to the ATM switch when the number of cells for the terminal detected by the cell detecting means is less than the threshold. ATM traffic shaping device. The response signal returning means returns a response signal indicating that reception is impossible to the ATM switch when the number of cells for the terminal detected by the cell detecting means is equal to or greater than the threshold value. Item 3. An ATM traffic shaping device according to Item 1 or 2. The cell detection means is output from the ATM switch from a UTOPIA level 2 signal (TxSOC, TxENB, and TxADDR) output from the ATM switch having a UTOPIA level 2 interface which is an ATM standard interface defined by the ATM Forum. 4. The ATM traffic shaping apparatus according to claim 1, wherein the TxADDR to which the received cell belongs is detected and a corresponding cell reception signal corresponding to the TxADDR is output. The response signal returning means validates the output available signal at a shaping rate setting period set from the outside, and invalidates the output available signal when receiving the corresponding cell reception signal outputted from the cell detecting means. And a selector that selects one of the plurality of available signals using the TxADDR as a selection signal and outputs it as a TxCLAV signal of the UTOPIA level 2 signal to the ATM switch. The ATM traffic shaping device according to claim 1, wherein the ATM traffic shaping device is included. The available output control circuit includes a frequency division counter that divides a clock, a frequency division number M (M is a positive integer) set by the shaping rate setting, and a counter value L (L is a positive value) of the frequency division counter. A comparator that outputs a match pulse when they match, an up / down counter that counts down with the match pulse and up counts with the corresponding cell reception signal, and a counter value T (T Is a 0 or a positive integer) and a comparator for comparing the threshold value set from the outside, and as a result of comparison by the comparator, when T is less than the threshold value, it is set and the output available signal can be received. The response signal indicating that the output available signal cannot be received is reset when T is equal to or greater than the threshold as a result of the comparison by the comparator. By providing the S-R circuit, the available signal is dynamically enabled or disabled so that the cell rate of the corresponding cell output from the ATM switch matches the shaping cell rate set by the shaping rate setting. 6. The ATM traffic shaping apparatus according to claim 5, wherein control is performed. 7. The ATM traffic shaping apparatus according to claim 4, wherein the TxADDR and the virtual path of the shaping unit are assigned one-to-one. The ATM traffic shaping device according to any one of claims 4 to 6, wherein the TxADDR and a virtual channel in a shaping unit are assigned one-to-one. 7. The ATM traffic shaping apparatus according to claim 4, wherein the TxADDR and a PHY device in a shaping unit are assigned in a one-to-one relationship.

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