JP2858548B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit that reduces switching noise in a vertically stacked multistage circuit.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit having a vertically stacked multistage circuit structure will be described below with reference to FIG.

Referring to FIG. 7, an output terminal Y is connected to a higher power supply terminal GND via a resistor R1, and an output terminal Z is connected to a higher power supply terminal GND via a resistor R2.

A collector of a bipolar transistor (also simply referred to as a "transistor") Q1 is connected to an output terminal Y, a base is connected to an input terminal D1, and an emitter is commonly connected to an emitter of the bipolar transistor Q2 at a node (node) E101. And the bipolar transistor Q2
Is connected to the output terminal Z, the base is connected to the reference power supply terminal VR1, and the bipolar transistors Q1 and Q2 of the differential pair constitute a first current switch 101.

The collector of the bipolar transistor Q3 is connected to the output terminal Y, the base is connected to the input terminal D2, the emitter is commonly connected to the emitter of the bipolar transistor Q4 at a node E102, and the collector of the bipolar transistor Q4 is connected to the output. The base is connected to the reference power supply terminal VR1, and the bipolar transistors Q3 and Q4 are connected to the second current switch 102.
Is composed.

The collector of bipolar transistor Q5 is connected to node E101, the base is connected to input terminal S1, the emitter is commonly connected to the emitter of bipolar transistor Q6 at node E201, and the collector of bipolar transistor Q6 is connected to node E102. The base is connected to the reference power supply terminal VR2. A third current switch 2 is formed by bipolar transistors Q5 and Q6.
01, and the node E201 is connected to the lower power supply terminal VEE via the current source Ics.

The path of the current of the current source Ics is switched by the third current switch 201, and the input terminal S1
When a high level is input, the current flows through the bipolar transistor Q5, and when a low level is input, the current flows through the transistor Q6.

When a high level is input to the input terminal S1 and the current is switched to the transistor Q5 side, the current is further switched by the first current switch 101.

When a high-level signal is input to the input terminal D1, a current flows through the transistor Q1 and the resistor R
Due to the potential drop of 1, a low level is output to the output terminal Y and a high level is output to the output terminal Z.

On the other hand, when a low level is input to the input terminal D1, a current flows through the transistor Q2, a low level is output to the output terminal Z due to a potential drop of the resistor R2, and a high level is output to the output terminal Y. The level is output.

When a low level is input to the input terminal S1 and the current is switched to the transistor Q6 side, the current is further switched by the second current switch 102.

When a high level is input to the input terminal D2, a current flows through the transistor Q3, and a low level is output to the output terminal Y and a high level is output to the output terminal Z due to the potential drop of the resistor R1. Is done.

When a low level is input to the input terminal D2, a current flows through the transistor Q4, and a low level is output to the output terminal Z due to a potential drop of the resistor R2.
The output terminal Y outputs a high level.

By the above-described circuit operation, the circuit shown in FIG. 7 is configured such that when a high level is input to the input terminal S1,
The data input to the input terminal D1 is output to the output terminal Z, its inverted output is output to the output terminal Y, and the input terminal S
When a low level is input to the terminal 1, the data input to the input terminal D2 is output to the output terminal Z, and the inverted output thereof is output to the output terminal Y.

A circuit in which a current switched by one current switch is switched by a current switch arranged in another hierarchy is called a vertically stacked multi-stage circuit.

In a vertically stacked multi-stage circuit, the first-stage current switch as viewed from the higher power supply terminal GND is a vertically-stacked one-stage portion, and the second-stage current switch is a vertically-stacked two-stage portion. Is similarly defined.

A circuit having only a vertically stacked one-stage current switch is defined as a vertically-stacked one-stage circuit, and a circuit having vertically-stacked one-stage and two-stage current switches is defined as a vertically-stacked two-stage circuit.
A three-stage circuit is defined in the same manner for a vertically stacked three-stage circuit.

According to this definition, the circuit shown in FIG. 7 is a vertically stacked two-stage circuit, and the first and second current switches 101,
102 is a vertically stacked one-stage section, and a third current switch 201
Corresponds to a vertically stacked two-stage portion. ECL for vertically stacked multi-stage circuits
(Emitter Coupled Logic), CM
L (Current Mode Logic).

FIG. 8 shows a conventional circuit of a vertically stacked three-stage circuit.

Referring to FIG. 8, output terminal Y is connected to a higher power supply terminal GND via a resistor R1, and output terminal Z is connected to a higher power supply terminal GND via a resistor R2.

The collector of bipolar transistor Q1 is connected to output terminal Y, the base is connected to input terminal D1, the emitter is commonly connected to the emitter of bipolar transistor Q2 at node E101, and the collector of bipolar transistor Q2 is connected to output terminal Z. , And the base is connected to the reference power supply terminal VR1.

The bipolar transistors Q1 and Q2 constitute a first current switch 101 of a vertically stacked one-stage portion.

The collector of bipolar transistor Q3 is connected to output terminal Y, the base is connected to input terminal D2, the emitter is commonly connected to the emitter of bipolar transistor Q3 at node E102, and the collector of bipolar transistor Q4 is connected to output terminal Z. , And the base is connected to the reference power supply terminal VR1.

The bipolar transistors Q3 and Q4 constitute a second current switch 102 in a vertically stacked one-stage section.

The collector of bipolar transistor Q5 is connected to output terminal Y, the base is connected to input terminal D3, the emitter is commonly connected to the emitter of bipolar transistor Q6 at node E103, and the collector of bipolar transistor Q6 is connected to output terminal Z. , And the base is connected to the reference power supply terminal VR1.

Bipolar transistors Q5 and Q6 constitute a third current switch 103 of a vertically stacked one-stage portion.

The collector of bipolar transistor Q7 is connected to output terminal Y, the base is connected to input terminal D4, the emitter is commonly connected at node E104 to the emitter of bipolar transistor Q8, and the collector of bipolar transistor Q8 is connected to output terminal Z. , And the base is connected to the reference power supply terminal VR1.

A fourth current switch 104 of a vertically stacked one-stage portion is constituted by the bipolar transistors Q7 and Q8,

The collector of bipolar transistor Q9 is connected to node E101, the base is connected to input terminal S1, the emitter is commonly connected to the emitter of bipolar transistor Q10 at node E201, and the collector of bipolar transistor Q10 is connected to node E102. And
The base is connected to the reference power supply terminal VR2.

Bipolar transistors Q9 and Q10 constitute a vertically stacked two-stage current switch 201.

The collector of bipolar transistor Q11 is connected to node E103, the base is connected to input terminal S1, the emitter is commonly connected to the emitter of bipolar transistor Q12 at node E202, and the collector of bipolar transistor Q12 is connected to node E104. The base is connected to the reference power supply terminal VR2.

The bipolar transistors Q11 and Q12 form a vertically stacked two-stage current switch 202.

The collector of bipolar transistor Q13 is connected to node E201, the base is connected to input terminal S2, the emitter is commonly connected at node E301 to the emitter of bipolar transistor Q14, and the collector of bipolar transistor Q14 is connected to node E202. The base is connected to the node VR3.

The bipolar transistors Q13 and Q14 form a vertically stacked three-stage current switch 301.

The collector of the bipolar transistor Q15 is connected to the higher power supply GND, the base is connected to the reference power supply terminal VR2, and the emitter is connected to the node VR3.

The node VR3 is connected to the lower power supply terminal VEE via the current source Ics2, and the node E301 is connected to the current source Ics2.
It is connected to the lower power supply terminal VEE via cs.

The path of the current of the current source Ics is switched by a vertically stacked three-stage current switch 301. When a high level is input to the input terminal S2, the transistor Qs
When the low level is input, the current flows through the transistor Q14.

When a high level is input to the input terminal S2 and the current is switched to the transistor Q13 side, the current is further switched by the vertically stacked two-stage current switch 201 and the vertically stacked one-stage current switch 101 or 102.

The vertically stacked two-stage current switch 201 and the vertically stacked one-stage current switches 101 and 102 are shown in FIG.
1 has the same configuration as that of the circuit shown in FIG.

When a low level is input to the input terminal S2 and the current is switched to the transistor Q14 side, the current is further switched by the vertical stacked two-stage current switch 202 and the vertical stacked single-stage current switches 103 and 104. Vertical stacking two-stage current switch 202 and vertical stacking 1
The step current switches 103 and 104 have the same configuration as the circuit shown in FIG. 7 and perform the same current path switching operation.

By the above-described circuit operation, the circuit shown in FIG. 8 outputs the input to the input terminal D1 to the output terminal Z when the high level is input to both the input terminals S1 and S2, and outputs the inverted output thereof. Is output to the output terminal Y.

When a low level and a high level are input to the input terminals S1 and S2, respectively, the input to the input terminal D2 is output to the output terminal Z, the inverted output thereof is output to the output terminal Y, and the input terminal S1 , S2, the input to the input terminal D3 is output to the output terminal Z, and the inverted output is output to the output terminal Y.

When a low level is input to both the input terminals S1 and S2, the input to the input terminal D4 is changed to the output terminal Z.
And the inverted output thereof is output to the output terminal Y.

[0044]

In the conventional vertically stacked two-stage circuit shown in FIG. 7, when the input signal of the input terminal S1 is switched from the high level to the low level, the output of the output terminal Z is output to the input terminal D1. The input signal changes to an input signal to the input terminal D2. At this time, if a low level is input to both the input terminals D1 and D2, the output signal of the output terminal Z does not change and remains at the low level. However, positive pulse noise may occur in the low level output.

When a low level is input to the input terminals D1 and D2 and the input signal at the input terminal S1 is switched from a high level to a low level, the current switches from the path of the transistor Q2 → Q5 to the path of the transistor Q4 → Q6. .

At this time, the load capacitance of the node E102 and the transistor Q
A current is consumed to discharge the parasitic capacitance of No. 4 and the current flowing through the resistor R2 transiently decreases to reduce the amount of potential drop, thereby generating positive pulse noise.

In the conventional vertically stacked three-stage circuit shown in FIG. 8, when a low level is input to the input terminals D1 and D4 and the input signals of the input terminals S1 and S2 are simultaneously switched from the high level to the low level, the output terminal Z Output is expected to be low, but current is consumed to discharge the load capacitance of the nodes E104 and E202 and the parasitic capacitance of the transistors Q8 and Q12.
The current in the resistor R2 transiently decreases and the amount of potential drop decreases, thereby generating positive pulse noise.

At this time, the current flows through the transistors Q2 → Q9 →
From the path of Q13, the transistors Q8 → Q12 → Q14
However, in the vertically stacked three-stage circuit, there are more places to be discharged than in the vertically stacked two-stage circuit, and a larger amount of current is consumed by discharging the capacitance. , The noise also increases.

FIG. 9 is a waveform diagram showing an example of noise generated in the circuit shown in FIG. Referring to FIG. 8, input terminal D1
When the low level is input to D4 and the input signals of the input terminals S1 and S2 are simultaneously switched from the high level to the low level, the output terminal Z is expected to output a low level.
A large noise is generated as indicated by a two-dot chain line (indicated by Z) in the figure.
It exceeds R1 and is recognized as high level.

When such noise is input to, for example, a clock of a flip-flop, the noise is recognized as a clock signal, and there is a risk that a circuit malfunctions.

As described above, the generation of noise is caused by the fact that the current is consumed to discharge the capacitance on the path when the current path is switched, and the current in the output section decreases transiently. If the amount of electric discharge can be reduced, noise can be reduced.

In the current switch in which a current flows, the potential of the node to which the emitters of the transistors constituting the current switch are connected in common is set to a high level at the base which is the input terminal among the transistors constituting the current switch. Is lower than the base potential of the transistor through which the current flows by the input by the base-emitter voltage V _BE corresponding to the current flowing through the transistor.

Since the base-emitter voltage V _BE of a transistor through which no current flows is smaller than the base-emitter voltage V _BE of a transistor through which current flows, a current switch through which no current flows is used. Is that the potential of the node to which the emitters of the transistors constituting the current switch are connected in common is raised compared to the corresponding portion of the current switch in which current is flowing (the node to which the emitters of the transistors are connected in common). , More current is consumed to discharge the load capacitance at that node.

Therefore, the present invention solves the above problems,
An object of the present invention is to provide a semiconductor integrated circuit having a vertically stacked multi-stage configuration that reduces switching noise by reducing a current consumed by discharging a capacitor when switching a current path.

[0055]

In order to achieve the above object, the present invention provides a current source having one end connected to a low potential side power source.
And a second current switch for switching a current path to the current switch, and the current switch group switches the current path .
Load resistor that carries current and has one end connected to the high-potential-side power supply
And at least a collector of one bipolar transistor constituting the second current switch is connected to a node to which an emitter of the bipolar transistor constituting the first current switch is commonly connected. Type circuit configuration, a constant voltage generation circuit,
An anode connected to the node, the cathode comprises a diode connected to said constant voltage generating circuit, the node
Circuit to prevent the potential of
A semiconductor integrated circuit having a path .

According to the present invention , one end is connected to the low potential side power supply.
First and second current switches for switching a current path to a current source , and switching by the current switch group
The obtained current flows and one end is connected to the high-potential side power supply.
A load resistor element, and a collector of one bipolar transistor forming the second current switch is connected to a node to which an emitter of the bipolar transistor forming the first current switch is commonly connected. It has a vertically stacked circuit configuration and generates a constant voltage.
And the circuit, a base connected to the node, the collector is high electrostatic
Is connected to a position-side power supply, it includes a bipolar transistor having an emitter connected to said constant voltage generating circuit, wherein the node
A clamp that prevents the potential of a point from exceeding a predetermined potential
To provide a semiconductor integrated circuit, comprising a circuit.

According to the present invention , one end is connected to the low potential side power supply.
First and second current switches for switching a current path to a current source , and switching by the current switch group
The obtained current flows and one end is connected to the high-potential side power supply.
And a load resistor element , wherein a drain of one MOS transistor forming the second current switch is connected to a node to which a source of the MOS transistor forming the first current switch is commonly connected. is a circuit configuration of a vertically stacked-type, and the constant voltage generating circuit, the anode is connected to the node, the cathode comprises a diode connected to said constant voltage generating circuit, the nodes
Provided is a semiconductor integrated circuit having a clamp circuit for preventing a potential from becoming equal to or higher than a predetermined potential .

According to the present invention , one end is connected to the low potential side power supply.
First and second current switches for switching a current path to a current source , and switching by the current switch group
The obtained current flows and one end is connected to the high-potential side power supply.
And a load resistor element , wherein a drain of one MOS transistor forming the second current switch is connected to a node to which a source of the MOS transistor forming the first current switch is commonly connected. is a circuit configuration of a vertically stacked-type, includes a constant voltage generation circuit, a base connected to the node, a collector connected to the high potential side power supply, a bipolar transistor having an emitter connected to said constant voltage generating circuit, the , The potential of the node
There is provided a semiconductor integrated circuit having a clamp circuit for preventing the potential from becoming higher than a predetermined potential .

According to the present invention , one end is connected to the low potential side power supply.
Current source and bipolar transistor pair or MOS
A current switch composed of a pair of transistors. In a bipolar transistor, an emitter, a collector, a base, and in a MOS transistor, a source, a drain, and a gate serve as a first signal terminal, a second signal terminal, and a control terminal, respectively . the transistors connected in common said first signal terminals of the pair to each other, and first and second current switch for switching the current path to the current source based on a signal potential applied to the control terminal, said Karen
Flow the current switched by the
At least the load resistance element connected to the high-potential-side power supply.
And a transformer constituting the first current switch.
At the node where the first signal terminals of the transistor are commonly connected,
One transistor constituting the second current switch
Vertical type circuit formed by connecting the second signal terminal of
If the potential of the node is equal to or higher than a predetermined potential,
The present invention provides a semiconductor integrated circuit having a clamp means for clamping current so as to suppress current consumed in discharging from a capacitor associated with the node when switching a current path.

[0060]

According to the present invention, the discharge current transiently consumed at the time of switching the current path is reduced by clamping the potential of the node to which the emitter of the transistor constituting the current switch is connected in common. Significant reduction of noise generated at the time of switching is achieved.

[0061]

Embodiments of the present invention will be described below with reference to the drawings.

[0062]

Embodiment 1 FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

Referring to FIG. 1, output terminal Y is connected to higher power supply terminal GND via resistor R1, and output terminal Z is connected to higher power supply terminal GND via resistor R2. The collector of the bipolar transistor Q1 is connected to the output terminal Y, the base is connected to the input terminal D1, the emitter is commonly connected to the emitter of the bipolar transistor Q2 at a node E101, and the bipolar transistor Q2
Is connected to the output terminal Z, the base is connected to the reference power supply terminal VR1, and the bipolar transistors Q1 and Q2 of the differential pair constitute a first current switch 101 of a vertically stacked one-stage portion.

The collector of bipolar transistor Q3 is connected to output terminal Y, the base is connected to input terminal D2, the emitter is commonly connected to the emitter of bipolar transistor Q4 at node E102, and the collector of bipolar transistor Q4 is connected to output terminal Z. , The base is connected to the reference power supply terminal VR1, and the bipolar transistors Q3 and Q4 of the differential pair constitute a second current switch 102 of a vertically stacked one-stage portion.

The collector of bipolar transistor Q5 is connected to node E101, the base is connected to input terminal S1, the emitter is commonly connected to the emitter of bipolar transistor Q6 at node E201, and the collector of bipolar transistor Q6 is connected to node E102. The base is connected to the reference power supply terminal VR2, and the bipolar transistors Q5 and Q6 are connected to a vertically stacked two-stage current switch 2
01, and a differential pair of bipolar transistors Q5,
A node E201, which is a common connection point of the emitters of Q6, is connected to the lower power supply terminal VEE via the current source Ics.

In this embodiment, the node E101, which is the common connection point of the emitters of the bipolar transistors Q1 and Q2 forming the first current switch, and the constant voltage generation circuit 401 are connected to the anode of the first diode DI2. And a cathode. Further, the bipolar transistor Q forming the second current switch
The second diode DI1 is connected to a node E102, which is a common connection point of the emitters of the transistors Q3 and Q4, and the constant voltage generation circuit 401.
Are connected to each other.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described with reference to FIG.

According to the present embodiment, in the vertically stacked single-stage current switches 101 and 102 in which current does not flow to one side due to the input of the input terminal S1, the node to which the emitters of the transistors constituting the current switches are commonly connected Is connected to the constant voltage generating circuit 401 via a diode, so that the potentials of the nodes E101 and E102 are changed from the potential of the constant voltage generating circuit 401 to the anodes where the first and second diodes DI1 and DI2 are turned on. When the voltage rises above the voltage between the cathodes, the diode turns on and a current flows to prevent the potential from rising.

For this reason, the current consumed for discharging the load capacitance of the nodes E101 and E102 when the current path is switched can be reduced, and the noise generated at the time of switching can be suppressed.

[0070]

FIG. 2 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

Referring to FIG. 2, output terminal Y is connected to higher power supply terminal GND via resistor R1, and output terminal Z is connected to higher power supply terminal GND via resistor R2. The collector of the bipolar transistor Q1 is connected to the output terminal Y, the base is connected to the input terminal D1, the emitter is commonly connected to the emitter of the bipolar transistor Q2 at a node E101, and the bipolar transistor Q2
Is connected to the output terminal Z, the base is connected to the reference power supply terminal VR1, and the first current switch 101 of the vertically stacked one-stage portion is connected by the bipolar transistors Q1 and Q2.
Is composed.

The collector of bipolar transistor Q3 is connected to output terminal Y, the base is connected to input terminal D2, the emitter is commonly connected to the emitter of bipolar transistor Q4 at node E102, and the collector of bipolar transistor Q4 is connected to output terminal Z. And the base is connected to the reference power supply terminal VR1, and the bipolar transistors Q3 and Q4 constitute a second current switch 102 of a vertically stacked one-stage portion.

The collector of bipolar transistor Q5 is connected to node E101, the base is connected to input terminal S1, the emitter is commonly connected to the emitter of bipolar transistor Q6 at node E201, and the collector of bipolar transistor Q6 is connected to node E102. The base is connected to the reference power supply terminal VR2, and the bipolar transistor Q5 and Q6 form a vertically stacked two-stage current switch 2
No. 01, and a node E201 which is a common connection point of the emitters of the bipolar transistors Q5 and Q6 is connected to a current source Ics.
To the lower power supply terminal VEE.

In this embodiment, the base of the bipolar transistor Q7 is connected to the node E101, the collector is connected to the higher power supply terminal GND, and the emitter is connected to the constant voltage generating circuit 401. The base of the bipolar transistor Q8 is connected to the node E102, the collector is connected to the higher power supply terminal GND, and the emitter is connected to the constant voltage generation circuit 401.

Next, the operation of the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIG.

The semiconductor integrated circuit of this embodiment has an input terminal S
In the vertically stacked single-stage current switches 101 and 102 in which a current does not flow to one of them due to the input of 1, the nodes E101 and E102 to which the emitters of the transistors constituting the current switch are commonly connected are connected. Are connected to the bases of the transistors Q7 and Q8 connected to the nodes E101 and E102.
Is higher than the potential of the constant voltage generation circuit 401 by the voltage between the base and the emitter that turns on the transistors Q7 and Q8, the transistor is turned on and current flows to prevent the potential from rising. Therefore, the current consumed for discharging the load capacitance of the nodes E101 and E102 at the time of switching the current path can be reduced, and the generated noise can be suppressed.

In the circuit of this embodiment shown in FIG. 2, only the base current flows from the circuit side at the time of level adjustment when the levels of the nodes E101 and E102 rise, and the influence on the original circuit operation is affected by the above-described circuit. It is smaller than the circuit of the first embodiment.

FIG. 3 shows a vertical stack 3 according to the second embodiment.
It is a figure showing an example of the circuit composition which constituted the stage circuit.

Referring to FIG. 3, the present embodiment has a circuit configuration obtained by applying the configuration of the second embodiment shown in FIG. 2 to the conventional circuit shown in FIG. In addition to the configuration shown, there is provided a constant voltage generating circuit 401 which outputs a node VR4 connected via a resistor R3 to a node VR3 having a reference potential of a vertically stacked three-stage portion, and has bases of nodes E101 and E10.
2, Q103 and E104, respectively, the collectors of which are commonly connected to the higher power supply terminal GND, and the emitters of which are commonly connected to the node VR4.
7, Q18 and Q19.

In the present embodiment shown in FIG.
By suppressing the rise in the potential of 102, E103, and E104, the discharge current is reduced and noise is reduced. FIG. 4 is a waveform diagram showing operation waveforms of the present embodiment shown in FIG. 3, and corresponds to FIG. 9 which is a waveform diagram showing an operation example of the conventional circuit shown in FIG.

FIG. 4 is compared with FIG. 9, and in this embodiment, the noise at the output terminal Z when the input terminals S1 and S2 are switched from high level to low level is larger than that in the conventional example. Has been reduced.

[0082]

Third Embodiment FIG. 5 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

Referring to FIG. 5, the present embodiment has a configuration in which all the bipolar transistors constituting the current switches of the semiconductor integrated circuit of the first embodiment shown in FIG. 1 are replaced with MOS transistors. .

In this embodiment, the same operation as in the first embodiment is performed, and the description is omitted.

[0085]

Embodiment 4 FIG. 6 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

Referring to FIG. 6, the present embodiment has a configuration in which a bipolar transistor constituting a current switch of the semiconductor integrated circuit of the second embodiment shown in FIG. 2 is replaced with a MOS transistor. An operation similar to that of the second embodiment is performed.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principles of the present invention.

[0088]

As described above, the semiconductor integrated circuit of the present invention clamps the potential of the node to which the emitter of the transistor constituting the current switch is connected in common, so that the transient occurs when the current path is switched. This has the effect of suppressing the discharge current consumed during the switching operation and greatly reducing the noise generated during switching.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 shows a vertical stack 3 using the configuration of the second embodiment of the present invention.
It is a circuit diagram showing an example of a stage circuit.

FIG. 4 is a waveform chart showing an example of the operation of the second embodiment (the semiconductor integrated circuit shown in FIG. 3) of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 8 is a circuit diagram showing an example of a three-stage vertically stacked circuit using a conventional semiconductor integrated circuit.

9 is a waveform chart showing an example of the operation of the semiconductor integrated circuit shown in FIG.

[Explanation of symbols]

Q1, Q2,..., Q19 Bipolar transistors M1, M2,. , D2, D3, D4, S1, S2 input terminals Z, Y output terminals E101, E102, E103, E104, E201,
E202, E301, VR3, VR4 Nodes 101, 102, 103, 104 Vertically stacked one-stage current switch 201, 202 Vertically stacked two-stage current switch 301 Vertically stacked three-stage current switch 401 Constant voltage generation circuit

Claims (5)

(57) [Claims] 1. A first and second current switch for switching the current path to the current source having one end to the low potential side power supply is connected, the flow of cut conversion the obtained current by a current switch group, the high end A load resistance element connected to a potential side power supply, and a bipolar transistor forming the second current switch at a node where the emitter of the bipolar transistor forming the first current switch is commonly connected. And a constant voltage generating circuit, a diode having an anode connected to the node, and a cathode connected to the constant voltage generating circuit. A semiconductor integrated circuit having a clamp circuit for preventing a potential from becoming higher than a predetermined potential. First and second current switch for switching the current path to 2. A current source having one end to the low potential side power supply is connected, the flow of cut conversion the obtained current by a current switch group, the high end A load resistance element connected to a potential side power supply, and a bipolar transistor forming the second current switch at a node where the emitter of the bipolar transistor forming the first current switch is commonly connected. And a constant voltage generating circuit, a base is connected to the node, a collector is connected to a high potential side power supply, and an emitter is connected to the constant voltage generating circuit. And a clamp circuit that prevents the potential of the node from being equal to or higher than a predetermined potential. Semiconductor integrated circuit. First and second current switch for switching the current path to 3. A current source having one end to the low potential side power supply is connected, the flow of cut conversion the obtained current by a current switch group, the high end A load resistance element connected to a potential side power supply, and a MOS transistor forming the second current switch is connected to a node to which a source of the MOS transistor forming the first current switch is commonly connected. A drain connected to the vertical stack type circuit configuration, comprising: a constant voltage generating circuit; a diode having an anode connected to the node, and a cathode connected to the constant voltage generating circuit; A semiconductor integrated circuit having a clamp circuit for preventing a potential from becoming higher than a predetermined potential. First and second current switch for switching the current path to 4. A current source having one end to the low potential side power supply is connected, the flow of cut conversion the obtained current by a current switch group, the high end A load resistance element connected to a potential side power supply, and a MOS transistor forming the second current switch is connected to a node to which a source of the MOS transistor forming the first current switch is commonly connected. A constant voltage generating circuit, a base is connected to the node, a collector is connected to the high potential side power supply, and an emitter is connected to the constant voltage generating circuit. A bipolar transistor, and a clamp circuit for preventing the potential of the node from being higher than a predetermined potential. Integrated circuit. 5. A current source having one end connected to a low potential side power source.
And a current switch composed of a bipolar transistor pair or a MOS transistor pair, wherein the bipolar transistor has an emitter, a collector, a base,
In the S transistor, a source, a drain, a gate, its
Respectively a first signal terminal, a second signal terminal, a control terminal, said transistor connected in common said first signal terminals of the pair to each other, the current source based on a signal potential applied to the control terminal To switch the current path to
2 and a current switched by the current switch group.
And a load resistance element having one end connected to the high potential side power supply,
And at least one of the transistors forming the first current switch
The second signal terminal is commonly connected to the node where the second signal terminal is connected to the second signal terminal.
Of the transistor constituting the current switch of
A vertically stacked circuit configuration in which a second signal terminal is connected;
Is, class a potential of the node, so as not to or greater than the predetermined potential
Clamp to suppress the current consumed in discharging from the capacitance associated with the node when switching the current path
A semiconductor integrated circuit comprising means .