JP3464864B2 - ECL logic circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an ECL (Emitter-Emitter).
Coupled Logic) Concerning a logic circuit.

[0002]

2. Description of the Related Art The structure of a conventional ECL logic circuit is shown in FIG. A resistor 3 and npn are provided between the ground terminal and the node N1.
Type bipolar transistor 2 and resistor 4 and npn type bipolar transistor 5 are connected in parallel to form a transistor differential pair. The base of the transistor 2 is connected to the input terminal 2 which receives an input signal from the outside, and the base of the transistor 5 is connected to the constant voltage source 6. A constant current source having an npn-type bipolar transistor 7, a constant voltage source 10, and a resistor 8 and connected to a constant voltage source 9 is connected to the node N1.

Further, the collector and the emitter of the npn type bipolar transistor 11 are connected between the ground terminal and the output terminal 12, respectively, and the npn type bipolar transistor 13 and the resistor 14 are connected between the output terminal and the constant voltage source 9.
Are connected to form a constant current source. Transistor 7
The constant voltage source 10 is connected to the bases of the transistors 13 and 13. As a result, a current Ics1 flows between the node N1, the transistor 7, the resistor 8 and the constant voltage source 9, and a current Ics2 flows between the transistors 11 and 13, the resistor 14 and the constant voltage source 9. The output terminal 12 is connected to the load capacitance 15 of the circuit to be driven.

For example, from -1.6V to-
An input signal in the range of 0.8V is input. Reference potential Vref corresponding to the intermediate potential -1.2 V of this input signal
Are supplied to the base of the transistor 5. Reference potential V
When the input signal VH higher than ref is input, the transistor 2 is turned on and the transistor 5 is turned off. Of the resistors 3 and 4, current flows only in the resistor 3 and the transistor 1
The base potential of 1 maintains the ground potential. The output terminal 12 is at the base-emitter potential -VBE, and the transistor 1
1, the load capacity 15 is charged.

When the load capacitance 15 is completely charged, no current flows through the output terminal 12, but the current flows through the transistors 11 and 13, the resistor 14 and the constant voltage source 9.

When the input signal VL lower than the reference potential Vref is input to the input terminal 1, the transistor 2 is turned off and the transistor 5 is turned on. The current Ics1 flows through the resistor 4 having the resistance value R1 among the resistors 3 and 4, and the transistor 11
The base potential of the transistor drops to -VBE-R1.Ics1 and the transistor 11 is turned off. The electric charge accumulated in the load capacitance 15 is extracted to the transistor 13 via the output terminal 12 and discharged.

However, the conventional ECL logic circuit has the following problems. The rising edge of the waveform of the signal output from the output terminal 12 is determined by the current flowing through the load capacitor 15. Therefore, in order to make the output waveform steep, it is necessary to increase the current flowing through the base of the transistor 11. Further, the fall of the output waveform is determined by the speed at which the charge is discharged from the load capacitance 15. This discharge rate is the collector current Ics2 of the transistor 13.
Since it depends on the time constant determined by the load capacitance CL, the collector current Ics2 must be increased in order to accelerate the falling speed of the output waveform.

However, like the transistor 7, the transistor 13 is always on because the constant voltage source 10 is connected to the base. Therefore, if the collector current of the transistor 13 is increased, the current consumption increases. Therefore, the circuit shown in FIG. 3 cannot increase the operating speed without increasing the current consumption.
Further, when the size of the transistor 13 is increased, a large current flows when the transistor 13 is turned on, which causes a ringing in the output.

FIG. 4 shows the configuration of another conventional ECL logic circuit. Both ends of the npn-type bipolar transistor 26 are connected between the ground terminal and the output terminal 12, and the collector and the emitter of the transistor 27 are connected between the emitter of the transistor 26 and one end of the constant voltage source 9, respectively. The base of the transistor 26 is connected between the resistor 4 and the collector of the transistor 5, and the base of the transistor 27 is connected to the connection point between the resistor 3 and the collector of the transistor 2 via the capacitor 21.

A constant voltage source 22, between the ground terminals,
The clamp circuit 23, the resistor 24, and the constant voltage source 25 are connected in series. The connection point between the clamp circuit 23 and the resistor 24 is connected to the base of the transistor 27. The other elements that are the same as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

In the circuit of FIG. 3, a constant power supply voltage output from the constant voltage source 10 is applied to the base of the transistor 13 and is always on, which causes an increase in current consumption.

On the other hand, in the circuit of FIG. 4, a small amount of current flows in the transistor 27 in the steady state, and the transistor 27 is discharged only when the output waveform falls, that is, when the charge accumulated in the load capacitance 15 is discharged. I'm trying to allow current to flow.

When the high level input signal VH is input, the transistor 2 is turned on and the transistor 5 is turned off. The potential at the connection point between the resistor 3 and the collector of the transistor 2 drops. The constant voltage output from the clamp circuit 23 and applied to the base of the transistor 27 in a steady state is set to be slightly lower than the voltage at which the transistor 27 turns on. Therefore, at this time, the transistor 2
7 does not turn on. The transistor 26 turns on and the load capacitance 15 is charged.

When the input signal changes from the high level VH to the low level VL, at that moment, the resistor 3 and the transistor 2
The potential at the connection point with the collector of rises. This potential change is applied to the base of the transistor 27 via the capacitor 21. As a result, the transistor 27 is turned on and the electric charge accumulated in the load capacitance 15 is discharged.

As described above, in the circuit of FIG. 4, since the transistor 27 is turned on and the current from the capacitor 15 flows only at the moment when the input signal changes from the high level to the low level, the current consumption is reduced.

However, since a momentary large current flows through the transistor 27, ringing occurs in the output waveform and other circuits connected to the output terminal 12 malfunction due to fluctuations in the power supply voltage and the ground voltage. was there. Further, in the circuit of FIG. 4, circuits such as the capacitor 21, the constant voltage sources 22 and 25, and the clamp circuit 23 must be added, and in order to accelerate the falling speed of the output waveform, the capacitance of the capacitor 21 must be increased. It is necessary to increase the value, resulting in an increase in element area and an increase in cost. In particular, in a semi-custom integrated circuit such as a gate array, a great limitation is placed on the arrangement and wiring of elements.

[0017]

As described above, the conventional ECL logic circuit shown in FIG. 3 cannot realize high speed and low power consumption, and the circuit shown in FIG. It was causing an increase.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an ECL logic circuit capable of reducing power consumption at high speed while suppressing an increase in element area.

[0019]

The ECL logic circuit of the present invention is provided with an input signal and a reference voltage, and outputs a first signal that changes according to the potential difference between the input signal and the reference voltage. An output emitter whose collector is connected to a dynamic pair amplifier and a ground terminal, and which receives the first signal output from the differential pair amplifier to its base to change the potential of an output terminal connected to the emitter. A follower transistor,
A collector is connected to the output terminal, the reference voltage is input to the base, and the emitter is connected to the emitter of the transistor pair included in the differential pair amplifying unit.

Alternatively, in the ECL logic circuit of the present invention, the collector is connected to the ground terminal via the first resistor, the base is connected to the input terminal for inputting an input signal, and the emitter is connected to the first node. A first bipolar transistor, a second bipolar transistor having a collector connected to a ground terminal via a second resistor, a reference voltage input to a base, and an emitter connected to the first node; A constant current source connected between the first node and the constant voltage source, a collector is connected to the ground terminal, a base is connected to the collector of the second bipolar transistor, and an emitter is connected to the output terminal. A collector is connected to the third bipolar transistor and the output terminal,
A fourth bipolar transistor having the base supplied with the reference voltage and having the emitter connected to the first node is provided.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

The ECL logic circuit according to the present embodiment has a configuration as shown in FIG.

A resistor 3 and an npn-type bipolar transistor 2 connected in series and a resistor 4 and an npn-type bipolar transistor 5 connected in series are connected in parallel between the ground terminal and the node N11 to form a node N11. A constant current source having an npn-type bipolar transistor 7 having a constant voltage source 10 connected to its base and a resistor 8 is connected between the constant voltage source 9 and the constant voltage source 9. The base of the transistor 2 is connected to the input terminal 1 to which an input signal of high level VH or low level VL is input, and the base of the transistor 5 is connected to a constant voltage source 6 which outputs a reference voltage Vref.

The collector and emitter of the npn bipolar transistor 11 are connected between the ground terminal and the output terminal 12, and npn is provided between the output terminal 12 and the node N11.
The collector and emitter of the bipolar transistor 13 are connected to each other. The base of the transistor 11 is a resistor 4
And the node N12 connecting the collector of the transistor 5
The base of the transistor 13 is connected to the constant voltage source 6
It is connected to the. A load capacitance 14 is connected to the output terminal 12.

When a high level VH input signal is input to the input terminal 1, only the transistor 2 of the transistors 2 and 5 is turned on. Transistors 5 and 13 are both off. The node N12, to which the base of the transistor 11 is connected, maintains the ground voltage,
Turns on to charge the load capacitance 14.

When the signal input to the input terminal 1 switches from the high level VH to the low level VL, the transistor 2 is turned off and the transistors 5 and 13 are turned on. Assuming that the emitter areas of the transistor 5 and the transistor 13 are A1 and A2, respectively, A2 / A2 corresponding to the ratio of the emitter areas of the transistor 5 and the transistor 13 at the node N12.
(A1 + A2) × Ics current flows, and transistor 1
The emitter potential of 1 is -VBE-R · Ics × A1 / (A1
+ A2), and the transistor 11 is turned off. The charge accumulated in the load capacitance 14 is transferred to the transistor 13
And are discharged via 7.

As described above, according to the present embodiment, the input signal of the transistor 13 for lowering the emitter potential of the output emitter follower transistor is high level VH.
Is turned on only when switching from the low level to the low level VL, and the electric charge accumulated in the load capacitance 14 is discharged. For this reason,
Even if the size of the transistor 13 is set large for speeding up, the power consumption can be reduced as compared with the circuit shown in FIG. 3 in which the transistor 13 is always on. Further, the circuit shown in FIG. 4 requires constant voltage sources 22 and 25, a clamp circuit 23, and a capacitor 21 in addition to the circuit shown in FIG. 3, whereas in the present embodiment, such an element is newly added. It is not necessary to add the element and it is possible to prevent the element area from increasing. In particular, in the case of a semi-custom LSI such as a gate array, in order to realize the circuit of FIG. 4, it is necessary to modify the power supply wiring of what was configured only with a normal ECL logic circuit. It was supposed to give a big restriction. In the present embodiment, such restrictions are not given, and the design efficiency is improved.

Further, the transistor 13 is turned on and the capacitance 1
Even when the charge stored in 4 is discharged, the transistor 5 provided in parallel with the transistor 13 is turned on at the same time and the total current Ics is drawn as a constant current by the transistor 7, so that the transistor 13 is instantaneously supplied to the transistor 13. No large current flows and ringing at the output is prevented.

FIG. 2 shows the result of the simulation of the relationship between the load capacitance and the delay time. The rising delay time of the output signal of the conventional ECL logic circuit shown in FIG. 3 is line L2, the falling delay time is line L1, and the rising delay time of the output signal of the ECL logic circuit according to the present embodiment is line L3. The falling delay time is indicated by line L4.

According to the present embodiment, the current consumption can be suppressed while shortening the fall delay time as compared with the conventional circuit. Further, regarding the rise time, the circuit according to the present embodiment is slightly slower than the conventional circuit of FIG. 3, but in reality, since the average delay time of both the rise and the fall is used, a large fall delay is caused. It is not a delay that has a practical impact due to the shortened time.

The above-described embodiment is an example and does not limit the present invention. For example, although the transistor 7, the constant voltage sources 9 and 10, and the resistor 8 are used as the constant current source in the present embodiment, other configurations may be used as long as they are used as the constant current source.

[0032]

As described above, according to the ECL logic circuit of the present invention, the collector and the emitter are connected between the emitter of the output emitter follower transistor whose collector is connected to the ground terminal and the constant current source, and the difference is provided. By having a transistor whose base is connected to the base of one of the transistors of the dynamic pair amplifier, the transistor whose collector is connected to the output terminal is turned on only when it is necessary to discharge the capacitance connected to the output terminal. It is possible to achieve high speed and reduce current consumption at the same time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an ECL logic circuit according to an embodiment of the present invention.

FIG. 2 is a graph comparing the delay time of the ECL logic circuit with the delay time of the conventional ECL logic circuit.

FIG. 3 is a circuit diagram showing a configuration of a conventional ECL logic circuit.

FIG. 4 is a circuit diagram showing the configuration of another conventional ECL logic circuit.

[Explanation of symbols]

1 input terminal 2, 5, 7, 11, 13 npn type bipolar transistor 3, 4, 8 resistance 6, 9, 10 constant voltage source 12 output terminal 14 load capacitance

Continuation of the front page (56) Reference JP-A-4-82319 (JP, A) JP-A-6-61757 (JP, A) JP-A-59-203296 (JP, A) JP-A-5-29919 (JP , A) JP 3-128526 (JP, A) JP 4-315314 (JP, A) JP 5-37350 (JP, A) SAI 57-195243 (JP, U) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/086 H03F 3/45

Claims (2)

(57) [Claims] 1. A first circuit which is provided with an input signal and a reference voltage and changes in accordance with a potential difference between the input signal and the reference voltage.
Potential of the output terminal connected to the emitter, the collector of which is connected to the ground terminal, the first signal output from the differential pair amplifier is given to the base, An output emitter follower transistor for changing the output voltage, a transistor having a collector connected to the output terminal, inputting the reference voltage to the base, and an emitter connected to the emitter of the transistor pair of the differential pair amplifying section, An ECL logic circuit, comprising: 2. A first bipolar transistor having a collector connected to a ground terminal through a first resistor, a base connected to an input terminal for inputting an input signal, and an emitter connected to a first node. A second bipolar transistor having a collector connected to the ground terminal via a second resistor, a reference voltage input to the base, and an emitter connected to the first node; and the first node and a constant voltage. A constant current source connected to the source, a collector connected to the ground terminal, a base connected to the collector of the second bipolar transistor, and a third bipolar transistor connected to the output terminal for the emitter; A fourth bipolar transistor having a collector connected to the output terminal, the reference voltage input to the base, and an emitter connected to the first node; An ECL logic circuit comprising: