JP2856588B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a ROM, RA having a static read circuit.
M and other semiconductor memory devices.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional semiconductor memory device has an SRAM cell group 1, and a pair of column lines D and D '(an inverted signal line of D) of one cell. The drains of P-channel MOS transistors 6 and 7 for precharging are connected to one end of (). P channel MO
The precharge signal terminal 10 is connected to the gates of the S transistors 6 and 7, and the first power supply 8 is connected to the source. The other end of the column line of the SRAM cell group 1 is connected to the input terminal of the column selector 2. The output terminal of the column selector 2 is connected to the input terminal of the static read circuit 3. A row decoder 4 is connected to a row line C of the SRAM cell group 1, and a column decoder 5 acting as a selection line is connected to the column selector 2. The SRAM cell is 1
Only the number is shown, and the number of the pair of P-channel MOS transistors 6 and 7 and the number of the pair of column lines D and D 'are determined corresponding to the number of cells per column of the SRAM cell group 1, and the row decoder 4 Is determined in accordance with the number of cells per row of the SRAM cell group 1.

In this semiconductor memory device, when a precharge signal (Low) is input to a precharge signal terminal 10 during a precharge period, P-channel MOS transistors 6 and 7 are turned on, and a column line pair of the SRAM cell group 1 is turned on. D and D ′ are charged up to the voltage V _DD applied to the power supply terminal 8. Further, during the precharge period, the output of the column decoder 5 is determined and a pair of column selectors 2 are selected, and the column lines D and D 'of the SRAM cell group 1 and the input terminal of the static read circuit 3 are short-circuited. .

Next, in the read period, the precharge signal terminal 10 is at the voltage V _DD , and in this case, the P-channel MO
The S transistors 6 and 7 are off, and the column line pair is at the voltage V _DD . When the output of the row decoder 4 is determined and one row of SRAM cells is selected, one of the column line pairs is discharged to GND by the data of the SRAM cell group 1.

In this manner, the data of the column line of the SRAM cell at the intersection of the pair of column lines selected by the column selector 2 and the row line selected by the row decoder 4 is input to the static read circuit 3. You. And the column line is V _DD
During the discharge to the ground, the data is latched when the input logical threshold value V _THR of the static read circuit 3 is reached.

In this case, most of the read time is occupied by the time t _R until the column line is discharged from V _DD to V _THR . This time t _R is the total capacity of one column line, C _d ,
When the current capacity of the N-channel MOS transistor of the inverter in the SRAM cell was I _N, represented by _{t R = C d · (V} DD -V THR) / I N.

[0007]

In the conventional semiconductor memory device described above, the column line is connected to V _DD during the read period.
, And from there to the input logic threshold value V _THR of the static read circuit 3, the N-channel MOS transistor of the inverter of the SRAM cell must discharge. In this case, the column line capacitance C _d increases with an increase in the storage capacity of the SRAM cell group 1, and the current capacity I _N of the N-channel MOS transistor of the inverter in the SRAM cell decreases when the area of the SRAM cell group is integrated. Therefore, there is a drawback that enormous reading time is consumed, erroneous data is read before output data is determined, and a malfunction occurs in the entire system.

In view of these drawbacks, the object of the present invention is to
It is an object of the present invention to shorten the discharge time of a column line in a semiconductor memory device having a static read circuit so that reading can be speeded up.

[0009]

According to the semiconductor memory device of the present invention, the drains of the first and second first conductivity type MOS transistors are connected to one end of a pair of column lines of each cell in the SRAM cell group, and the source is connected. To the first power supply,
The other end of the column line of each cell in the RAM cell group is connected to a pair of input terminals of a column selector, and the output terminal of the column selector is connected to the input terminal of a static read circuit.
In a semiconductor memory device having a row decoder connected to a row line of an AM cell group and a column decoder connected to a selection line of the column selector, first and second second terminals are connected to a pair of output terminals of the column selector. A drain and a gate of a conductivity type MOS transistor are connected, and a first input of a first and second two-input OR circuit is connected to a source of the first and second second conductivity type MOS transistors. 1 and 2
The second input of the input OR circuit is connected to a precharge signal terminal, the output of the first two-input OR circuit is connected to the gate of the first first conductivity type MOS transistor, and the second The output of the input OR circuit is connected to the second first conductivity type M
A circuit connected to the gate of the OS transistor is provided.

[0010]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention.
An SRAM cell group 1, a column selector 2, a static read circuit 3, a row decoder 4, and a column decoder 5 are provided. Further, it has P-channel MOS transistors 6 and 7, a power supply terminal 8, a data output terminal 9, and a precharge signal terminal 10. The present invention, in addition to the above configuration,
Two-input OR circuits 11 and 12 and N-channel MOS transistors 13 and 14 having the same threshold value as the threshold value V _THR of the static read circuit 3 are provided on the output side of the column selector 2.

Specifically, the drains and gates of the N-channel MOS transistors 13 and 14 are connected to the output terminal of the column selector 2, and these MOS transistors 13 and 14 are connected.
The source 14 is connected to one input of the two-input OR circuits 11 and 12, and the other input of the two-input OR circuits 11 and 12 is connected to the precharge signal terminal 10. And
The output of the two-input OR circuit 12 is connected to the gate of the P-channel MOS transistor 6, and the output of the two-input OR circuit 11 is connected to the gate of the P-channel MOS transistor 7. As in the conventional case, only one cell is shown in the SRAM cell group 1, and only a pair of column lines represented by D and D 'are shown.

In FIG. 1, a low level (GND) is input to a precharge signal terminal 10 during a precharge period of a first cycle.
The outputs of the circuits 11 and 12 are Low, and the P-channel MOS transistors 6 and 7 for precharging are in the ON state.
The column line pair of the SRAM cell group 1 is charged up in the direction of the power supply voltage V _DD applied from the GND to the power supply terminal 8.
At the same time as the start of the precharge period, the output of the column decoder 5 is determined, and when one pair of the column selectors 2 is selected,
One of the pair of column lines D and D 'on the SRAM cell group 1 side is short-circuited to the input terminal of the static read circuit 3, and the column line on the output side of the column selector 2 is simultaneously charged up from GND to _VDD. You.

_Assuming that the column line level on the SRAM cell group 1 side is V _dL1 and the static read circuit 3 side is V _dL2 , the charge level of the column line is
_VdL1 > _VdL2 . N channel M
The level on the source side of the OS transistors 13 and 14 is lower than that on the drain side by the threshold voltage V _TN . Therefore, the input logical threshold value of the static read circuit 3 is set to V _THR
When V _dL2 ≧ V _THR + V _TN , the input logical threshold value V _THR ′ of the two-input OR circuits 11 and 12 is set to V _THR.
If V _THR 'is set, the output becomes High (V _DD ), the P-channel MOS transistors 6 and 7 are turned off, and the charge-up of the column lines D and D' is stopped. V _dL2
Since V _dL2 = V _THR + V _TN , the static readout circuit 3 is latched in a stable state.

Next, in the read period, the output of the row decoder 4 is determined, and any one of the row lines C of the SRAM cell group 1 becomes active. D and D 'are discharged. When the data of the pair of column lines selected by the column selector 2 is input to the static read circuit 3, and the discharged column lines _satisfy V _dL2 ≤ V _THR. The static read circuit 3 latches data.

Next, considering the precharge period of the nth cycle, if one of the input-side column lines of the static readout circuit 3 is in the charged state (V _THR + V _TN ), the precharge signal is input. , The column line side 2 in the charged state
The output of the input OR circuit 12 or 13 is High (= V _DD )
It is. In this case, one of the column lines on the SRAM cell group 1 side is not charged up even at the GND level. However, when the column line to be read by the selection of the column selector 2 is low, the column line capacitance C _R of the static read circuit 3 is generally smaller than the column line capacitance C _d of the SRAM cell group 1. ,
Because the relationship that sufficiently smaller than C _d, the amount each of the column lines charged by charge sharing Q _d, Q _R is collimated. As a result, the column line level _VdL2 on the static readout circuit 3 side becomes substantially equal to _VdL1 . That is, since V _dL2 is substantially at a low level, a two-input OR
The output of the circuit 12 becomes Low, and V _dL2 = V _THR +
_Charged up to VTN. In the reading period, the operation is the same as in the first cycle.

In this embodiment, a P-channel type MOS transistor is used for the precharge MOS transistor. However, it goes without saying that a similar effect can be obtained by using an N-channel type MOS transistor.

The read time can be reduced by the following equation (1).
Is represented by

[0018]

(Equation 1)

[0019]

As described above, the present invention provides an SRAM
The voltage level at which the column line is charged up in the precharge is changed to the input logical threshold value: V
By keeping _THR + V _TN , the read time can be shortened by V _DD − (V _THR + V _TN ), and stable read data can be obtained. Data read prevention and, consequently,
The stable operation of the system can be measured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 SRAM cell group 2 Column selector 3 Static readout circuit 4 Row decoder 5 Column decoder 6,7 P channel MOS transistor 8 Power supply terminal 9 Data output terminal 10 Precharge signal terminal 11,12 Two-input OR circuit 13,14 N channel MOS Transistor

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/41

Claims (1)

(57) [Claims] 1. The SRAM cell according to claim 1, wherein drains of first and second first conductivity type MOS transistors are connected to one ends of a pair of column lines of each cell in the SRAM cell group, and a source is connected to a first power supply. The other end of the column line of each cell in the group is connected to a pair of input terminals of a column selector, the output terminal of the column selector is connected to the input terminal of a static readout circuit, and the column line is connected to the row line of the SRAM cell group. In a semiconductor memory device having a connected row decoder and a column decoder connected to a selection line of the column selector, drains of first and second second conductivity type MOS transistors are connected to a pair of output terminals of the column selector. A first input of a first and second two-input OR circuit connected to a source of the first and second second conductivity type MOS transistors, and a first and second two input; OR times The second input of the path is connected to a precharge signal terminal, the output of the first two-input OR circuit is connected to the gate of the first first conductivity type MOS transistor, and the second two-input OR The output of the circuit
And a circuit connected to the gate of the first conductivity type MOS transistor.