JP2856455B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2856455B2 JP2856455B2 JP1258763A JP25876389A JP2856455B2 JP 2856455 B2 JP2856455 B2 JP 2856455B2 JP 1258763 A JP1258763 A JP 1258763A JP 25876389 A JP25876389 A JP 25876389A JP 2856455 B2 JP2856455 B2 JP 2856455B2
- Authority
- JP
- Japan
- Prior art keywords
- lead portion
- inner lead
- semiconductor chip
- lead frame
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Description
【発明の詳細な説明】 （発明の技術分野） 本発明は、半導体装置の改良に関する。Description: TECHNICAL FIELD The present invention relates to an improvement in a semiconductor device.
（従来の技術） 半導体チップをパッケージとして実装するには、チッ
プ上の電極パッドから外部リード端子への接続が必要で
ある。(Prior Art) In order to mount a semiconductor chip as a package, it is necessary to connect electrode pads on the chip to external lead terminals.
その一例として、たとえば第６図に示すような、いわ
ゆるワイヤボンディング方式による接続が行われてい
る。これは、まず、リードフレーム１の所定位置に半導
体チップ２を上向きにして固定するマンウント工程がな
される。ついで、ワイヤボンディングによって半導体チ
ップ２上の電極パッド３と上記リードフレーム１の端子
とをワイヤ４を介して接続する。As an example, connection by a so-called wire bonding method as shown in FIG. 6 is performed. First, a mounting step of fixing the semiconductor chip 2 upward at a predetermined position of the lead frame 1 is performed. Next, the electrode pads 3 on the semiconductor chip 2 and the terminals of the lead frame 1 are connected via wires 4 by wire bonding.
これらの接続にあたっては、Au線を主体とした熱圧着
法と、Al線を主体とした超音波ボンディング法とがあ
る。この種ワイヤボンディングは、近年、１ワイヤ0.2
〜0.4秒の高速のオートボンダが開発されるに至り、LSI
コストの低減と信頼性向上に寄与している。For these connections, there are a thermocompression bonding method mainly using an Au wire and an ultrasonic bonding method mainly using an Al wire. In recent years, this type of wire bonding has
The development of high-speed auto bonders of up to 0.4 seconds
This contributes to cost reduction and reliability improvement.
しかしながら、このような自動ワイヤボンディングが
進んでいるとはいえ、本質的には１点毎の接続であるの
で、組立工程で大きな割合いを占め、コストの低減に悪
影響がある。However, although such automatic wire bonding is progressing, the connection is essentially a point-to-point connection, so that it occupies a large proportion in the assembling process and adversely affects cost reduction.
また、上記半導体チップ２に多数の電極パッド３…を
備える、多数端子化が最近の傾向であり、300〜500ピン
のニーズもある。The semiconductor chip 2 is provided with a large number of electrode pads 3..., And the number of terminals is a recent trend, and there is a need for 300 to 500 pins.
上記半導体チップ２がたとえば平面矩形状であり、そ
の周囲四辺に電極パッド３…が並べられる、いわゆるQF
Pタイプのものにおいては、多数端子に対応するようリ
ードフレーム１のリード幅を細くしようとしても限界が
あるので、端子数の増大にともなってワイヤ４のリード
フレーム１に対する接続位置を半導体チップ２のマウン
ト位置から遠く離し、その位置で接続しなければならな
い。The semiconductor chip 2 has, for example, a planar rectangular shape, and electrode pads 3...
In the case of the P type, there is a limit even if the lead width of the lead frame 1 is reduced so as to correspond to a large number of terminals. Therefore, as the number of terminals increases, the connection position of the wires 4 to the lead frame 1 is changed. The connection must be made far away from the mounting position.
このため、半導体チップ２をパッケージとして実装し
た状態で大型になってしまうとともに、ワイヤボンディ
ングの加工精度がチップの多数端子化にともなって求め
られる寸法精度に追付けなくなっている。For this reason, the semiconductor chip 2 becomes large in a state in which it is mounted as a package, and the processing accuracy of wire bonding cannot follow the dimensional accuracy required as the number of terminals of the chip increases.
このような不具合を解消するために、第７図に示すよ
うな、フィルムキャリヤ方式である、いわゆるTAB方式
が多用される傾向にある。In order to solve such problems, a so-called TAB system, which is a film carrier system, as shown in FIG. 7, tends to be frequently used.
これは、基本的には多数端子の接続を一括ボンディン
グによって行うものであり、同時に加工精度の高度化を
可能とし、組立工程の高効率化、低コスト化と高密度実
装化を同時に実現することを目的としている。This is basically to connect a large number of terminals by collective bonding. At the same time, it is possible to improve the processing accuracy, and to achieve high efficiency of assembly process, low cost and high density mounting at the same time. It is an object.
このTAB方式は、まず、ポリイミド材からなるフィル
ムテープ５に銅箔をはり付け、この銅箔をホトエッチン
グして上記フィルムテープ５上にリード６を形成する。In the TAB method, first, a copper foil is attached to a film tape 5 made of a polyimide material, and the copper foil is photo-etched to form leads 6 on the film tape 5.
一方、極く微少のピッチで形成した多数の電極パッド
７上にそれぞれ金属蒸着膜を介して金属突起８を備え、
半導体チップ９を形成する。なお、上記電極パッド７の
周囲はパッシベーション膜で被覆される。On the other hand, a plurality of electrode pads 7 formed at an extremely small pitch are provided with metal projections 8 via metal deposition films, respectively.
A semiconductor chip 9 is formed. The periphery of the electrode pad 7 is covered with a passivation film.
このような半導体チップ９をボンディングステージ上
に支持し、上記リード６のインナリード部6aを介して上
記金属突起８を加熱ツールで加圧し、上記インナリード
部6aを半導体チップ９に対して一括ボンディングする。
このような工程をインナリードボンディング（ILB）と
呼んでいる。Such a semiconductor chip 9 is supported on a bonding stage, and the metal projection 8 is pressed by a heating tool via the inner lead portion 6a of the lead 6, and the inner lead portion 6a is collectively bonded to the semiconductor chip 9. I do.
Such a process is called inner lead bonding (ILB).
ついで、ディスペンサから樹脂を滴下して半導体チッ
プ９およびリード６の特にインナリード部6aをモールド
するポッティング工程、上記フィルムテープ５からリー
ド６のアウタリード部6bを打抜く切断工程を経て、リー
ド６のアウタリード部6bをリードフレーム10に一括ボン
ディングする工程となる。Then, a potting step of dropping a resin from a dispenser to mold the semiconductor chip 9 and the lead 6, particularly the inner lead part 6a, and a cutting step of punching the outer lead part 6b of the lead 6 from the film tape 5 are performed. This is the step of batch bonding the portion 6b to the lead frame 10.
このアウタリード部6bをボンディングする工程は、上
記インナリードボンディング（ILB）と区別して、アウ
タリードボンディング（OLB）と呼んでいる。The step of bonding the outer lead portion 6b is referred to as outer lead bonding (OLB) in distinction from the inner lead bonding (ILB).
このように全てのボンディングは自動化されるととも
に極く微少ピッチの多数端子であっても、一括ボンディ
ングが可能となっている。As described above, all bonding is automated, and collective bonding can be performed even with a large number of terminals having an extremely small pitch.
（発明が解決しようとする課題） しかしながら、この種TAB方式による実装にも問題が
あって、たとえば、所定長尺のフィルムテープ５上に、
リード６のインナリード部6aを接続するILB工程を所定
量の半導体チップ９に対して行ない、これとは別の部位
で、ILB工程を経たフィルムテープ５に対し、リード６
のアウタリード部6bをリードフレーム10に接続するOLB
工程が必要であり、それぞれの作業および管理が必要で
手間がかかることは避けられない。(Problems to be Solved by the Invention) However, there is also a problem in mounting by this type of TAB method, for example, on a film tape 5 of a predetermined length,
An ILB process for connecting the inner lead portions 6a of the leads 6 is performed on a predetermined amount of the semiconductor chips 9. At a different portion from the semiconductor chip 9, the lead 6 is attached to the film tape 5 that has undergone the ILB process.
OLB that connects the outer lead portion 6b of the
It is inevitable that a process is required, and each work and management are required and time-consuming.
また、上記フィルムテープ５は高価なポリイミド材が
使用されて、この種TAB部品自体のコストが高くなり、
かつポッティング工程で樹脂モールド内に熱膨張係数が
大きく異なるポリイミド材が含まれるために、信頼性に
難点がある等の不具合がある。In addition, the above-mentioned film tape 5 uses an expensive polyimide material, which increases the cost of this kind of TAB component itself,
In addition, since a polyimide material having a significantly different coefficient of thermal expansion is contained in the resin mold in the potting step, there is a problem that reliability is difficult.
本発明は上記事情に着目してなされたものであり、そ
の目的とするところは、複数の電極パッドを有する半導
体チップに対し、リードフレームのインナリード部を直
接、かつ一括ボンディングすることにより、半導体チッ
プとリードフレームのみで廉価に構成でき、しかも極く
微少ピッチでありながら多数のファインピッチで接続し
て信頼性の向上化を得られる半導体装置を提供すること
を目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to directly and collectively bond an inner lead portion of a lead frame to a semiconductor chip having a plurality of electrode pads. It is an object of the present invention to provide a semiconductor device which can be formed at a low cost only with a chip and a lead frame, and which can be connected at a large number of fine pitches and have improved reliability even though the pitch is extremely small.
（課題を解決する手段） 上記目的を達成するため、本発明の半導体装置は、複
数の電極パッドを有する半導体チップと、一端側に各電
極パッドに接続されるインナリード部が一体形成され、
かつ他端側に外部端子に接続されるアウタリード部が一
体形成されたリードフレームとを具備し、インナリード
部の肉厚をインナリード部以外のリードフレームの肉厚
よりも薄く形成し、半導体チップはインナリード部側に
形成されたリードフレームの凹状空間に収納されている
ことを特徴とする。(Means for Solving the Problems) In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor chip having a plurality of electrode pads and an inner lead portion connected to each electrode pad on one end side,
And a lead frame integrally formed with an outer lead portion connected to an external terminal on the other end side, wherein the thickness of the inner lead portion is formed smaller than the thickness of the lead frame other than the inner lead portion, and the semiconductor chip Are housed in a concave space of a lead frame formed on the inner lead portion side.
このような課題を解決する手段を採用すれば、インナ
リード部の幅寸法が極く細くなり、それに対応して肉厚
を極く薄くする。このことにより、ボンディング時の加
熱ツールからの入熱量および熱圧着時間などのマッチン
グがとり易くなる。また、リードフレーム全体に亘って
肉厚を薄くすると、強度的に極めて弱いものになるの
で、インナリード部以外の肉厚はこれまでと同様の肉厚
とし、強度を確保する。If the means for solving such a problem is adopted, the width of the inner lead portion becomes extremely thin, and the thickness is correspondingly made extremely thin. This facilitates matching of the amount of heat input from the heating tool and the time of thermocompression bonding during bonding. Further, when the thickness is reduced over the entire lead frame, the strength becomes extremely weak. Therefore, the thickness of the portion other than the inner lead portion is set to the same thickness as before and the strength is secured.
さらに半導体チップを、リードフレームの一端部に一
体形成されかつ薄肉化されたインナリード部側のリード
フレームに形成された凹状空間に、はみ出すことなくス
ッポリと収納させるようにしたので、パッケージの薄型
化に寄与することができる。また、インナリード部をリ
ードフレームに直接形成しているので、TAB方式に比べ
構造が単純化し、生産コストが安くできる。Furthermore, the semiconductor chip is housed in the recessed space formed in the lead frame on the side of the inner lead portion formed integrally with the one end of the lead frame and thinned without protruding, so that the package is made thinner. Can be contributed to. In addition, since the inner lead portion is formed directly on the lead frame, the structure is simplified and the production cost can be reduced as compared with the TAB method.
（発明の実施の形態） 第１図に示すように、11は平面矩形状である、いわゆ
るQFP（Quad Flat Package）タイプの半導体チップで
あり、その四辺に多数の接続端子である電極パッド12が
極く微少ピッチで設けられる。(Embodiment of the Invention) As shown in FIG. 1, reference numeral 11 denotes a so-called QFP (Quad Flat Package) type semiconductor chip having a planar rectangular shape, and electrode pads 12 as a large number of connection terminals are provided on four sides thereof. It is provided at an extremely small pitch.
それぞれの電極パッド12はアルミニウムからなり、こ
れ以外の表面はパッシベーション膜で被覆される。ま
た、上記電極パッド12には金属突起13が設けられ、互い
に極く微少のピッチとなる。Each electrode pad 12 is made of aluminum, and the other surface is covered with a passivation film. Further, metal projections 13 are provided on the electrode pads 12, and have extremely small pitches with respect to each other.
一方、14はリードフレームであり、たとえば0.4μｍ
程度の錫メッキあるいは金メッキが全周面あるいは部分
的に被覆され、もしくは銅材から構成し何等のメッキ処
理を施さないものでもよい。On the other hand, 14 is a lead frame, for example, 0.4 μm
A tin plating or a gold plating of a certain degree may be entirely or partially covered, or may be made of a copper material and not subjected to any plating treatment.
このようなリードフレーム14の一端側は、半導体チッ
プ11に対する接続部であるインナリード部14aの肉厚M1
のみ極く薄い肉厚とし、このインナリード部14a以外の
リードフレーム14他端側であり、基板側のリード、すな
わち外部端子に接続されるアウタリード部14bおよびイ
ンナリード部14a近傍部分に亘っては通常の肉厚M0とす
る。One end of such a lead frame 14 has a thickness M 1 of an inner lead portion 14a which is a connection portion to the semiconductor chip 11.
Only the very thin wall thickness is the other end side of the lead frame 14 other than the inner lead portion 14a, and the lead on the substrate side, that is, the outer lead portion 14b connected to the external terminal and the portion near the inner lead portion 14a are the normal wall thickness M 0.
実際の形成寸法としては、アウタリード部14bおよび
インナリード部14a近傍部分に亘る肉厚を、たとえば100
〜300μｍとしたとき、上記インナリード部14aの長さ寸
法L1は約700μｍとし、ここの肉厚を35μｍとする。少
なくとも、インナリード部14aの肉厚M1は、アウタリー
ド部14bおよびインナリード部14a近傍部分に亘る肉厚M0
の70％以下とするのが好ましい。As the actual forming dimensions, the thickness over the portion near the outer lead portion 14b and the inner lead portion 14a is, for example, 100
When the thickness is about 300 μm, the length L 1 of the inner lead portion 14 a is about 700 μm, and the thickness here is 35 μm. At least, the thickness M 1 of the inner lead portion 14a is thicker M 0 over the outer lead portions 14b and the inner lead portion 14a adjacent portion
Is preferably 70% or less.
なお上記リードフレーム14においては、極く微少ピッ
チの電極パッド12に直接接続するため、必然的にリード
フレーム14全体もしくは少なくともインナリード部14a
の幅寸法を狭くしなければならない。このようなリード
フレーム14は、エッチング加工もしくはプレス加工によ
り得られる。In the lead frame 14, since the lead frame 14 is directly connected to the electrode pads 12 having an extremely fine pitch, it is inevitable that the entire lead frame 14 or at least
Must be narrowed. Such a lead frame 14 is obtained by etching or pressing.
しかして、上記半導体チップ11を図示しないボンディ
ングステージ上に支持し、上記リード14のインナリード
部14aを介して金属突起13を加熱ツールで加圧し、上記
電極パッド12とインナリード部14aを一括ボンディング
する。Then, the semiconductor chip 11 is supported on a bonding stage (not shown), and the metal protrusion 13 is pressed by a heating tool via the inner lead portion 14a of the lead 14, thereby bonding the electrode pad 12 and the inner lead portion 14a together. I do.
その結果、半導体チップは第１図に示すように、薄肉
化されているインナリード部14a側のリードフレーム４
に直接形成された凹状空間に、はみ出すことなくスッポ
リと収容される。As a result, as shown in FIG. 1, the semiconductor chip becomes thinner in the lead frame 4 on the inner lead portion 14a side.
Is accommodated in the concave space formed directly without protruding.
このとき、インナリード部14aは、その幅寸法が細い
ばかりでなく極く薄い肉厚M1であるので、加熱ツールの
入熱量および熱圧着時間等のマッチングがとり易い。At this time, the inner lead portion 14a, since the width dimension is in the extremely thin thickness M 1 not only thin, easily takes heat input and matching of the thermal compression bonding time of the heating tool.
すなわち、インナリード部14aと電極パッド12との接
続を確実に行なうためには、リードフレーム14のたとえ
ば錫メッキ層と金属突起13の金バンプとの共晶反応を促
進させる必要がある。そのため、加熱ツールの加熱温度
および熱圧着時間が適さないと、上記パッシベーション
膜にクラックが生じたりボンディング能率が低下する恐
れがある。That is, in order to reliably connect the inner lead portion 14a and the electrode pad 12, it is necessary to promote a eutectic reaction between, for example, a tin plating layer of the lead frame 14 and a gold bump of the metal projection 13. Therefore, if the heating temperature and the thermocompression bonding time of the heating tool are not suitable, cracks may occur in the passivation film or the bonding efficiency may be reduced.
しかしながら、上述のごとき構成によれば、ボンディ
ング能率を犠牲にすることなく高いボンディング特性が
得られ、かつ半導体装置としての製品歩留りおよび信頼
性が向上する。However, according to the configuration described above, high bonding characteristics can be obtained without sacrificing the bonding efficiency, and the product yield and reliability as a semiconductor device are improved.
ついで、第２図に示すように、樹脂を滴下して半導体
チップ11およびインナリード部14aをモールドするポッ
ティング工程を経て、リードフレーム14のアウタリード
部14bを所定位置で切断し、かつ曲げ加工することによ
りパッケージが完成する。このようなアウタリード部14
bの曲げ加工にあたって、ここは通常の肉厚M0を有する
から充分な強度を保持する。Then, as shown in FIG. 2, the outer lead portion 14b of the lead frame 14 is cut and bent at a predetermined position through a potting step of dropping a resin to mold the semiconductor chip 11 and the inner lead portion 14a. Completes the package. Such outer lead portion 14
In b of bending, now retains sufficient strength because of ordinary thickness M 0.
また、半導体チップ11がインナリード部14a側のリー
ドフレーム４に直接形成された凹状空間に、はみ出すこ
となくスッポリと収まっているので、樹脂部の厚さを薄
くすることができる。また、インナリード部をリードフ
レームに直接形成しているので、TAB方式に比べ構造が
単純化し、生産コストが安くできる。Further, since the semiconductor chip 11 fits into the concave space directly formed in the lead frame 4 on the inner lead portion 14a side without protruding, the thickness of the resin portion can be reduced. In addition, since the inner lead portion is formed directly on the lead frame, the structure is simplified and the production cost can be reduced as compared with the TAB method.
なお、パッケージとしては以下に述べるように形成し
てもよい。すなわち、第３図に示すように、リードフレ
ーム14のインナリード部14aは上記実施の形態と同様の
極く薄い肉厚M1とし、かつこのインナリード部14aの近
傍部分14cをインナリード部14aよりも僅かに厚い肉厚M2
とし、かつこれら以外の部分は全て通常の肉厚M0とす
る。The package may be formed as described below. That is, as shown in FIG. 3, the inner lead part 14a of the lead frame 14 is a very thin wall thickness M 1 of the embodiment similar to the above embodiment, and the inner lead portion 14a of the portion near 14c of the inner lead portion 14a slightly than the thick wall thickness M 2
And then, and all portions other than these are the normal thickness M 0.
この場合は、電極パッド12の数が極く多い半導体チッ
プ11と、これよりは電極パッドの数が少ないとともに大
型の半導体チップとの、２種類の半導体チップに対応で
きる。In this case, it is possible to cope with two types of semiconductor chips: a semiconductor chip 11 having an extremely large number of electrode pads 12 and a large semiconductor chip having a smaller number of electrode pads.
また第４図に示すように、リードフレーム14自体は先
に第１図および第２図で示したものと同一でよいが、同
図とは逆にこれを裏返し状態とし、このインナリード部
14aを半導体チップ11に金属突起13を介して接続する。
この場合には、特別な形状のパッケージとしての仕様に
対応することとなる。Also, as shown in FIG. 4, the lead frame 14 itself may be the same as that shown in FIGS. 1 and 2 above, but in the reverse of FIG.
14a is connected to the semiconductor chip 11 via the metal protrusion 13.
In this case, it corresponds to the specification as a package having a special shape.
さらにまた、第５図に示すように、極く薄肉のインナ
リード部14a′をリードフレーム14の肉厚の略中央部に
形成するようにしてもよい。この場合には、半導体チッ
プ11を上向きにして接続しても、また下向きに接続して
も、樹脂モールドした状態では全く同一のパッケージが
形成されることとなる。Further, as shown in FIG. 5, an extremely thin inner lead portion 14a 'may be formed substantially at the center of the thickness of the lead frame 14. In this case, even when the semiconductor chip 11 is connected upward or downward, the same package is formed in a resin-molded state.
（発明の効果） 以上説明したように本発明によれば、複数の電極パッ
ドを備えた半導体チップを、リードフレームに直接形成
し、かつ極く薄肉したインナリード部に直接一括して接
続し、薄肉化したインナリード部側のリードフレームに
形成された凹状空間に、半導体チップがはみ出すことな
くスッポリと収まるように接合するようにしたから、フ
ァインピッチで、かつ確実な接続を可能化し、これまで
のようないわゆるTAB部品を用いずにすみ、コストの低
減化を図るとともに小型薄型化したパッケージを得、ま
た樹脂モールドの際に熱膨張係数の相違に神経を使う必
要がなく、信頼性の向上を図れるなどの効果がある。(Effects of the Invention) As described above, according to the present invention, a semiconductor chip having a plurality of electrode pads is directly formed on a lead frame and directly connected collectively to an extremely thin inner lead portion. Since the semiconductor chip is joined to the recessed space formed in the thinner inner lead part side lead frame so that it does not protrude and fits into the gap, fine pitch and reliable connection has been enabled. No need to use so-called TAB parts such as these, reducing cost and obtaining a small and thin package, and eliminating the need to use nerves for differences in the coefficient of thermal expansion during resin molding, improving reliability This has the effect of achieving
さらに、リードフレームをファインピッチ化しても
プレスまたはエッチングなどによりリード形成が可能と
なる。リードフレームの剛性を犠牲にすることなく、
インナリード部のみボンディングに最適の厚さに設定す
ることが可能となる。インナリード部をリードフレー
ムに直接形成しているので、TAB方式に比べ構造が単純
化し、生産コストを安くすることができる。などの効果
も奏する。Further, even if the lead frame is made fine pitch, the lead can be formed by pressing or etching. Without sacrificing the rigidity of the lead frame,
Only the inner lead portion can be set to an optimum thickness for bonding. Since the inner lead portion is formed directly on the lead frame, the structure is simplified and the production cost can be reduced as compared with the TAB method. It also produces effects such as:
第１図は本発明の一実施の形態を示す半導体装置の一工
程状態の縦断側面図、第２図はパッケージとして完成さ
れた半導体装置の縦断面図、第３図ないし第５図は互い
に異なる本発明の他の実施の形態を示す半導体装置の一
工程状態の縦断側面図、第６図および第７図は互いに異
なる本発明の従来例を示す半導体装置の一工程状態の縦
断側面図である。 12……電極パッド、11……半導体チップ、14……リード
フレーム、14a……インナリード部、13……金属突起、1
4b……アウトリード部。FIG. 1 is a longitudinal sectional side view of a semiconductor device showing one embodiment of the present invention in one process state, FIG. 2 is a longitudinal sectional view of a semiconductor device completed as a package, and FIGS. 3 to 5 are different from each other. FIGS. 6 and 7 are longitudinal sectional side views of one process state of a semiconductor device showing a conventional example of the present invention, which are different from each other, showing another embodiment of the present invention. . 12 ... Electrode pad, 11 ... Semiconductor chip, 14 ... Lead frame, 14a ... Inner lead part, 13 ... Metal protrusion, 1
4b …… Out lead part.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 23/50──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 23/50
Claims (1)
と、 一端側に上記各電極パッドに接続されるインナリード部
が一体形成され、かつ他端側に外部端子に接続されるア
ウタリード部が一体形成されたリードフレームとを具備
し、 上記インナリード部の肉厚は、上記インナリード部以外
の上記リードフレームの肉厚よりも薄く形成され、 上記半導体チップは、上記インナリード部側に形成され
た上記リードフレームの凹状空間に収納されていること
を特徴とする半導体装置。A semiconductor chip having a plurality of electrode pads, an inner lead portion connected to each of the electrode pads on one end side, and an outer lead portion connected to an external terminal on the other end side are integrally formed. A thickness of the inner lead portion is formed smaller than a thickness of the lead frame other than the inner lead portion, and the semiconductor chip is formed on the inner lead portion side. A semiconductor device housed in a concave space of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1258763A JP2856455B2 (en) | 1989-10-05 | 1989-10-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1258763A JP2856455B2 (en) | 1989-10-05 | 1989-10-05 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03123042A JPH03123042A (en) | 1991-05-24 |
| JP2856455B2 true JP2856455B2 (en) | 1999-02-10 |
Family
ID=17324750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1258763A Expired - Fee Related JP2856455B2 (en) | 1989-10-05 | 1989-10-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2856455B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3230348B2 (en) * | 1993-09-06 | 2001-11-19 | ソニー株式会社 | Resin-sealed semiconductor device and method of manufacturing the same |
| JP2007335632A (en) | 2006-06-15 | 2007-12-27 | Toyota Industries Corp | Semiconductor device |
-
1989
- 1989-10-05 JP JP1258763A patent/JP2856455B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03123042A (en) | 1991-05-24 |
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