JP2847970B2 - Gas sensor and method of manufacturing the same - Google Patents
Gas sensor and method of manufacturing the sameInfo
- Publication number
- JP2847970B2 JP2847970B2 JP40396290A JP40396290A JP2847970B2 JP 2847970 B2 JP2847970 B2 JP 2847970B2 JP 40396290 A JP40396290 A JP 40396290A JP 40396290 A JP40396290 A JP 40396290A JP 2847970 B2 JP2847970 B2 JP 2847970B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- layer
- electrode pair
- curved portion
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明はガスセンサおよびその
製造方法に係り、特にヒータの消費電力が少なくＩＣの
実装密度に優れるガスセンサおよびその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gas sensor and a method of manufacturing the same, and more particularly to a gas sensor which consumes less power in a heater and has an excellent IC mounting density and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】酸化スズ，酸化亜鉛等のｎ型金属酸化物
半導体は、大気中で３００〜５００℃の温度に加熱され
ると粒子表面に大気中の酸素が活性化吸着して高抵抗化
しているが、可燃性ガスが接触すると吸着酸素と可燃性
ガスとが反応して吸着酸素が除去され抵抗値が減少す
る。このような性質を利用して、酸化スズを用いたガス
センサはＬＰガス，都市ガス等のガス漏れ警報器に広く
用いられている。2. Description of the Related Art When an n-type metal oxide semiconductor such as tin oxide or zinc oxide is heated to a temperature of 300 to 500 ° C. in the air, oxygen in the air is activated and adsorbed on the particle surface to increase the resistance. However, when the combustible gas comes into contact, the adsorbed oxygen reacts with the combustible gas to remove the adsorbed oxygen and reduce the resistance value. Utilizing such properties, gas sensors using tin oxide are widely used in gas leak alarms for LP gas, city gas and the like.
【０００３】このようなｎ型金属酸化物半導体を用いる
ガスセンサは、ヒータを用いて上記所定温度に加熱され
る。図５は従来のガスセンサを示す断面図である。アル
ミナ基板１４の一方の主面の上に電極１１，１２、酸化
スズからなる感ガス層１３、被覆層１７が、他の主面に
はヒータ１８が設けられる。１５，１６はヒータ用電極
である。A gas sensor using such an n-type metal oxide semiconductor is heated to the above-mentioned predetermined temperature by using a heater. FIG. 5 is a sectional view showing a conventional gas sensor. The electrodes 11 and 12 and the gas-sensitive layer 13 made of tin oxide and the coating layer 17 are provided on one main surface of the alumina substrate 14, and the heater 18 is provided on the other main surface. Reference numerals 15 and 16 denote heater electrodes.
【０００４】図６は従来の異なるガスセンサを示す断面
図である（特開昭59−143946号公報参照）。アンダカッ
トされたシリコン基板２０Ａの上部に酸化シリコン層２
１Ａに支持されたセンサ用電極２４Ａと、酸化シリコン
層２３Ａで絶縁されたヒータ２５Ａと、酸化スズ層２６
Ａとが張出した構造となっている。FIG. 6 is a sectional view showing a different conventional gas sensor (see Japanese Patent Application Laid-Open No. Sho 59-143946). A silicon oxide layer 2 is formed on the undercut silicon substrate 20A.
1A, a sensor electrode 24A supported by the heater 1A, a heater 25A insulated by a silicon oxide layer 23A, and a tin oxide layer 26A.
A has a protruding structure.
【０００５】[0005]
【発明が解決しようとする課題】しかしながらこのよう
な従来のガスセンサにおいては、消費電力が数１００mW
であり、乾電池をヒータ電源として用いることができな
いかまたは乾電池が使用可能としてもそのアンダカット
に際し両面マスク合わせを行う必要があった。However, in such a conventional gas sensor, the power consumption is several hundred mW.
Therefore, even if the dry battery cannot be used as a heater power supply or the dry battery can be used, it is necessary to perform double-sided mask alignment when undercutting the dry battery.
【０００６】この発明は上述の点に鑑みてなされ、その
目的はセンサ構造を改良して、ヒータの消費電力を少な
くして、乾電池駆動可能な小型のガスセンサを提供し、
あわせてマスク合わせの必要のないガスセンサの容易な
構造方法を提供することにある。The present invention has been made in view of the above points, and an object of the present invention is to provide a small gas sensor which can be driven by a dry battery by improving a sensor structure, reducing power consumption of a heater, and
Another object of the present invention is to provide a method of easily constructing a gas sensor that does not require mask alignment.
【０００７】[0007]
【課題を解決するための手段】上述の目的はこの発明に
よれば、SUMMARY OF THE INVENTION The above objects are attained according to the present invention.
【０００８】1)シリコン基板と、ポリシリコン層と、第
一および第二の絶縁層と、第一および第二の電極対と、
酸化物半導体層、とを有し、シリコン基板は表面が平坦
なものであり、ポリシリコン層はシリコン基板に接する
平坦な部分とシリコン基板に接することのないわん曲の
部分とからなり、第一の絶縁層はシリコン基板に接する
ものであって第一の絶縁層とポリシリコン層のわん曲の
部分とで囲まれる領域は空間部となるものであり、第二
の絶縁層はポリシリコン層のわん曲の部分と平坦な部分
の両者につき少なくともそれらの一部を被覆し、この際
第二の絶縁層の平坦な部分には第二の電極対のためにコ
ンタクトホールが設けられ、第一の電極対は第二の絶縁
層の上に選択的に積層されるとともに、第二の絶縁層の
わん曲の部分で対向して配置され、第二の電極対は第二
の絶縁層の上に第一の電極対と隔離して選択的に設けら
れ、前記コンタクトホールにおいてポリシリコン層と接
続し、酸化物半導体層は第一の電極対の対向する部分に
設けられ、第一の電極対に接続されること、1) a silicon substrate, a polysilicon layer, first and second insulating layers, first and second electrode pairs,
An oxide semiconductor layer, and the silicon substrate has a flat surface, and the polysilicon layer has a flat portion in contact with the silicon substrate and a curved portion not in contact with the silicon substrate. The insulating layer is in contact with the silicon substrate, and the region surrounded by the first insulating layer and the curved portion of the polysilicon layer is a space, and the second insulating layer is formed of the polysilicon layer. At least a part of both the curved portion and the flat portion is covered, wherein the flat portion of the second insulating layer is provided with a contact hole for the second electrode pair, The electrode pairs are selectively stacked on the second insulating layer, and are arranged to face each other at a curved portion of the second insulating layer, and the second electrode pair is placed on the second insulating layer. Selectively provided separately from the first electrode pair, Connected to the polysilicon layer in the hole, the oxide semiconductor layer is provided in a portion opposed to the first electrode pair, being connected to the first electrode pair,
【０００９】2)シリコン基板と、第三の絶縁層と、第四
の絶縁層と、第五の絶縁層と、ヒータと、第三の電極対
と、酸化物半導体層とを有し、シリコン基板は表面が平
坦なものであり、第三の絶縁層はシリコン基板の主面に
直接的に積層され、第四の絶縁層は第三の絶縁層の上に
接して積層される平坦な部分と、第三の絶縁層に接する
ことのないわん曲の部分とからなり、ここにわん曲の部
分と第三の絶縁層とに囲まれる領域は空間部となり、第
三の電極対は、第四の絶縁層の平坦な部分とわん曲の部
分の上に選択的にかつ離隔して積層され、この際わん曲
の部分に積層される電極対は対向して配置され、ヒータ
は第四の絶縁層の平坦な部分とわん曲の部分の上に選択
的に積層され、第五の絶縁層は窓部を有するとともに、
この窓部を除きヒータと、第四の絶縁層と、第三の電極
対の上に積層されて平坦な部分とわん曲の部分を形成
し、この際窓部は第三の電極対の平坦な部分およびわん
曲の部分、並びにヒータの平坦な部分にそれぞれ設けら
れ、酸化物半導体層は第五の絶縁層のわん曲の部分の上
に選択的に積層され、このとき第五の絶縁層の窓部を介
して、第三の電極対と電気的に接続されるものであるこ
と、または2) a silicon substrate having a silicon substrate, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a heater, a third electrode pair, and an oxide semiconductor layer; The substrate has a flat surface, the third insulating layer is directly laminated on the main surface of the silicon substrate, and the fourth insulating layer is a flat portion laminated on and in contact with the third insulating layer. And a curved portion that does not come into contact with the third insulating layer, a region surrounded by the curved portion and the third insulating layer becomes a space, and the third electrode pair The four insulating layers are selectively and separately laminated on the flat portion and the curved portion, and the electrode pair laminated on the curved portion is disposed to face each other, and the heater is provided in the fourth portion. Selectively laminated on the flat portion and the curved portion of the insulating layer, the fifth insulating layer has a window,
Except for this window portion, the heater, the fourth insulating layer, and the third electrode pair are stacked to form a flat portion and a curved portion, and the window portion is formed by flattening the third electrode pair. And a curved portion, and a flat portion of the heater, respectively, and the oxide semiconductor layer is selectively laminated on the curved portion of the fifth insulating layer. Being electrically connected to the third pair of electrodes via the window of
【００１０】3)第一の工程ないし第七の工程を有し、第
一の工程はシリコン基板の平坦な１主面に第三の絶縁層
を形成し、第二の工程は、第三の絶縁層の上にポリシリ
コン層を形成し、第三の工程は、ポリシリコン層をパタ
ーニングして複数個のメサ形ポリシリコンを形成し、第
四の工程は、第三の絶縁層とメサ形ポリシリコンの上に
第四の絶縁層を形成し、第五の工程は第四の絶縁層の上
に白金層を積層し、次いでパターニングを行ってヒータ
と第三の電極対を形成し、この際第三の電極対は第四の
絶縁層の平坦な部分と、わん曲の部分とに選択的にかつ
対向して配置され、ヒータは第四の絶縁層の平坦部とわ
ん状の部分の上に選択的に配置され、第六の工程は、第
四の絶縁層とヒータと第三の電極対の上に第五の絶縁層
を積層し、次いで第五の絶縁層の所定部をエッチングし
て、第三の電極対の平坦部とわん曲部の一部に通ずる窓
と、ヒータの平坦な部分の一部に通ずる窓を形成すると
ともに第四と第五の絶縁層を順次エッチングして、第四
と第五の絶縁層のわん曲の部分の周辺部分にポリシリコ
ンに通ずる窓を形成してポリシリコンを溶解除去し、第
七の工程は、第五の絶縁層のわん曲の部分に酸化物半導
体層を積層する工程であるとすることにより達成され
る。3) a first step to a seventh step, wherein the first step forms a third insulating layer on one flat main surface of the silicon substrate, and the second step includes a third step. Forming a polysilicon layer on the insulating layer; a third step of patterning the polysilicon layer to form a plurality of mesa-type polysilicon; and a fourth step, forming a third insulating layer and the mesa-shaped polysilicon. A fourth insulating layer is formed on the polysilicon, and a fifth step is to stack a platinum layer on the fourth insulating layer, and then perform patterning to form a heater and a third electrode pair. In this case, the third electrode pair is selectively and opposed to the flat portion of the fourth insulating layer and the curved portion, and the heater is provided between the flat portion of the fourth insulating layer and the curved portion. And a sixth step of laminating a fifth insulating layer on the fourth insulating layer, the heater and the third electrode pair, A predetermined portion of the fifth insulating layer is etched to form a window that communicates with a portion of the flat portion and the curved portion of the third electrode pair, and a window that communicates with a portion of the flat portion of the heater. The fifth insulating layer is sequentially etched to form a window communicating with the polysilicon around the curved portion of the fourth and fifth insulating layers to dissolve and remove the polysilicon. This is achieved by a step of stacking an oxide semiconductor layer on a curved portion of the fifth insulating layer.
【００１１】[0011]
【作用】酸化物半導体層とそれを加熱するためのヒータ
がブリッジ構造により基板と非接触とされるので熱容量
が減り消費電力が少なくなる。またこの発明に係るセン
サの構造は半導体の製造技術を適用することができ、そ
のために超小型化することができ消費電力が少なくな
る。さらに、ヒータと第三の電極対とが同一のマスクを
用いて同時に形成され、メサ形ポリシリコンの溶解によ
り空間部が形成される。Since the oxide semiconductor layer and the heater for heating the oxide semiconductor layer are not in contact with the substrate by the bridge structure, the heat capacity is reduced and the power consumption is reduced. Further, the structure of the sensor according to the present invention can be applied to a semiconductor manufacturing technology, so that the sensor can be miniaturized and power consumption can be reduced. Further, the heater and the third electrode pair are simultaneously formed using the same mask, and a space is formed by melting the mesa-type polysilicon.
【００１２】[0012]
【実施例】次にこの発明の実施例を図面に基づいて説明
する。図１は請求項１で定義された発明の実施例に係る
ガスセンサを示し、図１（ａ）は平面図、図１（ｂ）は
図１（ａ）のＡ−Ａ矢視図である。シリコン基板１とそ
の上に形成された窒化シリコン膜１Ａと、空間部２と、
ポリシリコン層３と、窒化シリコンからなる第二の絶縁
層４と、Ａｌ・Ｓｉからなる第一の電極対５Ａ，５Ｂと
第二の電極対５Ｃ，５Ｄと、酸化スズからなる酸化物半
導体層７とからガスセンサが構成される。このようなガ
スセンサは以下のようにして製造される。図２は請求項
１で定義された発明の実施例に係るガスセンサの製造手
順を示す工程図である。任意の結晶方位をもつシリコン
基板１の上に絶縁膜として窒化シリコン膜１Ａがさらに
その上にシリコン酸化膜２Ａが公知の技術を用いて２μ
ｍ厚に形成される（図２（ａ）参照）。次いでシリコン
酸化膜２Ａはエッチングされ、島状のシリコン酸化膜２
Ｂが形成される（図２（ｂ）参照）。続いてポリシリコ
ン層３、窒化シリコンからなる絶縁層４を設け絶縁層４
にコンタクトホール８Ａ，８Ｂが形成される（図２
（ｃ）参照）。引続いてＡｌ・Ｓｉ金属層を形成し、エ
ッチングにより第一の電極対５Ａ，５Ｂ、第二の電極対
５Ｃ，５Ｄを形成する（図２（ｄ）参照）。Ａｌ・Ｓｉ
金属層のエッチングのあと窒化シリコンからなる絶縁層
４につき図１（ａ）に示す幅Ｗが１２μｍ，長さＬが１
０００μｍになるようにドライエッチングが行われる。
絶縁層４のドライエッチングのあと、ポリシリコン層３
が絶縁層４と同じパターンでフッ硝酸によりエッチング
される。島状の酸化シリコン２Ｂがフッ酸により除去さ
れ空間部２となる。最後に酸化スズがスパッタされ厚さ
１μｍ，幅１０μｍ，長さ１００μｍの酸化物半導体層
７が形成される（図２（ｅ）参照）。このとき酸化スズ
の抵抗は１００ｋΩである。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a gas sensor according to an embodiment of the present invention defined in claim 1, FIG. 1 (a) is a plan view, and FIG. 1 (b) is a view taken along the line AA of FIG. 1 (a). A silicon substrate 1, a silicon nitride film 1A formed thereon, a space 2,
A polysilicon layer 3, a second insulating layer 4 made of silicon nitride, a first electrode pair 5A, 5B and a second electrode pair 5C, 5D made of Al.Si, and an oxide semiconductor layer made of tin oxide 7 constitute a gas sensor. Such a gas sensor is manufactured as follows. FIG. 2 is a process chart showing a gas sensor manufacturing procedure according to the embodiment of the invention defined in claim 1. A silicon nitride film 1A as an insulating film is further formed on a silicon substrate 1 having an arbitrary crystal orientation, and a silicon oxide film 2A is further formed thereon by a known technique.
It is formed to have a thickness of m (see FIG. 2A). Next, the silicon oxide film 2A is etched to form the island-shaped silicon oxide film 2A.
B is formed (see FIG. 2B). Subsequently, a polysilicon layer 3 and an insulating layer 4 made of silicon nitride are provided.
Contact holes 8A and 8B are formed in FIG.
(C)). Subsequently, an Al.Si metal layer is formed, and first electrode pairs 5A and 5B and second electrode pairs 5C and 5D are formed by etching (see FIG. 2D). Al ・ Si
After the etching of the metal layer, the width W of the insulating layer 4 made of silicon nitride is 12 μm and the length L is 1 shown in FIG.
Dry etching is performed to a thickness of 000 μm.
After the dry etching of the insulating layer 4, the polysilicon layer 3
Are etched with hydrofluoric acid in the same pattern as the insulating layer 4. The island-shaped silicon oxide 2B is removed by hydrofluoric acid to form the space 2. Finally, tin oxide is sputtered to form an oxide semiconductor layer 7 having a thickness of 1 μm, a width of 10 μm, and a length of 100 μm (see FIG. 2E). At this time, the resistance of the tin oxide is 100 kΩ.
【００１３】第一の電極対５Ａ，５Ｂは酸化物半導体層
７の抵抗を測定する。可燃性ガスが酸化スズに接触する
と、酸化スズの抵抗が減少する。第二の電極対５Ｃ，５
Ｄはヒータであるポリシリコン層３に電流を流す。３Ｖ
印加して３mWの電力で酸化物半導体層７を３００℃で加
熱することができる。これは従来の数１００mWの電力に
比し約１／１００の電力消費量である。上述の製造プロ
セスは半導体製造技術を適用するものであり、この場合
特にＭＯＳ ＦＥＴ半導体の製造方法に主要部が共通と
なっている。被加熱部分である第二の絶縁層４、第一お
よび第二の電極対、酸化物半導体層７が空間部２を伴っ
て微細に形成され、熱容量の小さいガスセンサとなる。
この発明の構造を有するガスセンサは３mm×３mmのシリ
コンチップ上にトランジスタ等と共に形成することも可
能であり、電池駆動でポータブルのガスセンサを構造で
きる。またポリシリコンは耐熱性が大きいので高信頼性
のガスセンサが得られる。The first pair of electrodes 5A and 5B measures the resistance of the oxide semiconductor layer 7. When the combustible gas contacts the tin oxide, the resistance of the tin oxide decreases. Second electrode pair 5C, 5
D passes a current through the polysilicon layer 3 as a heater. 3V
The oxide semiconductor layer 7 can be heated at 300 ° C. with the applied power of 3 mW. This is about 1/100 of power consumption compared to the conventional power of several hundred mW. The above-described manufacturing process applies a semiconductor manufacturing technology, and in this case, the main part is particularly common to a method of manufacturing a MOS FET semiconductor. The second insulating layer 4, the first and second electrode pairs, and the oxide semiconductor layer 7, which are the portions to be heated, are finely formed with the space 2 to provide a gas sensor having a small heat capacity.
The gas sensor having the structure of the present invention can be formed together with a transistor or the like on a 3 mm × 3 mm silicon chip, and a portable gas sensor driven by a battery can be structured. Since polysilicon has high heat resistance, a highly reliable gas sensor can be obtained.
【００１４】図３は請求項２で定義された発明の実施例
に係るガスセンサを示し、図３（ａ）は平面図、図３
（ｂ）は図３（ａ）のＢ−Ｂ矢視断面図である。FIG. 3 shows a gas sensor according to an embodiment of the invention defined in claim 2, FIG. 3 (a) is a plan view, and FIG.
FIG. 3B is a cross-sectional view taken along line BB of FIG.
【００１５】このガスセンサは表面が平坦な基板２０と
酸化シリコンからなる第三の絶縁層２１と、空間部２７
と、酸化シリコンからなる第四の絶縁層２２と、ヒータ
２５と、第三の電極対２４と、第五の絶縁層２３と、窓
部３１，４１，５１，７１，７２と、酸化物半導体層２
６とから構成される。This gas sensor comprises a substrate 20 having a flat surface, a third insulating layer 21 made of silicon oxide, and a space 27.
, A fourth insulating layer 22 made of silicon oxide, a heater 25, a third electrode pair 24, a fifth insulating layer 23, windows 31, 41, 51, 71, 72, and an oxide semiconductor Layer 2
And 6.
【００１６】このようなガスセンサは次のようにして調
製される。図４は請求項３で定義された発明の実施例に
係るガスセンサの製造手順を示す工程図である。Such a gas sensor is prepared as follows. FIG. 4 is a process chart showing a gas sensor manufacturing procedure according to the embodiment of the invention defined in claim 3.
【００１７】先ず、任意の結晶方位を持つ２．５mm角，
厚さ４００μｍのシリコン基板２０の上に熱酸化により
厚さ１μｍの酸化シリコン層２１を第三の絶縁層として
形成し、さらにその上にポリシリコン層２７Ａを公知の
技術を用いて２μｍ厚に形成する（図４（ａ）参照）。
次いでポリシリコン層２７Ａを選択エッチングし、図３
（ａ）の二点鎖線で示す４００μｍ角のメサ形ポリシリ
コン２７Ｂを形成する（図４（ｂ）参照）。次に、１μ
ｍ厚の酸化シリコン層２２を被覆し、さらに０．２μｍ
厚の白金層を積層する。この白金層をパターニングして
ヒータ２５および第三の電極対２４を形成する（図４
（ｃ）図４（ｄ）参照）。続いて１μｍ厚の酸化シリコ
ン層２３を被覆する（図４（ｅ）参照）。このあとフォ
トエッチングにより窓部３１，４１，５１，７１，７２
を設ける（図４（ｆ）参照）。その後窓部７１を通じて
酸化シリコンはエッチングしないエッチング液、例えば
ＨＦ−ＨＮＯ3 −ＣＨ3 ＣＯＯＨ混酸を用いてメサ形ポ
リシリコン２７Ｂを除去し、空間部２７を形成する（図
4g参照）。このようにして形成されたブリッジの上に酸
化スズ層２６が１μｍ厚に形成され、酸化物半導体層２
６がつくられる（図４（ｈ）参照）。First, a 2.5 mm square having an arbitrary crystal orientation,
A silicon oxide layer 21 having a thickness of 1 μm is formed as a third insulating layer by thermal oxidation on a silicon substrate 20 having a thickness of 400 μm, and a polysilicon layer 27A is further formed thereon to a thickness of 2 μm using a known technique. (See FIG. 4A).
Next, the polysilicon layer 27A is selectively etched, and FIG.
A 400 μm-square mesa-shaped polysilicon 27B indicated by a two-dot chain line in FIG. 4A is formed (see FIG. 4B). Next, 1μ
m silicon oxide layer 22 having a thickness of 0.2 μm
Laminate a thick platinum layer. This platinum layer is patterned to form a heater 25 and a third electrode pair 24 (FIG. 4).
(C) See FIG. 4 (d)). Subsequently, a silicon oxide layer 23 having a thickness of 1 μm is covered (see FIG. 4E). Thereafter, window portions 31, 41, 51, 71, 72 are formed by photoetching.
(See FIG. 4F). Then etchant silicon oxide is not etched through the window portion 71, to remove the mesa-type polysilicon 27B by using, for example, a HF-HNO 3 -CH 3 COOH mixed acid, to form a space portion 27 (FIG.
4g). The tin oxide layer 26 is formed to a thickness of 1 μm on the bridge thus formed, and the oxide semiconductor layer 2
6 (see FIG. 4 (h)).
【００１８】なお、窓部はエッチング液の入口となるほ
か、酸化シリコン層２２，２３を通じての熱伝導を制限
するので、消費電力を減少させるのに役立つ。The window serves as an inlet for the etching solution and also limits the heat conduction through the silicon oxide layers 22 and 23, thus helping to reduce power consumption.
【００１９】上の実施例で基板２０の表面の酸化シリコ
ン層２１は、ポリシリコン層２７Ａをエッチングする
際、シリコン基板２０がエッチングされるのを防止する
役目をする。この際空間部２７の形成にＡｌなどのＳｉ
よりエッチングされやすい金属等を用いれば、酸化シリ
コン層２１を省略することもできる。In the above embodiment, the silicon oxide layer 21 on the surface of the substrate 20 serves to prevent the silicon substrate 20 from being etched when etching the polysilicon layer 27A. At this time, Si such as Al
If a metal or the like which is more easily etched is used, the silicon oxide layer 21 can be omitted.
【００２０】[0020]
【発明の効果】この発明によれば、シリコン基板と、
ポリシリコン層と、第一および第二の絶縁層と、第一お
よび第二の電極対と、酸化物半導体層とを有し、シリコ
ン基板は表面が平坦なものであり、ポリシリコン層はシ
リコン基板に接する平坦な部分とシリコン基板に接する
ことのないわん曲の部分とからなり、第一の絶縁層はシ
リコン基板に接するものであって第一の絶縁層とポリシ
リコン層のわん曲の部分とで囲まれる領域は空間部とな
るものであり、第二の絶縁層はポリシリコン層のわん曲
の部分と平坦な部分の両者につき少なくともそれらの一
部を被覆し、この際第二の絶縁層の平坦な部分には第二
の電極対のためにコンタクトホールが設けられ、第一の
電極対は第二の絶縁層の上に選択的に積層されるととも
に、第二の絶縁層のわん曲の部分で対向して配置され、
第二の電極対は第二の絶縁層の上に第一の電極対と隔離
して選択的に設けられ、前記コンタクトホールにおいて
ポリシリコン層と接続し、酸化物半導体層は第一の電極
対の対向する部分に設けられ、第一の電極対に接続さ
れ、According to the present invention, a silicon substrate,
A polysilicon layer, first and second insulating layers, first and second electrode pairs, and an oxide semiconductor layer, the silicon substrate has a flat surface, and the polysilicon layer is formed of silicon. The first insulating layer is in contact with the silicon substrate, and has a flat portion in contact with the substrate and a curved portion not in contact with the silicon substrate, and a curved portion of the first insulating layer and the polysilicon layer. The second insulating layer covers at least a part of both the curved portion and the flat portion of the polysilicon layer, and the second insulating layer covers the second insulating layer. A contact hole is provided in the flat part of the layer for a second electrode pair, the first electrode pair is selectively laminated on the second insulating layer, and the second insulating layer It is placed opposite to the song part,
The second electrode pair is selectively provided on the second insulating layer separately from the first electrode pair, is connected to the polysilicon layer at the contact hole, and the oxide semiconductor layer is formed of the first electrode pair. Are provided at opposing portions of the first pair of electrodes,
【００２１】シリコン基板と、第三の絶縁層と、第四
の絶縁層と、第五の絶縁層と、ヒータと、第三の電極対
と、酸化物半導体層とを有し、シリコン基板は表面が平
坦なものであり、第三の絶縁層はシリコン基板の主面に
直接的に積層され、第四の絶縁層は第三の絶縁層の上に
接して積層される平坦な部分と、第三の絶縁層に接する
ことのないわん曲の部分とからなり、ここにわん曲の部
分と第三の絶縁層とに囲まれる領域は空間部となり、第
三の電極対は、第四の絶縁層の平坦な部分とわん曲の部
分の上に選択的にかつ離隔して積層され、この際わん曲
の部分に積層される電極対は対向して配置され、ヒータ
は第四の絶縁層の平坦な部分とわん曲の部分の上に選択
的に積層され、第五の絶縁層は窓部を有するとともに、
この窓部を除きヒータと、第四の絶縁層と、第三の電極
対の上に積層されて平坦な部分とわん曲の部分を形成
し、この際窓部は第三の電極対の平坦な部分およびわん
曲の部分、並びにヒータの平坦な部分にそれぞれ設けら
れ、酸化物半導体層は第五の絶縁層のわん曲の部分の上
に選択的に積層され、このとき第五の絶縁層の窓部を介
して、第三の電極対と電気的に接続されるものであるこ
と、またはThe silicon substrate includes a silicon substrate, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a heater, a third electrode pair, and an oxide semiconductor layer. The surface is flat, the third insulating layer is directly stacked on the main surface of the silicon substrate, the fourth insulating layer is a flat portion that is stacked in contact with the third insulating layer, It is composed of a curved portion that does not come into contact with the third insulating layer, a region surrounded by the curved portion and the third insulating layer becomes a space, and the third electrode pair is a fourth electrode. The electrode layer is selectively and separately laminated on the flat portion and the curved portion of the insulating layer, and the electrode pair laminated on the curved portion is disposed to face each other, and the heater is connected to the fourth insulating layer. Selectively laminated on the flat part and the curved part of the fifth insulating layer having a window part,
Except for this window portion, the heater, the fourth insulating layer, and the third electrode pair are stacked to form a flat portion and a curved portion, and the window portion is formed by flattening the third electrode pair. And a curved portion, and a flat portion of the heater, respectively, and the oxide semiconductor layer is selectively laminated on the curved portion of the fifth insulating layer. Being electrically connected to the third pair of electrodes via the window of
【００２２】第一の工程ないし第七の工程を有し、第
一の工程はシリコン基板の平坦な１主面に第三の絶縁層
を形成し、第二の工程は、第三の絶縁層の上にポリシリ
コン層を形成し、第三の工程は、ポリシリコン層をパタ
ーニングして複数個のメサ形ポリシリコンを形成し、第
四の工程は、第三の絶縁層とメサ形ポリシリコンの上に
第四の絶縁層を形成し、第五の工程は第四の絶縁層の上
に白金層を積層し、次いでパターニングを行ってヒータ
と第三の電極対を形成し、この際第三の電極対は第四の
絶縁層の平坦な部分と、わん曲の部分とに選択的にかつ
対向して配置され、ヒータは第四の絶縁層の平坦な部分
とわん曲の部分の上に選択的に配置され、第六の工程
は、第四の絶縁層とヒータと第三の電極対の上に第五の
絶縁層を積層し、次いで第五の絶縁層の所定部をエッチ
ングして、第三の電極対の平坦部とわん曲部の一部に通
ずる窓部と、ヒータの平坦な部分の一部に通ずる窓を形
成するとともに第四と第五の絶縁層を順次エッチングし
て、第四と第五の絶縁層のわん曲の部分の周辺部分にポ
リシリコンに通ずる窓を形成してポリシリコンを溶解除
去し、第七の工程は、第五の絶縁層のわん曲の部分に酸
化物半導体層を積層する工程であるので、The first step includes a first step to a seventh step, wherein the first step forms a third insulating layer on one flat main surface of the silicon substrate, and the second step includes the third insulating layer. A third layer is formed by patterning the polysilicon layer to form a plurality of mesa-type polysilicon layers; and a fourth step is forming a third insulating layer and a mesa-type polysilicon layer. A fourth insulating layer is formed on the fourth insulating layer, and a fifth step is to form a platinum layer on the fourth insulating layer, and then perform patterning to form a heater and a third electrode pair. The three electrode pairs are selectively and opposingly disposed on the flat portion and the curved portion of the fourth insulating layer, and the heater is provided on the flat portion and the curved portion of the fourth insulating layer. In the sixth step, a fifth insulating layer is laminated on the fourth insulating layer, the heater and the third electrode pair, and A predetermined portion of the fifth insulating layer is etched to form a window portion communicating with a part of the flat portion and the curved portion of the third electrode pair, and a window communicating with a portion of the flat portion of the heater. The fourth and fifth insulating layers are sequentially etched to form a window in the periphery of the curved portion of the fourth and fifth insulating layers to communicate with the polysilicon to dissolve and remove the polysilicon. Is a step of laminating an oxide semiconductor layer on the curved portion of the fifth insulating layer,
【００２３】酸化物半導体層とそれを加熱するためのヒ
ータがシリコン基板と非接触の状態となり、加熱部分の
熱容量が減って消費電力が少なくなる。またこの発明に
係る構造を有するガスセンサは半導体技術を適用して超
小型化することができ消費電力を少なくすることができ
る。さらにこの構造を有するガスセンサはシリコンチッ
プ上にトランジスタ等とともに搭載することができ乾電
池駆動で低消費電力, ポータブル型小型ガスセンサとし
て使用することが可能となる。また請求項３で定義され
たガスセンサの製造方法においては、空間部の形成の際
にポリシリコン層のみを選択的に溶解除去できるうえ、
ヒータと第三の電極対の製造にマスク合わせが不要とな
り、ガスセンサの製造が容易になる。The oxide semiconductor layer and the heater for heating the oxide semiconductor layer are not in contact with the silicon substrate, so that the heat capacity of the heated portion is reduced and power consumption is reduced. Further, the gas sensor having the structure according to the present invention can be miniaturized by applying semiconductor technology, and the power consumption can be reduced. Furthermore, a gas sensor having this structure can be mounted on a silicon chip together with a transistor and the like, and can be used as a portable small gas sensor driven by a dry battery with low power consumption. According to the method of manufacturing a gas sensor defined in claim 3, only the polysilicon layer can be selectively dissolved and removed when forming the space portion.
The manufacture of the heater and the third electrode pair does not require mask alignment, and the manufacture of the gas sensor becomes easy.
【図１】請求項１で定義された発明の実施例に係るガス
センサを示し、図１（ａ）は平面図、図１（ｂ）は図１
（ａ）のＡ−Ａ矢視断面図1 shows a gas sensor according to an embodiment of the invention defined in claim 1, FIG. 1 (a) is a plan view, and FIG. 1 (b) is FIG.
(A) AA arrow sectional drawing
【図２】請求項１で定義された発明の実施例に係るガス
センサにつきその製造手順を示す工程図FIG. 2 is a process chart showing a manufacturing procedure of the gas sensor according to the embodiment of the invention defined in claim 1;
【図３】請求項２で定義された発明の実施例に係るガス
センサを示し、図３（ａ）は平面図、図３（ｂ）は図３
（ａ）のＢ−Ｂ矢視断面図3A and 3B show a gas sensor according to an embodiment of the invention defined in claim 2; FIG. 3A is a plan view, and FIG.
(A) BB arrow sectional drawing
【図４】請求項３で定義された発明の実施例に係るガス
センサの製造手順を示す工程図FIG. 4 is a process chart showing a gas sensor manufacturing procedure according to an embodiment of the invention defined in claim 3;
【図５】従来のガスセンサを示す断面図FIG. 5 is a sectional view showing a conventional gas sensor.
【図６】従来の異なるガスセンサを示す断面図FIG. 6 is a sectional view showing a different conventional gas sensor.
１ 基板 ２ 空間部 ３ ポリシリコン層 １Ａ 第一の絶縁層 ４ 第二の絶縁層 ５Ａ 第一の電極対 ５Ｂ 第一の電極対 ５Ｃ 第二の電極対 ５Ｄ 第二の電極対 ７ 酸化物半導体層 ２０ 基板 ２１ 第三の絶縁層 ２２ 第四の絶縁層 ２３ 第五の絶縁層 ２４ 第三の電極対 ２５ ヒータ ２６ 酸化物半導体層 ２７ 空間部 ３１ 窓部 ４１ 窓部 ５１ 窓部 ７１ 窓部 ７２ 窓部 DESCRIPTION OF SYMBOLS 1 Substrate 2 Space part 3 Polysilicon layer 1A 1st insulating layer 4 2nd insulating layer 5A 1st electrode pair 5B 1st electrode pair 5C 2nd electrode pair 5D 2nd electrode pair 7 Oxide semiconductor layer Reference Signs List 20 substrate 21 third insulating layer 22 fourth insulating layer 23 fifth insulating layer 24 third electrode pair 25 heater 26 oxide semiconductor layer 27 space portion 31 window portion 41 window portion 51 window portion 71 window portion 72 window Department
Claims (3)
および第二の絶縁層と、第一および第二の電極対と、酸
化物半導体層、とを有し、シリコン基板は表面が平坦な
ものであり、ポリシリコン層はシリコン基板に接する平
坦な部分とシリコン基板に接することのないわん曲の部
分とからなり、第一の絶縁層はシリコン基板に接するも
のであって第一の絶縁層とポリシリコン層のわん曲の部
分とで囲まれる領域は空間部となるものであり、第二の
絶縁層はポリシリコン層のわん曲の部分と平坦な部分の
両者につき少なくともそれらの一部を被覆し、この際第
二の絶縁層の平坦な部分には第二の電極対のためにコン
タクトホールが設けられ、第一の電極対は第二の絶縁層
の上に選択的に積層されるとともに、第二の絶縁層のわ
ん曲の部分で対向して配置され、第二の電極対は第二の
絶縁層の上に第一の電極対と隔離して選択的に設けら
れ、前記コンタクトホールにおいてポリシリコン層と接
続し、酸化物半導体層は第一の電極対の対向する部分に
設けられ、第一の電極対に接続される、ことを特徴とす
るガスセンサ。1. A silicon substrate having a silicon substrate, a polysilicon layer, first and second insulating layers, first and second electrode pairs, and an oxide semiconductor layer, wherein the silicon substrate has a flat surface. The polysilicon layer has a flat portion in contact with the silicon substrate and a curved portion not in contact with the silicon substrate, and the first insulating layer is in contact with the silicon substrate and has a first insulating property. The region surrounded by the layer and the curved portion of the polysilicon layer is a space, and the second insulating layer is formed by at least a part of both the curved portion and the flat portion of the polysilicon layer. In this case, a flat portion of the second insulating layer is provided with a contact hole for a second electrode pair, and the first electrode pair is selectively laminated on the second insulating layer. At the curved portion of the second insulating layer The second electrode pair is selectively provided on the second insulating layer separately from the first electrode pair, is connected to the polysilicon layer in the contact hole, and the oxide semiconductor layer is A gas sensor provided in a portion facing one electrode pair and connected to a first electrode pair.
絶縁層と、第五の絶縁層と、ヒータと、第三の電極対
と、酸化物半導体層とを有し、シリコン基板は表面が平
坦なものであり、第三の絶縁層はシリコン基板の主面に
直接的に積層され、第四の絶縁層は第三の絶縁層の上に
接して積層される平坦な部分と、第三の絶縁層に接する
ことのないわん曲の部分とからなり、ここにわん曲の部
分と第三の絶縁層とに囲まれる領域は空間部となり、第
三の電極対は、第四の絶縁層の平坦な部分とわん曲の部
分の上に選択的にかつ離隔して積層され、この際わん曲
の部分に積層される電極対は対向して配置され、ヒータ
は第四の絶縁層の平坦な部分とわん曲の部分の上に選択
的に積層され、第五の絶縁層は窓部を有するとともに、
この窓部を除きヒータと、第四の絶縁層と、第三の電極
対の上に積層されて平坦な部分とわん曲の部分を形成
し、この際窓部は第三の電極対の平坦な部分およびわん
曲の部分、並びにヒータの平坦な部分にそれぞれ設けら
れ、酸化物半導体層は第五の絶縁層のわん曲の部分の上
に選択的に積層され、このとき第五の絶縁層の窓部を介
して、第三の電極対と電気的に接続されるものであるこ
とを特徴とするガスセンサ。2. A semiconductor device comprising a silicon substrate, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a heater, a third electrode pair, and an oxide semiconductor layer. The substrate has a flat surface, the third insulating layer is directly laminated on the main surface of the silicon substrate, and the fourth insulating layer is a flat portion laminated on and in contact with the third insulating layer. And a curved portion that does not come into contact with the third insulating layer, a region surrounded by the curved portion and the third insulating layer becomes a space, and the third electrode pair The four insulating layers are selectively and separately laminated on the flat portion and the curved portion, and the electrode pair laminated on the curved portion is disposed to face each other, and the heater is provided in the fourth portion. Selectively laminated on the flat portion and the curved portion of the insulating layer, the fifth insulating layer has a window,
Except for this window portion, the heater, the fourth insulating layer, and the third electrode pair are stacked to form a flat portion and a curved portion, and the window portion is formed by flattening the third electrode pair. And a curved portion, and a flat portion of the heater, respectively, and the oxide semiconductor layer is selectively laminated on the curved portion of the fifth insulating layer. A gas sensor electrically connected to the third pair of electrodes via the window portion.
の工程はシリコン基板の平坦な１主面に第三の絶縁層を
形成し、第二の工程は、第三の絶縁層の上にポリシリコ
ン層を形成し、第三の工程は、ポリシリコン層をパター
ニングして複数個のメサ形ポリシリコンを形成し、第四
の工程は、第三の絶縁層とメサ形ポリシリコンの上に第
四の絶縁層を形成し、第五の工程は第四の絶縁層の上に
白金層を積層し、次いでパターニングを行ってヒータと
第三の電極対を形成し、この際第三の電極対は第四の絶
縁層の平坦な部分と、わん曲の部分とに選択的にかつ対
向して配置され、ヒータは第四の絶縁層の平坦な部分と
わん曲の部分の上に選択的に配置され、第六の工程は、
第四の絶縁層とヒータと第三の電極対の上に第五の絶縁
層を積層し、次いで第五の絶縁層の所定部をエッチング
して、第三の電極対の平坦部とわん曲部の一部に通ずる
窓と、ヒータの平坦な部分の一部に通ずる窓を形成する
とともに第四と第五の絶縁層を順次エッチングして、第
四と第五の絶縁層のわん曲の部分の周辺部分にポリシリ
コンに通ずる窓を形成してポリシリコンを溶解除去し、
第七の工程は、第五の絶縁層のわん曲の部分に酸化物半
導体層を積層する工程であることを特徴とするガスセン
サの製造方法。3. The method according to claim 1, further comprising a first step to a seventh step, wherein the first step forms a third insulating layer on one flat main surface of the silicon substrate, and the second step includes a third step. Forming a polysilicon layer on the insulating layer; a third step of patterning the polysilicon layer to form a plurality of mesa-type polysilicon; and a fourth step, forming a third insulating layer and the mesa-shaped polysilicon. A fourth insulating layer is formed on the polysilicon, and a fifth step is to stack a platinum layer on the fourth insulating layer, and then perform patterning to form a heater and a third electrode pair. In this case, the third electrode pair is selectively and opposed to the flat portion of the fourth insulating layer and the curved portion, and the heater is provided with the flat portion and the curved portion of the fourth insulating layer. And the sixth step is:
A fifth insulating layer is stacked on the fourth insulating layer, the heater, and the third electrode pair, and then a predetermined portion of the fifth insulating layer is etched to bend with the flat portion of the third electrode pair. A window leading to a part of the heater and a window leading to a part of the flat part of the heater are formed and the fourth and fifth insulating layers are sequentially etched to form a curved part of the fourth and fifth insulating layers. Form a window in the periphery of the part to the polysilicon and dissolve and remove the polysilicon,
The seventh step is a step of laminating an oxide semiconductor layer on a curved portion of the fifth insulating layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40396290A JP2847970B2 (en) | 1989-12-28 | 1990-12-20 | Gas sensor and method of manufacturing the same |
| JP3226270A JPH07110122B2 (en) | 1990-10-04 | 1991-09-06 | Oscillating actuator |
| US07/770,347 US5168184A (en) | 1990-10-04 | 1991-10-03 | Swing-type actuator |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34350289 | 1989-12-28 | ||
| JP1-343502 | 1989-12-28 | ||
| JP40396290A JP2847970B2 (en) | 1989-12-28 | 1990-12-20 | Gas sensor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03293553A JPH03293553A (en) | 1991-12-25 |
| JP2847970B2 true JP2847970B2 (en) | 1999-01-20 |
Family
ID=26577547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40396290A Expired - Fee Related JP2847970B2 (en) | 1989-12-28 | 1990-12-20 | Gas sensor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2847970B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3085749B2 (en) * | 1991-09-13 | 2000-09-11 | 株式会社リコー | Gas sensor |
| DE4314888C1 (en) * | 1993-05-05 | 1994-08-18 | Ignaz Eisele | Method for depositing a total surface (covering) layer through a mask and optional closure of this mask |
| JPH0894561A (en) * | 1994-09-26 | 1996-04-12 | Fuji Electric Co Ltd | Gas sensor and its manufacture |
| FR2736205B1 (en) * | 1995-06-30 | 1997-09-19 | Motorola Semiconducteurs | SEMICONDUCTOR SENSOR DEVICE AND ITS FORMING METHOD |
| US6023091A (en) * | 1995-11-30 | 2000-02-08 | Motorola, Inc. | Semiconductor heater and method for making |
| JP3700378B2 (en) * | 1998-03-04 | 2005-09-28 | 富士電機機器制御株式会社 | Gas detection alarm |
| JP3700379B2 (en) * | 1998-03-04 | 2005-09-28 | 富士電機機器制御株式会社 | Gas detection alarm |
| JP4325133B2 (en) * | 2001-08-27 | 2009-09-02 | 株式会社デンソー | Gas sensor and manufacturing method thereof |
| JP2011106921A (en) * | 2009-11-16 | 2011-06-02 | Kyocera Corp | Substrate for gas sensor, package for gas sensor, and gas sensor |
| JP6842622B2 (en) * | 2015-11-18 | 2021-03-17 | 地方独立行政法人東京都立産業技術研究センター | Flow sensor and its manufacturing method |
-
1990
- 1990-12-20 JP JP40396290A patent/JP2847970B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03293553A (en) | 1991-12-25 |
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