JP2843139B2 - Method of forming wiring on semiconductor substrate - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a technique for forming a wiring having a substantially T-shaped (or mushroom-shaped) cross section on a semiconductor substrate (chip).

2. Description of the Related Art In order to increase the operating speed of a semiconductor transistor, Ga
It is effective to provide a Schottky junction field effect transistor (MESFET) using a high-speed compound semiconductor such as As, and further reduce the gate length as much as possible. However, shortening the gate length means miniaturization of the gate,
This leads to an increase in the electrical resistance of the gate, which in turn hinders the speeding up of the transistor. In view of this, a T-shaped (or mushroom-shaped) gate in which the lower part of the gate that is in contact with the active layer of the semiconductor is made thinner and the upper part is made thicker on the contrary.

Several methods for forming the T-shaped gate have been considered, such as a method using a multilayer resist and direct writing with an electron beam, a method using focused ion beam lithography, a method combining a temporary gate and a planarization technique, and the like. There is.

Problems to be Solved by the Invention In view of the fact that each of the above conventional methods for forming a T-shaped gate requires a special device and complicates the manufacturing process, the applicant of the present application We have already developed a new method using image reverse lithography and filed a patent application (Japanese Patent Application No. 1-120989).
issue). This method does not require special equipment, and the process is simplified compared with the conventional method. However, it is also necessary to use a resist dedicated to image river lithography or to use a flood exposure (post-exposure) time. Need to be precisely controlled.

In contrast, the present invention does not require a special resist,
It is another object of the present invention to provide a simplified method of forming a T-shaped wiring.

Means for Solving the Problems In order to achieve the above object, a method for forming a wiring on a semiconductor substrate according to the present invention is directed to a method for forming a wiring having a substantially T-shaped cross section with a narrow lower part and a wide upper part on a semiconductor substrate. A) forming a temporary wiring having the same width as the lower part; and b) covering the substrate on which the temporary wiring is placed with a resist layer, and then forming a resist layer on the temporary wiring and a small amount of resist on both sides of the temporary wiring. Removing the layer; c) filling the gaps on both sides of the temporary wiring with a molten resist by heating the resist layer; and d) removing the temporary line while leaving the resist layer on the substrate. E) depositing a wiring material layer on the substrate; f) removing the wiring material layer leaving the upper width portion including the portion where the temporary wiring was placed; and g) resist. Removing the layer. The features.

Operation By heating (baking) the resist layer (or the entire substrate) in the above step c), the resist layer is softened and partially melted to fill gaps on both sides of the temporary wiring. Therefore, step d)
As a result, the temporary wiring is removed, so that the resist layer covers the substrate with a hole having the width of the temporary wiring. By depositing the wiring material in the step e) from above, the main wiring is formed in which the width of the portion in contact with the substrate is equal to the width of the temporary wiring. Further, by forming an upper portion having a width larger than that of the lower portion in step f), a wiring having a substantially T-shaped cross section is completed.

Since the resist layer fills the gaps on both sides of the provisional wiring by the baking in the step c), the alignment accuracy for forming the holes in the resist layer in the latter half of the step b) may not be so high (that is, the alignment becomes self-aligned). ing). In general, when a fusible object is heated, the corners are most easily melted and the corners become gentler. Therefore, when the wiring material is deposited on the entire surface in the step e), the material at the corners of the holes of the temporary wiring traces is removed. Cutting is prevented, and a reliable T-shaped wiring can be obtained.

Example Hereinafter, an example of the present invention will be described in describing the overall MESFET manufacturing process. Each step will be described below with reference to FIGS. 2A to 2J, which are cross-sectional views showing each step of the MESFET manufacturing process.

FIG. 2 (a): First, a semi-insulating GaAs (SIGaAs) substrate 1
An N-layer forming resist pattern 3 having a hole 2 of a predetermined size is formed thereon.

FIG. 2 (b): Next, ions of Si, Se, etc. are implanted (arrows) from above the N-layer forming resist pattern 3, whereby an N-layer 4 is formed on the substrate 1. The N layer 4 is the first of the FET
And a predetermined conductivity type is provided by adjusting the conditions of ion implantation.

FIG. 2 (c): The resist pattern 3 for forming the N layer is removed with a stripper or the like.

FIG. 2 (d): A temporary gate layer 5 is formed on the entire surface of the substrate 1 on which the N layer 4 is formed by a sputtering method, a plasma CVD method or the like. The material of the temporary gate layer 5 may be the same as the material used as the protective film (12 in FIG. 2 (h)) in the subsequent annealing step (the step for activating the N layer and the N ⁺ layer).
For example, Si ₃ N ₄ or SiO ₂ can be used. Further, a dist 6 is applied to the upper surface of the temporary gate layer 5.

FIG. 2 (e): By exposing through a predetermined photomask, a portion (temporary gate forming resist pattern) 7 a and a field portion 7 b (fourth portion of the FET) The resist is removed except for the region other than the region where the second semiconductor active layer is formed.

FIG. 2 (f): The temporary gate layer 5 is etched by RIE (reactive ion etching), wet etching with hydrofluoric acid or the like to form a temporary gate pattern 8a and a field protection pattern 3b. In this case, a fine gate pattern can be obtained by performing etching by penetrating into the inside of the boundary between the resists 7a and 7b (side etching). However, in this embodiment, for simplification of description, Straight etching shall be performed.

FIG. 2 (g): From above the temporary gate pattern 8a and the field protection pattern 8b, it is deeper than the N layer 4 and has a high concentration.
An N ⁺ layer 10 is formed in the GaAs substrate 1 by implanting ions (arrows) of Si ⁺ or the like. The two N ⁺ layers 10 separated by the provisional gate pattern 8a form a second semiconductor active layer that becomes the source and drain regions of the FET, respectively.

FIG. 2 (h): While the temporary gate pattern 8a and the field protection pattern 8b are left, the substrate 1 is annealed by heating the substrate 1 after the entire surface of the substrate 1 is covered with the thin annealing protection film 12. As described above, the annealing protective film 12 can be formed by a sputtering method, a plasma CVD method, or the like, and as its material, Si ₃ N ₄ , SiO _2, or the like can be used.
By this annealing, the N layer 4 and the N ⁺ layer 10 are activated. Thereafter, the annealing protective film 12 is removed by anisotropic dry etching using RIE or the like.

FIG. 2 (i): A T-shaped (mushroom type) gate electrode 19 is formed using the temporary gate pattern 8a.

Since the step of forming the T-shaped gate is a part according to the present invention, it will be described in detail with reference to FIGS.
For simplicity, FIG. 1 shows only a portion around the gate electrode.

FIG. 1 (a): As described above, a temporary gate 8a is formed on the substrate 1 at a lower portion (foot) of a portion where a T-shaped gate electrode is to be formed later. As a material of the temporary gate 8a,
SiN, SiO ₂ , SiON or the like can be used.

FIG. 1B: A positive resist 21 is applied so as to completely cover the temporary gate 8a.

FIG. 1 (c): The provisional gate 8a is formed by the exposure / development process.
A small gap 22 is made around the hole, and a hole is made in the resist 21. As will be described later, the alignment of the gap 22 does not need to be strict.

FIG. 1 (d): The substrate 1 is placed in a furnace and baked.
The baking temperature is such that the upper surface of the resist 21 melts and flows a little. However, if the temperature is too high, it is difficult to dissolve and remove the resist 21 with an organic solvent later. 200 ° C). By this baking process, the gap 22 around the temporary gate 8a is filled, and the resist 21 covers the substrate 1 except for the width of the temporary gate 8a. For this reason, the exposure alignment for forming the holes in the resist 21 in the previous step (c) can be performed relatively roughly, and the process management becomes easy. Further, since the provisional gate 8a is provided, there is no possibility that the resist 21 flows too much and the gate width becomes too thin or cut.

FIG. 1E: The temporary gate 8a is removed.

FIG. 1 (f): Metal layer 22 is applied to substrate 1 from above resist 21
Is deposited on the entire surface of the substrate.

FIG. 1 (g): An upper layer resist 23 is applied on the metal layer 22.

FIG. 1 (h): The provisional gate 8a is exposed by the exposure / development process.
The upper layer resist 23 is removed except for the portion where the pattern has been formed, leaving a wider portion 24 (that is, the upper portion of the T-shaped gate electrode = width of the head) 24. Then, by implanting ions such as Ar ⁺ , the portion 24
Then, the metal layer 22 other than the portion that has been attacked is removed (ion milling).

FIG. 1 (i): A state in which a metal layer 22 having a narrow lower portion and a wider upper portion is left in a gate portion, and a T-shaped gate electrode 19 is formed.

FIG. 1 (j): The upper resist 24 on the gate electrode 19 and the resist 21 on the left and right sides of the foot are removed with an organic solvent.

This is the state of FIG. 2 (i). By the baking step (FIG. 1 (d)), the lower part (foot) of the gate electrode 19 is formed.
Is narrowed in the same manner as the width of the provisional gate 8a, while the upper portion (head) of the gate electrode 19 is formed by the process of FIG.
Has become wider. Further, since the corners of the resist 21 on both sides of the temporary gate 8a are removed and smoothed by the baking process, when the gate metal material (metal) layer is formed on the substrate 1 in the process of FIG. The material (metal) is prevented from being cut at the part.

FIG. 2 (j): Thereafter, the source and drain electrodes 16 are formed, and the manufacture of the MESFET is completed.

In the above embodiment, the method of forming a T-shaped wiring according to the present invention was used for forming a gate electrode of a MESFET. However, the present invention may be applied to the formation of wiring of various semiconductor chips such as a HEMT. Can be.

Effect of the Invention As described above, according to the present invention, a T-shape can be obtained in a simple process without using a special apparatus or resist material, and without the need for complicated control such as delicate exposure time management. A type (mushroom type) wiring can be formed. Therefore, it is necessary to reduce the gate length while reducing the resistance while forming the gate electrode, or to reduce the stray capacitance between the substrate and the wiring such as the wiring on various semiconductor chips. Applicable to formation.

[Brief description of the drawings]

1 (a) to 1 (j) are cross-sectional views showing steps of manufacturing a MESFET gate electrode using the present invention, and FIGS.
(J) is sectional drawing which shows each process of MESFET manufacture.

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812 H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/51 H01L 29/872

Claims (1)

(57) [Claims] 1. A method for forming a wiring having a substantially T-shaped cross section with a narrow lower part and a wide upper part on a semiconductor substrate, comprising: a) forming a temporary wiring having the same width as the lower part; Removing the resist layer on the temporary wiring and a small amount of the resist layer on both sides of the temporary wiring after covering the placed substrate with a resist layer; c) heating the resist layer to form gaps on both sides of the temporary wiring; D) removing the temporary wiring while leaving the resist layer on the substrate; e) depositing a wiring material layer on the substrate; and f) placing the temporary wiring. A method of forming a wiring on a semiconductor substrate, comprising: a step of removing a wiring material layer while leaving a portion of the upper width including the above-mentioned portion; and g) a step of removing a resist layer.