JP2842327B2 - Wideband multiplier - Google Patents
Wideband multiplierInfo
- Publication number
- JP2842327B2 JP2842327B2 JP23073195A JP23073195A JP2842327B2 JP 2842327 B2 JP2842327 B2 JP 2842327B2 JP 23073195 A JP23073195 A JP 23073195A JP 23073195 A JP23073195 A JP 23073195A JP 2842327 B2 JP2842327 B2 JP 2842327B2
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- Japan
- Prior art keywords
- circuit
- output
- input
- double
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】[0001]
【発明の属する技術分野】本発明は、二逓倍器に関し、
特に、２つの入力信号の積を出力する二重平衡型乗算回
路を用いて二逓倍器を構成するものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a doubler,
In particular, the present invention relates to a configuration in which a doubler is configured using a double balanced type multiplication circuit that outputs a product of two input signals.
【０００２】[0002]
【従来の技術】従来、二重平衡型乗算回路に入力する２
つの信号間に、９０度の位相差（遅延）を与える移相回
路を設ける逓倍器として図４に示すようなものがある。
図４に示す逓倍器は、ＮＰＮ型バイポーラトランジスタ
等の能動素子で構成される二重平衡型乗算回路と、半導
体基板上に一般的に形成される受動素子の抵抗、容量か
ら構成される移相回路から成り立っている。2. Description of the Related Art Conventionally, 2 input to a double balanced type multiplying circuit is known.
FIG. 4 shows a multiplier provided with a phase shift circuit for providing a phase difference (delay) of 90 degrees between two signals.
The multiplier shown in FIG. 4 is a phase shifter composed of a double-balanced multiplication circuit composed of active elements such as NPN-type bipolar transistors and the resistance and capacitance of passive elements generally formed on a semiconductor substrate. It consists of circuits.
【０００３】前記移相回路は、入力信号を２つに分岐
し、一方は入力信号に対して直列に容量（Ｃｏ）を接続
し、並列に抵抗（Ｒｏ）を接続し接地する微分回路（Ｈ
ＰＦ（ハイパスフィルター）型）で出力端子（２）より
出力信号（ｖ１）を得る。又、もう一方は入力信号に対
して直列に抵抗（Ｒｏ）を接続し、並列に容量（Ｃｏ）
を接続し接地する積分回路（ＬＰＦ（ローパスフィルタ
ー）型）で出力端子（３）より出力信号（ｖ２）を得
る。The phase shift circuit divides an input signal into two, one of which is connected to a capacitance (Co) in series with the input signal and the other is a differential circuit (H) connected to a resistor (Ro) in parallel and grounded.
An output signal (v1) is obtained from an output terminal (2) by a PF (high-pass filter) type. On the other hand, a resistor (Ro) is connected in series to the input signal, and a capacitor (Co) is connected in parallel.
An output signal (v2) is obtained from an output terminal (3) by an integrating circuit (LPF (low-pass filter) type) connected to and grounded.
【０００４】また、前記二重平衡型乗算回路は、トラン
ジスタ（Ｑ１）（Ｑ２）及びトランジスタ（Ｑ３）（Ｑ
４）がそれぞれ上段エミッタ接地型差動増幅回路を形成
し、トランジスタ（Ｑ５）（Ｑ６）が下段エミッタ接地
型差動増幅回路を形成し、この上段、下段の差動増幅回
路が２段縦積みに接続される一種の２段積カスケード型
差動増幅回路を構成し、上段エミッタ接地型差動増幅回
路を形成するトランジスタ（Ｑ１）と（Ｑ３）のコレク
タどおしを接続し、負荷抵抗（Ｒ１）を介し電源電圧端
子（９）に接続される。Further, the double balanced type multiplication circuit includes transistors (Q1) and (Q2) and transistors (Q3) and (Q3)
4) each form an upper-stage grounded-type differential amplifier circuit, and the transistors (Q5) and (Q6) form a lower-stage grounded-type differential amplifier circuit. The upper and lower differential amplifier circuits are vertically stacked in two stages. A two-stage cascade-type differential amplifier circuit is connected to the transistors (Q1) and (Q3), which form an upper-stage emitter-grounded differential amplifier circuit. R1) is connected to the power supply voltage terminal (9).
【０００５】同様に、上段エミッタ接地型差動増幅回路
を形成するトランジスタ（Ｑ２）（Ｑ４）のコレクタど
おしを接続し、負荷抵抗（Ｒ２）を介し電源電圧端子
（９）に接続される。（８）は定電流源であって、前記
二重平衡型乗算回路の電流を決定する。（１５）は出力
端子であって、トランジスタ（Ｑ１）（Ｑ３）のコレク
タ電流の和が負荷抵抗（Ｒ１）によって電圧に変換さ
れ、出力信号（ｖｏ１）を得、（１６）も同様に出力端
子であってトランジスタ（Ｑ２）（Ｑ４）のコレクタ電
流の和が負荷抵抗（Ｒ２）によって電圧に変換され、出
力信号（ｖｏ２）を得る。Similarly, the collectors of transistors (Q2) and (Q4) forming an upper-stage emitter-grounded differential amplifier circuit are connected to each other and connected to a power supply voltage terminal (9) via a load resistor (R2). . (8) is a constant current source, which determines a current of the double balanced multiplication circuit. (15) is an output terminal, the sum of the collector currents of the transistors (Q1) and (Q3) is converted into a voltage by the load resistor (R1), and an output signal (vo1) is obtained. Then, the sum of the collector currents of the transistors (Q2) and (Q4) is converted into a voltage by the load resistor (R2) to obtain an output signal (vo2).
【０００６】図４において、（４）、（５）、（６）、
（７）は、前記二重平衡型乗算回路の入力端子であっ
て、入力端子（４）には前記微分回路からの出力信号
（ｖ１）とベース電位が高抵抗（Ｒｂ１）を介し与えら
れ、入力端子（５）には、ベース電位が高抵抗（Ｒｂ
１）を介し与えられ、容量（Ｃｂ１）によって接地され
る。入力端子（６）には、前記積分回路からの出力信号
（ｖ２）とベース電位が高抵抗（Ｒｂ２）を介し与えら
れ、入力端子（７）には、ベース電位が高抵抗（Ｒｂ
２）を介し与えられ、容量（Ｃｂ２）によって接地され
る。In FIG. 4, (4), (5), (6),
(7) is an input terminal of the double balanced type multiplication circuit, and an output signal (v1) from the differentiation circuit and a base potential are given to an input terminal (4) via a high resistance (Rb1); The input terminal (5) has a high potential (Rb
1) and grounded by a capacitor (Cb1). The input terminal (6) is supplied with the output signal (v2) from the integrating circuit and a base potential via a high resistance (Rb2), and the input terminal (7) is provided with a base potential having a high resistance (Rb2).
2) and grounded by a capacitor (Cb2).
【０００７】次に、動作について説明する。前記移相回
路は、微分回路と積分回路より成り立っているが、微分
回路は伝達関数で表すと、［数１］で表すことができ、Next, the operation will be described. The phase shift circuit is composed of a differentiation circuit and an integration circuit. The differentiation circuit can be represented by [Equation 1] when represented by a transfer function.
【数１】 入力と出力振幅の比、つまり利得Ｇ（ＨＰＦ）は、［数
２］となり、(Equation 1) The ratio between the input and output amplitudes, that is, the gain G (HPF) is given by [Equation 2].
【数２】 位相角φ（ＨＰＦ）は、−ｔａｎ−１（ωＴ）で表わせ
る。（Ｔ＝ＲｏＣｏ、ωは角周波数）(Equation 2) The phase angle φ (HPF) can be represented by -tan −1 (ωT). (T = RoCo, ω is angular frequency)
【０００８】又、積分回路は伝達関数で表わすと、［数
３］で表すことができ、When the integration circuit is represented by a transfer function, it can be represented by [Equation 3].
【数３】 利得Ｇ（ＬＰＦ）は、［数４］となり、(Equation 3) The gain G (LPF) becomes [Equation 4],
【数４】 位相角φ（ＬＰＦ）は、ｔａｎ−１（１／ωＴ）で表わ
すことができる。(Equation 4) The phase angle φ (LPF) can be represented by tan −1 (1 / ωT).
【０００９】これをグラフに示すと、図３のようにな
る。図３は、移相回路を構成する微分回路、積分回路の
利得と位相特性図である。横軸は、ωＴ＝２πｆＣｏＲ
ｏであり、縦軸の左が利得［ｄＢ］、縦軸の右が位相
［度］である。前記微分回路、積分回路を構成する抵抗
値、容量値をそれぞれ同一値とすると、周波数が変化し
ても、微分回路と積分回路の出力位相差は常に９０度で
あることがわかる。また、出力振幅は周波数が変化する
と微分回路のほうは周波数が低くなるにつれ振幅が減衰
し、積分回路は周波数が高くなるにつれ振幅が減衰して
いく特性を示す。This is shown in a graph in FIG. FIG. 3 is a diagram illustrating gain and phase characteristics of a differentiating circuit and an integrating circuit that constitute a phase shift circuit. The horizontal axis is ωT = 2πfCoR
o, the left side of the vertical axis is the gain [dB], and the right side of the vertical axis is the phase [degree]. Assuming that the resistance value and the capacitance value constituting the differentiating circuit and the integrating circuit are the same, the output phase difference between the differentiating circuit and the integrating circuit is always 90 degrees even if the frequency changes. Also, the output amplitude of the differentiating circuit decreases as the frequency decreases as the frequency changes, and the output circuit attenuates as the frequency increases as the frequency increases.
【００１０】次に、前記二重平衡型乗算回路の動作につ
いて説明する。図４の入力信号端子（４）、（６）には
同一周波数で、入力信号（ｖ１）が（ｖ２）より９０度
位相が進んでいるため、入力信号（ｖ１）、（ｖ２）は
［数５］の式（１）のように表わすことができる。Next, the operation of the double balanced multiplication circuit will be described. The input signals (v1) and (v2) have the same frequency at the input signal terminals (4) and (6) in FIG. 5] as in equation (1).
【数５】 （Ａは入力信号ｖ１の振幅、Ｂは入力信号ｖ２の振幅、
ωは角周波数）(Equation 5) (A is the amplitude of the input signal v1, B is the amplitude of the input signal v2,
ω is the angular frequency)
【００１１】前記入力信号（ｖ１）、（ｖ２）が、二重
平衡型乗算回路に入力されると、入力信号（ｖ１）、
（ｖ２）の積が出力信号（ｖｏ１）、（ｖｏ２）とな
り、［数６］の式（２）（２，）のように表わすことが
できる。When the input signals (v1) and (v2) are input to the double balanced multiplication circuit, the input signals (v1) and (v2)
The product of (v2) becomes the output signals (vo1) and (vo2), and can be expressed as Expression (2) (2 , ) in [Equation 6].
【数６】 従って、出力端子（１５）からは、振幅（１／２）・Ａ
・Ｂ・Ｇｃの入力信号の２倍の周波数の信号が出力さ
れ、出力端子（１６）からは、出力端子（１５）からの
出力信号の逆相の信号が出力することになる。(Equation 6) Therefore, from the output terminal (15), the amplitude (１ ／) · A
A signal having a frequency twice as high as that of the input signal of B · Gc is output, and a signal having the opposite phase to the output signal from the output terminal (15) is output from the output terminal (16).
【００１２】ここで、前記二重平衡型乗算回路に入力す
る信号に９０度位相差を与えて入力する効果について説
明する。入力信号（ｖ１）、（ｖ２）に位相差がない場
合、上述した式（１）同様、入力信号（ｖ１）、（ｖ
２）は、ｖ１＝ＡｓｉｎωＴ、 ｖ２＝ＢｓｉｎωＴと
なり、出力信号ｖｏ１は、［数７］となり、出力信号
は、振幅（１／２）Ａ・Ｂ・Ｇｃで、入力信号の２倍の
周波数の信号と（１／２）Ａ・Ｂ・Ｇｃの直流成分が出
力することになり、この直流成分が出力端子部の電圧オ
フセットを与えることになり、変換利得の劣化及び出力
波形の歪みを起こすことになる。Here, the effect of inputting a signal input to the double balanced multiplication circuit with a phase difference of 90 degrees will be described. When there is no phase difference between the input signals (v1) and (v2), the input signals (v1) and (v
2) is v1 = AsinωT, v2 = BsinωT, the output signal vo1 is [Equation 7], and the output signal is a signal having an amplitude (）) A · B · Gc and twice the frequency of the input signal. And (1/2) A.B.Gc DC components are output, and this DC component gives a voltage offset at the output terminal, resulting in deterioration of conversion gain and distortion of the output waveform. Become.
【数７】 (Equation 7)
【００１３】これは、特開昭６１−１０５９にも掲題さ
れており、公知の事実である。ところで、上述した式
（２）において、前記二重平衡型乗算回路の変換利得を
総合してＧｃとして説明してきたが、前記二重平衡型乗
算回路が上段エミッタ接地型差動増幅回路と下段エミッ
タ接地型差動増幅回路の２段積カスケード接続であるた
め、総合変換利得Ｇｃは、前記上段エミッタ接地型差動
増幅回路の変換周波数での、利得 Ｋ１Ｇ１ と、前記
下段エミッタ接地型差動増幅回路の変換周波数での、利
得Ｋ２Ｇ２ との和となる。（Ｋ１、Ｋ２は、入力周波
数と変換周波数との差によって生じる利得の変化量とす
る。）This is also known in JP-A-61-1059 and is a known fact. By the way, in the above equation (2), the conversion gain of the double balanced multiplication circuit has been described as Gc. However, the double balanced multiplication circuit is composed of an upper-stage emitter grounded differential amplifier circuit and a lower-stage emitter. for a 2 Danseki cascaded grounded type differential amplifier circuit, the overall conversion gain Gc is the conversion frequency of the upper emitter grounded type differential amplifier circuit, the gain K 1 G 1, the lower grounded-emitter differential It is the sum with the gain K 2 G 2 at the conversion frequency of the dynamic amplifier circuit. (K 1 and K 2 are the amounts of change in gain caused by the difference between the input frequency and the conversion frequency.)
【００１４】又、前記上段エミッタ接地型差動増幅回路
に流れる電流は、下段エミッタ接地型差動増幅回路のス
イッチングによって決定されるため、前記二重平衡型乗
算回路の総合変換利得Ｇｃは、下段エミッタ接地型差動
増幅回路の利得の依存性が強くなる。従って、 Ｇｃ＝Ｋ１Ｇ１＋Ｋ２Ｇ２ Ｋ１Ｇ１＜Ｋ２Ｇ２ の関係として表わすことができ、逓倍器の出力（ｖｏ
１）は、式（２）より、［数８］の式（３）のように表
わすことができる。Further, since the current flowing through the upper-stage common-emitter differential amplifier circuit is determined by switching of the lower-stage common-emitter differential amplifier circuit, the total conversion gain Gc of the double-balanced multiplying circuit is lower. The dependency of the gain of the common-emitter type differential amplifier circuit is increased. Therefore, Gc = K 1 G 1 + K 2 G 2 K 1 G 1 <K 2 G 2 , and the output of the multiplier (vo
1) can be expressed as Expression (3) of [Equation 8] from Expression (2).
【数８】 （Ｋ１、Ｋ２は、入力周波数が同じであるためＫ１＝Ｋ
２＝Ｋとする）(Equation 8) (K 1 and K 2 have the same input frequency, so K 1 = K
2 = K)
【００１５】従って、図５に示す様な前記微分回路の出
力を前記二重平衡型乗算回路の上段エミッタ接地型差動
増幅回路のベースに入力し、前記積分回路の出力を下段
エミッタ接地型差動増幅回路のベースに入力する前記逓
倍器積分回路の振幅特性の依存性が強く現れ、前記逓倍
器の出力振幅（変換利得）は図５に示す様な周波数特性
となる。なお、図５は、従来の逓倍器の各部における信
号の周波数特性図で、図５（ａ）において、横軸は移相
回路入力周波数ｆ（Ｈｚ）、縦軸は移相回路出力振幅で
あり、図５（ｂ）において横軸は二重平衡型乗算回路出
力周波数、縦軸は二重平衡型乗算回路出力振幅である。Therefore, the output of the differentiating circuit as shown in FIG. 5 is input to the base of the upper-stage grounded-type differential amplifier circuit of the double-balanced multiplier, and the output of the integrating circuit is connected to the lower-stage grounded-type differential amplifier. The dependence of the amplitude characteristic of the multiplier integrator circuit input to the base of the dynamic amplifier circuit strongly appears, and the output amplitude (conversion gain) of the multiplier has a frequency characteristic as shown in FIG. FIG. 5 is a frequency characteristic diagram of a signal in each section of the conventional frequency multiplier. In FIG. 5A, the horizontal axis represents the phase shift circuit input frequency f (H z ), and the vertical axis represents the phase shift circuit output amplitude. In FIG. 5B, the horizontal axis represents the output frequency of the double balanced multiplier circuit, and the vertical axis represents the output amplitude of the double balanced multiplier circuit.
【００１６】また、逆に、前記積分回路の出力を前記二
重平衡型乗算回路の上段エミッタ接地型差動増幅回路の
ベースに入力し、前記微分回路の出力を下段エミッタ接
地型差動増幅回路のベースに入力すると、微分回路の振
幅特性の依存性が強く現れ、図６に示す様な周波数特性
となる。なお、図６は従来の逓倍器（二重平衡型乗算回
路の入力入れ替え時）の各部における信号の周波数特性
図で、図６（ａ）において、横軸は移相回路入力周波数
ｆ（Ｈｚ）、縦軸は移相回路出力振幅であり、図６
（ｂ）において横軸は二重平衡型乗算回路出力周波数、
縦軸は二重平衡型乗算回路出力振幅である。Conversely, the output of the integrator is input to the base of a common-emitter differential amplifier at the upper stage of the double balanced multiplier, and the output of the differentiator is coupled to the common-emitter lower amplifier at the lower stage. , The dependence of the amplitude characteristic of the differentiating circuit appears strongly, resulting in a frequency characteristic as shown in FIG. Note that FIG. 6 is a frequency characteristic diagram of the signal in each part of (input time replacement of double-balanced multiplier circuit) conventional multiplier, in FIG. 6 (a), the horizontal axis represents the phase shift circuit input frequency f (H z 6), the vertical axis represents the output amplitude of the phase shift circuit, and FIG.
In (b), the horizontal axis is the output frequency of the double balanced type multiplication circuit,
The vertical axis represents the output amplitude of the double balanced multiplication circuit.
【００１７】[0017]
【発明が解決しようとする課題】二重平衡型乗算回路に
入力する２つの信号間に９０度の位相差を与える移相回
路を、半導体基板上に一般的に形成される受動素子であ
る、抵抗と容量で微分回路、積分回路を構成する場合、
素子を近接配置することにより、相対性度は良く、製造
工程における制御が難しいため、絶対精度があまり良く
ないという特徴をもっている。従って、抵抗値、容量値
を任意に決定した場合、図３に示すように、位相差特性
は、構成素子の相対精度のよって決まり常に９０度の位
相差が与えられるが、振幅特性は構成素子の絶対精度に
より決まり、構成素子のばらつきによって、振幅特性が
変化する。A phase shift circuit for providing a phase difference of 90 degrees between two signals input to a double balanced multiplication circuit is a passive element generally formed on a semiconductor substrate. When configuring a differentiation circuit and an integration circuit with resistance and capacitance,
By arranging the elements close to each other, the degree of relativeity is good and the control in the manufacturing process is difficult, so that the absolute accuracy is not very good. Therefore, when the resistance value and the capacitance value are arbitrarily determined, as shown in FIG. 3, the phase difference characteristic is determined by the relative accuracy of the constituent elements, and a phase difference of 90 degrees is always given. And the amplitude characteristics change due to the variation of the constituent elements.
【００１８】また、前記移相回路の周波数特性について
も同様で、前記微分回路より出力する信号は周波数が低
くなるにつれ振幅が減衰し、前記積分回路より出力する
信号は周波数が高くなるにつれ振幅が減衰していく。従
って、前記移相器からの出力を二重平衡型乗算回路に入
力すると、入力周波数の変化及び移相回路を構成する素
子のばらつきによって、入力振幅が変わり、二重平衡型
乗算回路の出力振幅（変換利得）が大きく変化してしま
うという問題があった。The same applies to the frequency characteristics of the phase shift circuit. The signal output from the differentiating circuit attenuates in amplitude as the frequency decreases, and the signal output from the integrator circuit increases in amplitude as the frequency increases. Decays. Therefore, when the output from the phase shifter is input to the double balanced multiplication circuit, the input amplitude changes due to the change in input frequency and the variation of the elements constituting the phase shift circuit, and the output amplitude of the double balanced multiplication circuit is changed. (Conversion gain) is greatly changed.
【００１９】[0019]
【課題を解決するための手段】本発明は、入力した信号
を２つに分岐し、それぞれの信号に９０度の位相差をも
たせて出力する移相回路と、周波数変換器として用いら
れる二重平衡型乗算回路を２つ備え、前記移相回路から
の２つの出力信号を、前記二重平衡型乗算回路のそれぞ
れに、たすき入力することを特徴とする逓倍器である。According to the present invention, there is provided a phase shifter which splits an input signal into two signals and outputs each signal with a phase difference of 90 degrees, and a doubler used as a frequency converter. A multiplier comprising two balanced multiplication circuits, wherein two output signals from the phase shift circuit are input to each of the double balanced multiplication circuits.
【００２０】また、本発明は、前記移相回路は、半導体
基板上に形成される受動素子である容量、抵抗、インダ
クタで構成し、一方は微分回路で、もう一方は、積分回
路で、それぞれの出力の位相差が常に９０度である移相
回路を具備したことを特徴とする上記に記載の逓倍器で
ある。Further, according to the present invention, the phase shift circuit comprises a capacitance, a resistor, and an inductor, which are passive elements formed on a semiconductor substrate. One is a differentiation circuit, and the other is an integration circuit. Wherein the phase difference of the output of the multiplier is always 90 degrees.
【００２１】[0021]
【作用】本発明において、逓倍器は入力信号を２つに分
岐し、それぞれの信号間の位相差を９０度として出力す
る移相回路と、二重平衡型乗算回路を２つ備え、前記二
重平衡型乗算回路１の出力端と前記二重平衡型乗算回路
２の出力端を接続し、出力を与える乗算回路を備え、前
記移相回路の９０度位相差を与えられた２つの信号を前
記二重平衡型乗算回路１の入力端子と前記二重平衡型乗
算回路２の入力端子それぞれに、たすき入力するもの
で、入力振幅特性の変化分を前記二重平衡型乗算回路１
の出力振幅変化と前記二重平衡型乗算回路２の出力振幅
変化を合成し、互いの変化分を相殺し合い、広帯域に一
定の出力振幅変化を得ることができるものである。In the present invention, the multiplier is provided with two phase shifters for splitting an input signal into two and outputting a phase difference of 90 degrees between the two signals, and two double-balanced multipliers. An output terminal of the double-balanced multiplication circuit 1 is connected to an output terminal of the double-balanced multiplication circuit 2, and a multiplication circuit for providing an output is provided. The input terminal of the double-balanced multiplication circuit 1 and the input terminal of the double-balanced multiplication circuit 2 are cross-input to each other.
And the output amplitude change of the double balanced type multiplying circuit 2 are combined to cancel out the mutual change, thereby obtaining a constant output amplitude change over a wide band.
【００２２】[0022]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【００２３】[0023]
【実施例】図１は、本発明による実施例の広帯域逓倍器
の回路構成図である。移相回路は、入力端子（１）より
入力した信号を２つに分岐し、一方は入力信号に対して
直列に容量（Ｃｏ）を接続し、並列に抵抗（Ｒｏ）を接
続し接地する微分回路（ＨＰＦ型）で出力端子（２）よ
り出力信号（ｖ１）を得る。又、もう一方は入力信号に
対して直列に抵抗（Ｒｏ）を接続し、並列に容量（Ｃ
ｏ）を接続し、接地する積分回路（ＬＰＦ型）で出力端
子（３）より出力信号（ｖ２）を得る。FIG. 1 is a circuit diagram of a wideband multiplier according to an embodiment of the present invention. The phase shift circuit branches a signal input from an input terminal (1) into two, one of which connects a capacitance (Co) in series with the input signal, and connects a resistor (Ro) in parallel with the input signal and grounds the differential. An output signal (v1) is obtained from an output terminal (2) by a circuit (HPF type). On the other hand, a resistor (Ro) is connected in series to the input signal, and a capacitor (C
o), and an output signal (v2) is obtained from the output terminal (3) by an integrating circuit (LPF type) that is grounded.
【００２４】そして、二逓倍周波数変換を行う乗算回路
は、２つの二重平衡型乗算回路で構成され、二重平衡型
乗算回路１はトランジスタ（Ｑ１）、（Ｑ２）及びトラ
ンジスタ（Ｑ３）、（Ｑ４）がそれぞれ、上段エミッタ
接地型差動増幅回路を形成し、トランジスタ（Ｑ５）、
（Ｑ６）が下段のエミッタ接地型差動増幅回路を形成
し、この上段、下段の差動増幅回路が２段縦積みに接続
される一種の２段積カスケード型差動増幅回路を構成し
ている。The multiplier for performing the double frequency conversion is composed of two double balanced multipliers. The double balanced multiplier 1 has transistors (Q1) and (Q2) and transistors (Q3) and (Q3). Q4) respectively form an upper-stage grounded-type differential amplifier circuit, and include a transistor (Q5),
(Q6) forms a lower-stage grounded-type differential amplifier circuit, and forms a two-stage cascade-type differential amplifier circuit in which the upper and lower differential amplifier circuits are vertically connected in two stages. I have.
【００２５】また、二重平衡型乗算回路２も同様に、ト
ランジスタ（Ｑ１１）、（Ｑ１２）及びトランジスタ
（Ｑ１３）、（Ｑ１４）が上段エミッタ接地型差動増幅
回路を形成し、トランジスタ（Ｑ１５）、（Ｑ１６）が
下段エミッタ接地型差動増幅回路を形成し、一種の２段
積カスケード型差動増幅回路を構成している。Similarly, in the double balanced multiplication circuit 2, the transistors (Q11) and (Q12) and the transistors (Q13) and (Q14) form an upper-stage grounded-type differential amplifier circuit, and the transistor (Q15) , (Q16) form a lower-stage grounded-type differential amplifier circuit, and constitute a kind of two-stage cascaded differential amplifier circuit.
【００２６】そして、前記二重平衡型乗算回路１のトラ
ンジスタ（Ｑ１）、（Ｑ３）の共通コレクタと、前記二
重平衡型乗算回路２のトランジスタ（Ｑ１１）、（Ｑ１
３）の共通コレクタとを接続し、前記二重平衡型乗算回
路１と前記二重平衡型乗算回路２の合成した出力（ｖｏ
１）を得る出力端子（１５）と同様に、トランジスタ
（Ｑ２）、（Ｑ４）の共通コレクタと、トランジスタ
（Ｑ１２）、（Ｑ１４）の共通コレクタとを接続し、合
成した出力（ｖｏ２）を得る出力端子（１６）を具備し
た２セル構成二重平衡型乗算回路である。The common collector of the transistors (Q1) and (Q3) of the double balanced multiplication circuit 1 and the transistors (Q11) and (Q1) of the double balanced multiplication circuit 2
3), and the combined output (vo) of the double-balanced multiplier 1 and the double-balanced multiplier 2 is connected.
Similarly to the output terminal (15) for obtaining 1), the common collector of the transistors (Q2) and (Q4) and the common collector of the transistors (Q12) and (Q14) are connected to obtain a combined output (vo2). This is a two-cell double balanced type multiplying circuit having an output terminal (16).
【００２７】図１において、（８）は定電流源であっ
て、前記二重平衡型乗算回路１と二重平衡型乗算回路２
の電流を決定する。（９）は、電源端子であって、電源
電圧が印加される。そして、前記２セル構成二重平衡型
乗算回路のトランジスタのベース電位は適切な電位（Ｖ
ｂ１）、（Ｖｂ２）がそれぞれ高抵抗（Ｒｂ１）、（Ｒ
ｂ２）を介し与えられ、基準部トランジスタ（Ｑ２）
（Ｑ３）及び（Ｑ７）と、（Ｑ１２）（Ｑ１３）及び
（Ｑ１６）のベースは、高周波的に接地されるよう、そ
れぞれ容量（Ｃｂ１）と（Ｃｂ２）で接地される。次に
前記移相回路と前記２セル構成In FIG. 1, reference numeral (8) denotes a constant current source, and the double balanced multiplication circuit 1 and the double balanced multiplication circuit 2
Is determined. (9) is a power supply terminal to which a power supply voltage is applied. The base potential of the transistor of the two-cell double-balanced multiplication circuit is set to an appropriate potential (V
b1) and (Vb2) are the high resistances (Rb1) and (Rb1), respectively.
b2), the reference transistor (Q2)
The bases of (Q3) and (Q7) and the bases of (Q12), (Q13) and (Q16) are grounded by capacitors (Cb1) and (Cb2), respectively, so as to be grounded at high frequencies. Next, the phase shift circuit and the two-cell configuration
【００２８】二重平衡型乗算回路との接地について説明
する。前記移相回路を構成する微分回路よりの出力信号
（ｖ１）は、２つに分岐されＤＣ成分を除去する容量
（Ｃ）を通り、次段の二重平衡型乗算回路に入力するた
め、高抵抗（Ｒｂ１）、（Ｒｂ２）を介し、適切な電位
（Ｖｂ１）と（Ｖｂ２）がそれぞれ与えられ、一方は、
二重平衡型乗算回路１の上段エミッタ接地型差動増幅回
路を形成するトランジスタの共通ベース信号入力端子
（４）に入力され、もう一方は、二重平衡型乗算回路２
の下段エミッタ接地型差動増幅回路を形成するトランジ
スタの信号入力端子（１３）に入力される。The grounding with the double balanced multiplication circuit will be described. The output signal (v1) from the differentiating circuit that constitutes the phase shift circuit passes through the capacitor (C) that is branched into two and removes the DC component, and is input to the next-stage double-balanced multiplying circuit. Appropriate potentials (Vb1) and (Vb2) are given via resistors (Rb1) and (Rb2), respectively.
The double balanced multiplication circuit 1 is inputted to a common base signal input terminal (4) of a transistor forming the upper-stage grounded emitter differential amplifier circuit, and the other is connected to the double balanced multiplication circuit 2
Is input to a signal input terminal (13) of a transistor forming the lower-stage grounded-emitter differential amplifier circuit.
【００２９】また、積分回路よりの出力信号（ｖ２）も
２つに分岐され、同様にＤＣ成分を除去する容量（Ｃ）
を通り、高抵抗（Ｒｂ１）、（Ｒｂ２）を介し、適切な
電位（Ｖｂ１）、（Ｖｂ２）がそれぞれ与えられ、一方
は二重平衡型乗算回路１の下段エミッタ接地型差動増幅
回路を形成するトランジスタの信号入力端子（６）に入
力され、もう一方は、二重平衡型乗算回路２の上段エミ
ッタ接地型差動増幅回路を形成するトランジスタの共通
ベース信号入力端子（１１）に入力される。The output signal (v2) from the integrating circuit is also branched into two, and a capacitor (C) for removing a DC component similarly.
And the appropriate potentials (Vb1) and (Vb2) are respectively applied through the high resistances (Rb1) and (Rb2), and one of them forms the lower-stage grounded-type differential amplifier circuit of the double-balanced multiplier circuit 1. The other input is input to a common base signal input terminal (11) of a transistor forming the upper-stage grounded-type differential amplifier circuit of the double balanced type multiplier 2. .
【００３０】従って、二重平衡型乗算回路１としての出
力振幅は、式（３）より （１／２）・Ｋ２・（Ｇ１Ａ）・（Ｇ２Ｂ） 、となり、二重平衡型乗算回路２としての出力振幅は、
式（３）より （１／２）・Ｋ２・（Ｇ１Ｂ）・（Ｇ２Ａ） 、となり、前記２セル構成二重平衡型乗算回路の出力振
幅は、合成出力となるため、［数９］となる。Therefore, the output amplitude of the double balanced multiplication circuit 1 is (1/2) · K 2 · (G 1 A) · (G 2 B) according to equation (3). The output amplitude of the multiplier 2 is
From Equation (3), (1/2) · K 2 · (G 1 B) · (G 2 A) is obtained, and the output amplitude of the two-cell double-balanced multiplier is a combined output. Equation 9].
【数９】 (Equation 9)
【００３１】図２に示すように、周波数の変化に対して
前記移相回路の振幅は変化し、それに追随し、前記二重
平衡型乗算回路１の出力振幅が変化した分、前記二重平
衡型乗算回路２の出力振幅も変化し、それが互いに相殺
し合うことになるため、前記２セル構成二重平衡型乗算
回路の出力振幅は入力周波数の変化に対して、広帯域に
一定の出力振幅を得ることが可能となる。また、同様に
前記移相回路を構成する抵抗、容量等の受動素子のばら
つきによって、前記移相回路の出力振幅変化するが、そ
の振幅変化に対しても、一定の出力振幅を得ることが可
能となる。なお、図２は本発明の一実施例の各部におけ
る信号の周波数特性図で、図２（ａ）において、横軸は
移相回路入力周波数ｆ（Ｈｚ）、縦軸は移相回路出力振
幅（ｄＢ）であり、図２（ｂ）において横軸は逓倍器出
力周波数、縦軸は二重平衡型乗算回路出力振幅（ｄＢ）
である。As shown in FIG. 2, the amplitude of the phase shift circuit changes with a change in frequency, and the amplitude of the phase shift circuit follows the change. Since the output amplitude of the multiplication circuit 2 also changes and cancels each other, the output amplitude of the two-cell double-balanced multiplication circuit has a constant output amplitude over a wide band with respect to a change in input frequency. Can be obtained. Similarly, the output amplitude of the phase shift circuit changes due to variations in passive elements such as resistors and capacitors constituting the phase shift circuit, and a constant output amplitude can be obtained with respect to the amplitude change. Becomes Incidentally, FIG. 2 is a frequency characteristic diagram of the signal in each part of an embodiment of the present invention, in FIG. 2 (a), the horizontal axis represents the phase shift circuit input frequency f (H z), the vertical axis represents the phase shift circuit output amplitude In FIG. 2B, the horizontal axis represents the output frequency of the multiplier, and the vertical axis represents the output amplitude (dB) of the double-balanced multiplier.
It is.
【００３２】[0032]
【発明の効果】以上説明したように本発明によれば、二
重平衡型乗算回路を２セル構成にし、二重平衡型乗算回
路１と二重平衡型乗算回路２の入力端子それぞれに、移
相回路からの出力信号をたすき入力することによって、
入力周波数又は構成受動素子のばらつきによって出力振
幅が変化する移相回路の特性を前記二重平衡型乗算回路
１と二重平衡型乗算回路２で互いに相殺し合い、逓倍器
としては、広帯域に一定の出力振幅特性を得ることがで
きるという効果を有する。As described above, according to the present invention, the double-balanced multiplication circuit has a two-cell configuration, and the input terminals of the double-balanced multiplication circuit 1 and the input terminals of the double-balanced multiplication circuit 2 are connected to each other. By crossing the output signal from the phase circuit,
The characteristics of the phase shifter whose output amplitude changes due to the variation of the input frequency or the constituent passive elements cancel each other out with the double balanced multiplier 1 and the double balanced multiplier 2, and as a multiplier, a constant over a wide band. This has the effect that output amplitude characteristics can be obtained.
【図１】本発明の一実施例の広帯域逓倍器回路図。FIG. 1 is a circuit diagram of a wideband multiplier according to an embodiment of the present invention.
【図２】本発明の一実施例の各部における信号の周波数
特性図。FIG. 2 is a frequency characteristic diagram of a signal in each unit according to the embodiment of the present invention.
【図３】移相回路を構成する微分回路、積分回路の利得
と位相特性図。FIG. 3 is a diagram illustrating gain and phase characteristics of a differentiating circuit and an integrating circuit that constitute a phase shift circuit.
【図４】従来の逓倍器回路図。FIG. 4 is a circuit diagram of a conventional multiplier.
【図５】従来の逓倍器の各部における信号の周波数特性
図。FIG. 5 is a frequency characteristic diagram of a signal in each section of a conventional multiplier.
【図６】従来の逓倍器（二重平衡型乗算回路の入力入れ
替え時）の各部における信号の周波数特性図。FIG. 6 is a frequency characteristic diagram of a signal in each section of a conventional multiplier (when the input of a double balanced multiplication circuit is switched).
１ 信号入力端子 ２ 微分回路信号出力端子 ３ 積分回路信号出力端子 ４、１１ 二重平衡型乗算回路、上段信号入力端子 ５、１２ 二重平衡型乗算回路上段基準電圧入力端子 ６、１３ 二重平衡型乗算回路下段信号入力端子 ７、１４ 二重平衡型乗算回路下段基準電圧入力端子 ８ 二重平衡型乗算回路定電流源 ９ 電源電圧端子 １５、１６ 逓倍器出力端子 REFERENCE SIGNS LIST 1 signal input terminal 2 differentiating circuit signal output terminal 3 integrating circuit signal output terminal 4, 11 double balanced type multiplication circuit, upper signal input terminal 5, 12 double balanced type multiplication circuit upper reference voltage input terminal 6, 13 double balanced Signal input terminal at lower stage of type multiplier 7, 14 Double-balanced type multiplier circuit lower reference voltage input terminal 8 Double balanced type multiplier circuit constant current source 9 Power supply voltage terminal 15, 16 Multiplier output terminal
Claims (2)
の信号に９０度の位相差をもたせて出力する移相回路
と、周波数変換器として用いられる二重平衡型乗算回路
を２つ備え、前記移相回路からの２つの出力信号を、前
記二重平衡型乗算回路のそれぞれに、たすき入力するこ
とを特徴とする逓倍器。1. A phase shifter for splitting an input signal into two and outputting each signal with a phase difference of 90 degrees, and two double-balanced multipliers used as frequency converters. , Wherein two output signals from the phase shift circuit are cross-input to each of the double balanced type multiplier circuits.
れる受動素子である容量、抵抗、インダクタで構成し、
一方は微分回路で、もう一方は、積分回路で、それぞれ
の出力の位相差が常に９０度である移相回路を具備した
ことを特徴とする請求項１に記載の逓倍器。2. The phase shift circuit comprises a passive element formed on a semiconductor substrate, a capacitor, a resistor, and an inductor.
2. A multiplier according to claim 1, wherein one is a differentiating circuit, and the other is an integrating circuit, the phase shifting circuit having a phase difference of 90 degrees between respective outputs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23073195A JP2842327B2 (en) | 1995-08-16 | 1995-08-16 | Wideband multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23073195A JP2842327B2 (en) | 1995-08-16 | 1995-08-16 | Wideband multiplier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0955629A JPH0955629A (en) | 1997-02-25 |
| JP2842327B2 true JP2842327B2 (en) | 1999-01-06 |
Family
ID=16912424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23073195A Expired - Fee Related JP2842327B2 (en) | 1995-08-16 | 1995-08-16 | Wideband multiplier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2842327B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3383619B2 (en) | 1999-08-30 | 2003-03-04 | シャープ株式会社 | Phase shifter and demodulator using the same |
| JP3898187B2 (en) * | 2004-01-28 | 2007-03-28 | Ｎｅｃエレクトロニクス株式会社 | Switch circuit for converter for satellite broadcasting |
-
1995
- 1995-08-16 JP JP23073195A patent/JP2842327B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0955629A (en) | 1997-02-25 |
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