JP2840948B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2840948B2
JP2840948B2 JP63207242A JP20724288A JP2840948B2 JP 2840948 B2 JP2840948 B2 JP 2840948B2 JP 63207242 A JP63207242 A JP 63207242A JP 20724288 A JP20724288 A JP 20724288A JP 2840948 B2 JP2840948 B2 JP 2840948B2
Authority
JP
Japan
Prior art keywords
chip
pad
pads
wire
external terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63207242A
Other languages
Japanese (ja)
Other versions
JPH0256942A (en
Inventor
裕紀 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP63207242A priority Critical patent/JP2840948B2/en
Publication of JPH0256942A publication Critical patent/JPH0256942A/en
Application granted granted Critical
Publication of JP2840948B2 publication Critical patent/JP2840948B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H01L2224/49052—Different loop heights
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
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    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/786—Means for supplying the connector to be connected in the bonding apparatus
    • H01L2224/78621—Holding means, e.g. wire clampers
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、ICチップを実装した半導体装置に係り、特
にICチップとICチップ外部に形成した外部端子とを高密
度に接続することができる半導体装置に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device having an IC chip mounted thereon, and more particularly to a high density connection between an IC chip and external terminals formed outside the IC chip. The present invention relates to a semiconductor device.

（従来の技術） ICチップを実装した半導体装置は、ICチップに設けた
パッドとICチップの外部に設けた外部端子とをボンディ
ングワイヤで接続することにより、ICチップの内部の集
積回路に電源や各種信号を供給している。(Prior art) A semiconductor device on which an IC chip is mounted is connected to a pad provided on the IC chip and an external terminal provided outside the IC chip by a bonding wire, so that a power supply or an integrated circuit inside the IC chip can be provided. It supplies various signals.

従来、ICチップに設けられるパッドはICチップの周囲
に一列に形成されていた。ワイヤボンディングに使用す
る金属ワイヤ（Au,Al）は25〜35μｍφであり、ICチッ
プのパッドへの接続は金属ワイヤの先端をボール状に形
成し、これを押し潰すことによって行なうので、パッド
は約100μｍ×100μｍの大きさが必要である。従って、
上記のようにパッドをICチップの周囲に形成する場合、
パッド中心間の距離は約150μｍ程度とすることが必要
であった。Conventionally, pads provided on an IC chip have been formed in a row around the IC chip. The metal wire (Au, Al) used for wire bonding has a diameter of 25 to 35 μm. The connection of the IC chip to the pad is made by forming the tip of the metal wire into a ball shape and crushing it. A size of 100 μm × 100 μm is required. Therefore,
When the pad is formed around the IC chip as described above,
The distance between the pad centers had to be about 150 μm.

そこで、一定の面積のICチップにおいてパッドの高密
度化を図るため、第４図に示すように、ICチップ50にパ
ッド51,パッド52を千鳥状に二列に配列させたものがあ
った。パッド51に対応する外部端子61及びパッド52に対
応する外部端子62をそれぞれICチップ50の外部に設け、
外部端子62より外部端子61をICチップ50の近くに形成し
ていた。そして、先ずパッド51と外部端子61間の一定距
離をカム式のワイヤボンダーに記憶させて、これらの間
をボンディングワイヤ71で接続し、次にパッド52と外部
端子62間をボンディングワイヤ72で接続していた。Therefore, in order to increase the density of pads in an IC chip having a fixed area, there has been an IC chip 50 in which pads 51 and pads 52 are arranged in a staggered two rows on an IC chip 50 as shown in FIG. An external terminal 61 corresponding to the pad 51 and an external terminal 62 corresponding to the pad 52 are provided outside the IC chip 50, respectively.
The external terminals 61 are formed closer to the IC chip 50 than the external terminals 62. First, a fixed distance between the pad 51 and the external terminal 61 is stored in a cam type wire bonder, and these are connected by a bonding wire 71, and then the pad 52 and the external terminal 62 are connected by a bonding wire 72. Was.

（発明が解決しようとする課題） しかしながら、カム式のワイヤボンダーにおいてはボ
ンディングワイヤの接続距離は指定できても、ボンディ
ングワイヤの形状やその高低を制御することができなか
った。ワイヤボンディングを行なう際にボンディングワ
イヤは若干蛇行するので、高低を制御できないことと相
俟って、パッドに接続された相隣合うボンディングワイ
ヤどうしが接触しないためにはそのピッチを約100μｍ
以上離してワイヤボンディングを行なわなければならな
かった。(Problems to be Solved by the Invention) However, in a cam-type wire bonder, the connection distance of the bonding wire can be designated, but the shape and height of the bonding wire cannot be controlled. When performing wire bonding, the bonding wire is slightly meandered, so that the height cannot be controlled, and in order to prevent adjacent bonding wires connected to the pad from coming into contact with each other, the pitch is set to about 100 μm.
The wire bonding had to be performed with the above separation.

従って、ICチップのパッド中心間も約100μｍとなっ
てしまい、一定面積においてこの密度で得られるパッド
数より多い個数のパッドを形成するためには、ICチップ
の外形面積を大型化しなければならないという欠点があ
った。Accordingly, the distance between the centers of the pads of the IC chip is also about 100 μm, and in order to form a larger number of pads than the pad obtained with this density in a certain area, the external area of the IC chip must be increased. There were drawbacks.

本発明は上記実情に鑑みてなされたもので、ICチップ
に高密度のワイヤボンディングを行なうことにより、IC
チップの小型化を図ることができる半導体装置を提供す
ることを目的とする。The present invention has been made in view of the above circumstances, and by performing high-density wire bonding on an IC chip,
It is an object of the present invention to provide a semiconductor device capable of reducing the size of a chip.

（課題を解決するための手段） 上記従来例の課題を解消するため本発明に係る半導体
装置は、ICチップを実装した半導体装置において次の構
成を特徴としている。(Means for Solving the Problems) In order to solve the problems of the conventional example, a semiconductor device according to the present invention is characterized by the following configuration in a semiconductor device on which an IC chip is mounted.

ICチップの周囲及びその内側に複数のパッド列を配設
し、パッド列を構成する各パッドに対応する外部端子を
ICチップの外部に設け、前記パッドと外部端子とをボン
ディングワイヤを介して接続する。A plurality of pad rows are provided around and inside the IC chip, and external terminals corresponding to each pad constituting the pad row are provided.
The pad is provided outside the IC chip, and the pad and the external terminal are connected via a bonding wire.

複数のパッド列における隔列のパッド列において、IC
チップの辺に対して垂直な方向に各パッド列のパッド同
士が一直線に並ぶように配置する。In a pad row separated from a plurality of pad rows, an IC
The pads of each pad row are arranged so as to be aligned in a direction perpendicular to the side of the chip.

前記外部端子は、ICチップの外側位置に設けたパッド
に対応するものほどICチップ近傍位置に形成する。The external terminals are formed closer to the IC chip as the external terminals correspond to the pads provided at positions outside the IC chip.

前記ボンディングワイヤの形状は、デジタルワイヤボ
ンダーを使用することにより、ICチップの内側位置に設
けられたパッドに接続されるものほど順次高く大きなル
ープ状とする。By using a digital wire bonder, the shape of the bonding wire is made larger and larger as it is connected to a pad provided at an inner position of the IC chip.

（作用） 本発明によれば、複数のパッド列における隔列のパッ
ド列について、ICチップの辺に対して垂直な方向に一直
線上に並ぶように各パッドを配置し、パッドと外部端子
とをボンディングワイヤで接続する場合に、デジタルワ
イヤボンダーを使用することによりワイヤの高さ制御が
容易になるので、接続距離が長いボンディングワイヤが
接続距離が短いものより高く大きなループ状に形成する
ことにより、ボンディングワイヤ同士が接触することな
く高密度に架設することができる。(Operation) According to the present invention, the pads are arranged so as to be arranged in a straight line in a direction perpendicular to the side of the IC chip with respect to the pad rows of the plurality of pad rows, and the pads and the external terminals are connected. When connecting with a bonding wire, using a digital wire bonder makes it easier to control the height of the wire, so by forming a bonding wire with a long connection distance in a large loop shape higher than that with a short connection distance, High-density installation is possible without contact between bonding wires.

（実施例） 本発明の一実施例について第１図及び第２図を参照し
ながら説明する。Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

第１図及び第２図は本発明の要部の平面図及び断面図
を示したものである。1 and 2 show a plan view and a sectional view of a main part of the present invention.

絶縁体で形成した基板１上にICチップ２が実装され、
このICチップ２の周囲にパッド３が４列に配設されてい
る。すなわち、ICチップ２の周囲端部に１列目のパッド
3aを各辺に沿って設け（第１パッド列）、このパッド3a
よりICチップ２の中心寄りでパッド3a間に位置するよう
にパッド3bを設け（第２パッド列）、このパッド3bより
さらにICチップ２の中心寄りでパッド3b間に位置するよ
うにパッド3cを設け（第３パッド列）、このパッド3cよ
りさらにICチップ２の中心寄りでパッド3c間に位置する
ようにパッド3dを設けている（第４パッド列）。そし
て、パッド3cとパッド3aは、パッドを高密度に配置する
ために、ICチップの辺に対して垂直な方向に一直線上に
並ぶように配置され、同様にパッド3dとパット3bは、IC
チップの辺に対して垂直な方向に一直線上に並ぶように
配置されている。An IC chip 2 is mounted on a substrate 1 formed of an insulator,
Pads 3 are arranged in four rows around the IC chip 2. That is, the first row of pads
3a is provided along each side (first pad row).
The pads 3b are provided so as to be located between the pads 3a closer to the center of the IC chip 2 (second pad row), and the pads 3c are further located closer to the center of the IC chip 2 and between the pads 3b than the pads 3b. The pad 3d is provided (third pad row) so as to be located between the pads 3c closer to the center of the IC chip 2 than the pad 3c (fourth pad row). The pads 3c and 3a are arranged so as to be arranged in a straight line in a direction perpendicular to the sides of the IC chip in order to arrange the pads with high density. Similarly, the pads 3d and the pads 3b are
The chips are arranged in a straight line in a direction perpendicular to the sides of the chip.

基板１のICチップ２近傍位置には、パッド３と接続さ
れる外部端子４が複数形成されている。パッド3aに対応
する外部端子4aは、ICチップ２の一辺に対してパッド3a
に相向かい合う位置に設けられる（第１外部端子列）。
パッド3bに対応する外部端子4bは、ICチップ２の一辺に
対してパッド3bに相向かい合う位置で前記外部端子4aよ
りICチップ２から離れた位置に設けられている（第２外
部端子列）。同様にしてパッド3c,パッド3dに対応する
外部端子4c（第３外部端子列），外部端子4d（第４外部
端子列）を基板１に設けることにより、外部端子4a間に
外部端子4bが、外部端子4b間に外部端子4cが、外部端子
4c間に外部端子4dが位置するとともに、ICチップ２の辺
側から外部端子4aの列、外部端子4bの列，外部端子4cの
列，外部端子4dの列が形成される。外部端子４はそれぞ
れリード線５に接続されており、このリード線５にICチ
ップ２を駆動するための各種信号が供給されている。A plurality of external terminals 4 connected to the pads 3 are formed near the IC chip 2 on the substrate 1. The external terminal 4a corresponding to the pad 3a is connected to the pad 3a with respect to one side of the IC chip 2.
(First external terminal row).
The external terminal 4b corresponding to the pad 3b is provided at a position facing the pad 3b with respect to one side of the IC chip 2 and at a position farther from the IC chip 2 than the external terminal 4a (second external terminal row). Similarly, by providing the external terminal 4c (third external terminal row) and the external terminal 4d (fourth external terminal row) corresponding to the pads 3c and 3d on the substrate 1, the external terminal 4b is provided between the external terminals 4a. External terminal 4c is connected between external terminals 4b.
The external terminals 4d are located between 4c, and a row of external terminals 4a, a row of external terminals 4b, a row of external terminals 4c, and a row of external terminals 4d are formed from the side of the IC chip 2. The external terminals 4 are respectively connected to lead wires 5, and various signals for driving the IC chip 2 are supplied to the lead wires 5.

パッド３と外部端子４とはボンディングワイヤ６で接
続されている。パッド3aと外部端子4aとを接続するボン
ディングワイヤ6aと、パッド3bと外部端子4bとを接続す
るボンディングワイヤ6bと、パッド3cと外部端子4cとを
接続するボンディングワイヤ6cと、パッド3dと外部端子
4dとを接続するボンディングワイヤ6dとは、それぞれ異
なる形状をなしている。ボンディングワイヤ６で接続す
る距離が長くなるにしたがいボンディングワイヤ６の高
さを高くし、ボンディングワイヤ6d,6c,6b,6aの順に大
きいループ形状とし、ボンディングワイヤ６どうしが接
触しないように形成している。The pad 3 and the external terminal 4 are connected by a bonding wire 6. Bonding wire 6a connecting pad 3a to external terminal 4a, bonding wire 6b connecting pad 3b to external terminal 4b, bonding wire 6c connecting pad 3c to external terminal 4c, pad 3d and external terminal
Each of the bonding wires 6d for connecting to 4d has a different shape. As the distance connected by the bonding wires 6 becomes longer, the height of the bonding wires 6 is increased, and the bonding wires 6d, 6c, 6b, and 6a are formed in a larger loop shape in this order, so that the bonding wires 6 are not in contact with each other. I have.

このようにボンディングワイヤ６の高さ及びその形状
の制御は、ディジタルワイヤボンダーを用いることによ
って実現できる。ディジタルワイヤボンダーは、第３図
にその要部概要を示すように、Auワイヤ11を中央に貫通
させたキャピラリ12と、Auワイヤ11の送り出し量を制御
する第１クランパ13及び第２クランパ14から構成され
る。従来のカム式のワイヤボンダーは、キャピラリの上
下動がAuワイヤの送り出し量に対して一義的に決められ
ていた。これに対してディジタルワイヤボンダーにおい
ては、キャピラリ12の上下動と、第１クランパ及び第２
クランパの閉じるタイミングをそれぞれ独立に可変でき
る。従って、クランパの開閉時間でAuワイヤ11の送り出
し量を決め、キャピラリ12の上下動でワイヤボンディン
グされるAuワイヤ11の高低及びそのループ形状を決める
ことができ、ボンディングワイヤのループ形状をカム式
のワイヤボンダーのように山形ではなく、第２図に示す
ように各ボンディングワイヤの中間部を直線状とするこ
とができ、ワイヤの使用量も少なくできる。As described above, the control of the height and the shape of the bonding wire 6 can be realized by using a digital wire bonder. As shown in FIG. 3, the digital wire bonder includes a capillary 12 having an Au wire 11 penetrated in the center, and a first clamper 13 and a second clamper 14 for controlling the feeding amount of the Au wire 11. Be composed. In the conventional cam-type wire bonder, the vertical movement of the capillary is uniquely determined with respect to the amount of the Au wire to be sent. On the other hand, in the digital wire bonder, the vertical movement of the capillary 12, the first clamper and the second
The closing timing of the clamper can be independently varied. Therefore, the sending amount of the Au wire 11 is determined by the opening / closing time of the clamper, and the height and the loop shape of the Au wire 11 to be wire-bonded by the vertical movement of the capillary 12 can be determined. Instead of a mountain shape like a wire bonder, the intermediate portion of each bonding wire can be made straight as shown in FIG. 2, and the amount of wire used can be reduced.

次に、本実施例の半導体装置の実装方法について説明
する。Next, a mounting method of the semiconductor device of the present embodiment will be described.

複数のリード線５及びその先端部に外部端子４が形成
された基板１上に、複数のパッド３が形成されたICチッ
プ２を固定する。外部端子４及びパッド３はそれぞれ４
列に配設され、ICチップ２の最外側部に設けたパッド3a
と最もICチップ２に近い列に設けた外部端子4a、ICチッ
プ２の外側から２番目の列のパッド3bとICチップ２側か
ら２番目の列の外部端子4b、３列目どうしのパッド3cと
外部端子4c、４列目どうしのパッド3dとの外部端子4dが
それぞれICチップ２の周辺に対して対峙している。An IC chip 2 on which a plurality of pads 3 are formed is fixed on a substrate 1 on which a plurality of lead wires 5 and external terminals 4 are formed at the ends thereof. External terminal 4 and pad 3 are 4
Pads 3a arranged in rows and provided on the outermost portion of IC chip 2
And the external terminals 4a provided in the row closest to the IC chip 2, the pads 3b in the second row from the outside of the IC chip 2, and the external terminals 4b in the second row from the IC chip 2 side, and the pads 3c in the third row The external terminal 4c and the external terminal 4d of the pad 3d in the fourth row face the periphery of the IC chip 2, respectively.

次に、パッド3aと外部端子4aとをディジタルワイヤボ
ンダーで接続する。この接続はパッド3a上にキャピラリ
12を配置させ、Auワイヤ11の先端をボール状に形成した
後、キャピラリ12を下ろしパッド3aにAuワイヤ11の先端
のボール状部を押付けて潰して圧着させることにより行
なう。キャピラリ12を引きあげるとともに水平方向に移
動させ、さらに下降させてループ状に形成（ボンディン
グワイヤ6a）し、外部端子4aに圧着させた後Auワイヤ11
を切断する。このときキャピラリ12の上下動と水平方向
の動きは自由に設定できるので、ボンディングワイヤ６
の高さ及びその形状を制御することができる。Next, the pad 3a and the external terminal 4a are connected by a digital wire bonder. This connection is made by capillary on pad 3a.
12, the tip of the Au wire 11 is formed in a ball shape, the capillary 12 is lowered, and the ball-shaped portion of the tip of the Au wire 11 is pressed against the pad 3a to be crushed and pressed. The capillary 12 is pulled up and moved in the horizontal direction, and further lowered to form a loop (bonding wire 6a), which is crimped to the external terminal 4a, and then the Au wire 11
Disconnect. At this time, the vertical movement and horizontal movement of the capillary 12 can be freely set, so that the bonding wire 6
Height and its shape can be controlled.

次に、パッド3bと外部端子4bとの接続を前記同様ディ
ジタルワイヤボンダーで行なう（ボンディングワイヤ6
b）。ボンディングワイヤ6bはボンディングワイヤ6aよ
り高く、大きなループとなるように形成し、ボンディン
グワイヤどうしが接触しないようにする。以下同様にパ
ッド3cと外部端子4c,パッド3dと外部端子4dを接続し、
ボンディングワイヤ6d,ボンディングワイヤ6c,ボンディ
ングワイヤ6b,ボンディングワイヤ6aの順で高く大きな
ループで形成する。この際に、パッド3cとパッド3a及
び、パッド3dとパッド3bにおいて、ICチップの辺に対し
て垂直な方向に一直線上に並ぶ位置に形成されていて
も、デジタルワイヤボンダーを使用することによりワイ
ヤの高さ制御が容易なので、パッド3d,3c,3b,3aに接続
される順（ICチップの内側位置に設けられたパッドに接
続される順）にボンディングワイヤのループ形状を高く
大きくでき、ボンディングワイヤ同士が接触することを
防止する。Next, the connection between the pad 3b and the external terminal 4b is performed by a digital wire bonder in the same manner as described above (bonding wire 6).
b). The bonding wire 6b is higher than the bonding wire 6a and is formed so as to form a large loop so that the bonding wires do not contact each other. Similarly, connect the pad 3c and the external terminal 4c, and connect the pad 3d and the external terminal 4d,
The bonding wire 6d, the bonding wire 6c, the bonding wire 6b, and the bonding wire 6a are formed in the order of a large and large loop. At this time, even if the pads 3c and 3a and the pads 3d and 3b are formed at positions aligned in a straight line in a direction perpendicular to the sides of the IC chip, the wires can be formed by using a digital wire bonder. The height of the bonding wire can be easily controlled, so that the bonding wire loop shape can be made larger and larger in the order of connection to the pads 3d, 3c, 3b, 3a (in the order of connection to the pads provided inside the IC chip). Prevent wires from contacting each other.

以上のような構成によれば、ボンディングワイヤ6a,6
a間、ボンディングワイヤ6b,6b間、ボンディングワイヤ
6c,6c間、ボンディングワイヤ6d,6d間のピッチを約100
μｍとしながら、基板１に形成されるリード線５のピッ
チを40μｍ程度にすることができる。According to the above configuration, the bonding wires 6a, 6
a, bonding wire 6b, 6b, bonding wire
The pitch between 6c, 6c and the bonding wire 6d, 6d is about 100
The pitch of the lead wires 5 formed on the substrate 1 can be reduced to about 40 μm while the thickness is set to μm.

上記実施例では基板上にリード線及び外部端子を形成
したが、リードフレーム等で形成してもよい。Although the lead wires and the external terminals are formed on the substrate in the above embodiment, they may be formed by a lead frame or the like.

（発明の効果） 本発明によれば、パッドを高密度に配置するために、
複数のパッド列における隔列のパッド列について、ICチ
ップの辺に対して垂直な方向に一直線上に各パッドを並
べた構成とし、パッドと外部端子とをボンディングワイ
ヤで接続する場合に、デジタルワイヤボンダーを使用す
ることによりワイヤの高さ制御が容易になるので、ICチ
ップの内側位置に設けられたパッドに接続されるボンデ
ィングワイヤほど順次高く大きなループ状とすることに
より、ボンディングワイヤ同士が接触することなく高密
度に架設することができる。(Effect of the Invention) According to the present invention, in order to arrange pads at high density,
For a pad row of a plurality of pad rows, each pad is arranged in a straight line in a direction perpendicular to the side of the IC chip, and when connecting pads and external terminals with bonding wires, a digital wire is used. The use of a bonder makes it easier to control the height of the wires, so the bonding wires connected to the pads provided inside the IC chip are made higher and larger in a loop, so that the bonding wires contact each other. It can be installed at high density without the need.

従って、ICチップに高密度にワイヤボンディングする
ことができ、従来例に比較して同一パッド数に対するIC
チップの小型化を図るとともに、ICチップを安価に供給
することができる。Therefore, high-density wire bonding can be performed on the IC chip.
It is possible to reduce the size of the chip and supply the IC chip at low cost.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明実施例の半導体装置の要部平面説明図、
第２図は本発明実施例の半導体装置の要部側面説明図、
第３図は実施例で使用されるディジタルワイヤボンダー
の概要を示す説明図、第４図は従来の半導体装置の実装
を示す説明図である。 １……基板 ２……ICチップ ３……パッド ４……外部端子 ５……リード線 ６……ボンディングワイヤFIG. 1 is an explanatory plan view of a main part of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is an explanatory side view of a main part of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is an explanatory view showing an outline of a digital wire bonder used in the embodiment, and FIG. 4 is an explanatory view showing mounting of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1 ... Board 2 ... IC chip 3 ... Pad 4 ... External terminal 5 ... Lead wire 6 ... Bonding wire

フロントページの続き (56)参考文献 特開 昭59−25238（ＪＰ，Ａ) 特開 昭60−182756（ＪＰ，Ａ) 特開 昭62−150831（ＪＰ，Ａ) 実願 昭61−149415号（実開 昭63− 55538号）の願書に添付した明細書及び 図面の内容を撮影したマイクロフィルム （ＪＰ，Ｕ) 鵜澤高吉著「電子部品の自動組立入 門」初版第１冊（昭56−７−30）日刊工 業新聞社 ｐ．84−87 (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60Continuation of the front page (56) References JP-A-59-25238 (JP, A) JP-A-60-182756 (JP, A) JP-A-62-150831 (JP, A) Practical application No. 61-149415 ( Microfilm (JP, U) Photograph of the contents of the specification and drawings attached to the application form of the Japanese Utility Model Application No. Sho 63-55538, "Introduction to Automatic Assembly of Electronic Components" by Takayoshi Uzawa. 7-30) Nikkan Kogyo Shimbun p. 84-87 (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】ICチップを実装した半導体装置において、 前記ICチップの周囲及びその内側に複数のパッド列を配
設し、パッド列を構成する各パッドに対応する外部端子
をICチップの外部に設け、前記パッドと外部端子とをボ
ンディングワイヤを介して接続する一方、 複数のパッド列における隔列のパッド列について、ICチ
ップの辺に対して垂直な方向に各パッド列のパッド同士
が一直線上に並ぶように配置し、 前記外部端子は、ICチップの外側位置に設けたパッドに
対応するものほどICチップ近傍位置に形成し、 前記ボンディングワイヤの形状は、デジタルワイヤボン
ダーを使用することにより、ICチップの内側位置に設け
られたパッドに接続されるものほど順次高く大きなルー
プ状とした ことを特徴とする半導体装置。1. A semiconductor device having an IC chip mounted thereon, wherein a plurality of pad rows are provided around and inside the IC chip, and external terminals corresponding to each pad constituting the pad row are provided outside the IC chip. And connecting the pads to the external terminals via bonding wires. On the other hand, the pads of each of the plurality of pad rows are aligned in a direction perpendicular to the side of the IC chip. The external terminals are formed closer to the IC chip as the external terminals correspond to the pads provided at positions outside the IC chip, and the shape of the bonding wire is determined by using a digital wire bonder. A semiconductor device characterized in that a device connected to a pad provided at an inner position of an IC chip has a larger and larger loop shape.
JP63207242A 1988-08-23 1988-08-23 Semiconductor device Expired - Lifetime JP2840948B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63207242A JP2840948B2 (en) 1988-08-23 1988-08-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63207242A JP2840948B2 (en) 1988-08-23 1988-08-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0256942A JPH0256942A (en) 1990-02-26
JP2840948B2 true JP2840948B2 (en) 1998-12-24

Family

ID=16536569

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Application Number Title Priority Date Filing Date
JP63207242A Expired - Lifetime JP2840948B2 (en) 1988-08-23 1988-08-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2840948B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770553B2 (en) * 1988-09-26 1995-07-31 日本電気株式会社 Method for manufacturing semiconductor integrated circuit device
JP2506606Y2 (en) * 1990-07-25 1996-08-14 三菱電機株式会社 Wire bonding lead pattern
JPH0823042A (en) * 1994-07-07 1996-01-23 Fujitsu Ltd Semiconductor device, its manufacture and mold used for it
JPH09266223A (en) * 1996-03-28 1997-10-07 Nec Kyushu Ltd Semiconductor device
US5723906A (en) * 1996-06-07 1998-03-03 Hewlett-Packard Company High-density wirebond chip interconnect for multi-chip modules
JPH11284006A (en) * 1998-03-31 1999-10-15 Fujitsu Ltd Semiconductor device
US6476506B1 (en) * 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925238A (en) * 1982-08-03 1984-02-09 Toshiba Corp Semiconductor device
JPS6355538U (en) * 1986-09-29 1988-04-14

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
鵜澤高吉著「電子部品の自動組立入門」初版第１冊（昭５６−７−３０）日刊工業新聞社 ｐ．８４−８７

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