JP2839203B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor integrated circuit using a step-down power supply (V _RC ), and relates to a PM of a V _RC gate circuit receiving an output of a V _CC gate circuit.
The purpose of the present invention is to adjust the threshold value of the OS transistor to prevent delay in signal transmission. One of the logic levels of the binary logic output is determined by the first power supply potential, and the other logic level is determined by the A first logic circuit determined by a second power supply potential having a potential difference A with respect to one power supply potential;
Outputs a value logic, determines one logic level of the binary logic by the first power supply potential, and sets the other logic level to a potential difference B smaller than the potential difference A with respect to the first power supply potential. A second-stage logic circuit that is determined by a third power supply potential of the second-stage logic circuit, wherein the input logic level is determined by the first power supply potential from a logic level determined by the second power supply potential. A PMOS transistor that transitions from an off state to an on state at a predetermined potential while changing to a logic level to determine the other logic level of the output logic, and adjusts the threshold value of the PMOS transistor. The predetermined potential is brought closer to a second power supply potential or a third power supply potential.

A first circuit for outputting an output signal having a high logic at a level substantially equal to a predetermined power supply potential; and a second circuit for receiving the output signal, wherein the first circuit Includes a first PMOS transistor having a source for receiving the predetermined power supply potential and a drain for outputting the output signal, wherein the second circuit includes a gate for receiving the output signal, and a gate connected to the predetermined power supply potential. A second PMOS transistor having a source receiving a lower power supply potential and a drain connected to the output terminal, wherein the first PMOS transistor and the second PMOS transistor each have a threshold voltage; The voltage is defined as a gate-source voltage, and a threshold voltage of the second PMOS transistor is higher than a threshold voltage of the first PMOS transistor. .

[Industrial applications]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit using a step-down power supply (V _RC ). When the density of a semiconductor integrated circuit is increased and miniaturization is advanced, for example, the withstand voltage of a transistor may be impaired. As a countermeasure, a power supply voltage is reduced.

[Prior Art] FIG. 4 is a diagram showing a part of a semiconductor integrated circuit used in combination buck power, preceding CMOS gates as the first circuit (hereinafter, V _CC system gate circuit) 10 for example, + 5V (Hereinafter referred to as V _CC ), and a second circuit C
MOS gate (hereinafter, V _RC system gate circuit) of 11 lower for example + 4V than V _CC is the power supply (hereinafter, V _RC) is given. Note that GND is a common power supply (for example, 0
V).

V _CC system gate circuit 10 is constituted by connecting a PMOS transistor (first PMOS transistor) 13 and the NMOS transistor 14 between V _CC and GND, Also, V _RC system gate circuit 11
Is configured by connecting a PMOS transistor (second PMOS transistor) 15 and an NMOS transistor 16 between _VRC and GND.

The input signal applied to the V _CC system gate circuit 10 has its high logic level at V _CC equivalent potential and its low logic level at GND equivalent potential. NMOS when input signal is high logic
Turn on the transistor 14 to make the output logic equivalent to the GND potential, and when the input signal is low logic, the PMOS transistor 13
To make the output logic equivalent to the V _CC potential. Here, the potential of PMOS transistor 13 is shifted to the ON state from the OFF threshold potential of the CMOS transistor 13 to V _CC (V _TH13)
, And V _TH13 is approximately −0.6V.

On the other hand, the input signal applied to the V _RC system gate circuit 11 (V _CC
Output signal of the system gate circuit 10)
The potential corresponding to V _CC is set, and the low logic level is set to the potential equivalent to GND. When the input signal is high logic, the NMOS transistor 16 is turned on to make the output logic equivalent to the GND potential, and when the input signal is low logic, the PMOS transistor 15 is turned on to make the output logic equivalent to the _VRC potential. Here, the potential of PMOS transistor 15 is shifted to the ON state from the OFF CMOS in V _RC
This is a value to which the threshold voltage (V _TH15 ) of the transistor 15 is added, and V _TH15 is approximately −0.6 V like V _TH13 described above.

Than V _CC to the circuit after including V _RC system gate circuit 11 using the V _RC low voltage, eliminating the breakdown voltage shortage.

[Problems to be solved by the invention]

However, such conventional semiconductor integrated circuit, threshold voltage of the PMOS transistor 15 of the V _RC system gate circuit 11 (V _TH15) is, PMOS transistors of V _CC system gate circuit 10
13 is approximately the same value (−0.6 V) as the threshold voltage (V _TH13 ), the transition of the PMOS transistor 15 from off to on is a potential _obtained by adding V _TH15 to V _RC , that is, +4 V +
It is necessary to wait until the voltage drops below (−0.6 V) = + 3.4 V. For example, when the output waveform of the V _CC gate circuit 10 is
There is a problem that a signal transmission of the _RC gate circuit 11 is delayed.

Further, as shown in FIG. 5, two V _RC circuits 17 and 18
Are connected by a PMOS transistor 19, and this PMOS transistor
19 even when such control on / off output of V _CC system gate circuit 20, as a result of delay in the switching of the PMOS transistor 19, a delay in signal transmission between the two V _RC circuits 17 and 18 generate I do.

The present invention has been made in view of such problems, by adjusting the threshold value of V _RC system gate circuit causing the PMOS transistor receiving an output of V _CC system gate circuit,
The purpose is to prevent delay in signal transmission.

[Means for solving the problem]

According to the present invention, in order to achieve the above object, one of the logic levels of the binary logic output is determined by a first power supply potential and the other logic level is determined by the first logic level as shown in FIG. A first-stage logic circuit determined by a second power supply potential having a potential difference A with respect to the power supply potential of the first stage, receiving a logic from the first-stage logic circuit and outputting binary logic, Is determined by the first power supply potential, and the other logic level is determined by a third power supply potential having a potential difference B smaller than the potential difference A with respect to the first power supply potential. The second-stage logic circuit is configured to switch from an off state at a predetermined potential while the input logic level changes from a logic level determined by the second power supply potential to a logic level determined by the first power supply potential. Oh Transitions to a state having a PMOS transistor which determines the other logic level of the output logic, said PM
The threshold value of the OS transistor is adjusted to bring the predetermined potential closer to the second power supply potential or the third power supply potential.

A first circuit for outputting an output signal having a high logic at a level substantially equal to a predetermined power supply potential; and a second circuit for receiving the output signal, wherein the first circuit Includes a first PMOS transistor having a source for receiving the predetermined power supply potential and a drain for outputting the output signal, wherein the second circuit includes a gate for receiving the output signal, and a gate connected to the predetermined power supply potential. A second PMOS transistor having a source receiving a lower power supply potential and a drain connected to the output terminal, wherein the first PMOS transistor and the second PMOS transistor each have a threshold voltage; The voltage is defined as a gate-source voltage, and a threshold voltage of the second PMOS transistor is higher than a threshold voltage of the first PMOS transistor. .

[Action]

According to the present invention, in the process in which the output of the preceding logic circuit changes from the logic level corresponding to the second power supply potential to the logic level corresponding to the first power supply potential, the potential of the logic level is changed to the third power supply potential. When the potential falls below a predetermined potential determined by the threshold value of the PMOS transistor, the PMOS transistor transitions to the ON state.

Here, the predetermined potential is set close to the second power supply potential or the third power supply potential.

Therefore, the transition of the PMOS transistor is advanced earlier by an amount closer to this, and a delay in signal transmission is prevented.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIGS. 2 to 4 are views showing one embodiment of a semiconductor integrated circuit according to the present invention, which is an example of application to a memory device using a step-down power supply together.

In FIG. 2, a memory cell 20 is connected to transfer gates 24, 2 via bit lines 21, 22 and a word line 23.
5, common bit lines 26 and 27, equalizing transistor 28,
The bit line driving circuits 29 and 30 and the word line driving circuit 31 are connected.

Other active circuit excluding the common bit lines 26 and 27, an external power source (e.g. + 5V, or less, V _CC) is a V _RC system gate circuit which operates by the step-down power supply made from (e.g. + 4V, below V _RC), A voltage applied to a bit line, a word line, and a memory cell is reduced to solve a shortage of withstand voltage due to miniaturization.

Each _VRC gate circuit includes at least one PMOS transistor. That is, the transfer gate 24 includes the PMOS transistors T _1a and T _1b , the transfer gate 25 includes the PMOS transistors T _2a and T _2b , the bit line driving circuit 29 includes the PMOS transistor T ₃ , and the bit line driving circuit 30 includes the PMOS transistor T _3. PMOS transistor T ₄ is, to the word line drive circuit 31 is a PMOS transistor T _5a, T _5b is included respectively. Note that the equalizing transistor 28 is itself a PMOS transistor.

Each PMOS transistor is driven by the output of the gate G ₁ ~G ₇ in diagram illustrating an inverter symbol, these PMOS
The _VRC gate circuit having a transistor functions as a subsequent logic circuit (or a second circuit) described in the gist of the present invention.

Meanwhile, the gate G ₁ ~G ₇ is, V _CC operating at the external power supply V _CC
The output of each gate has a high logic level corresponding to the _VCC potential (second power supply potential) and a low logic level corresponding to the GND potential (first power supply potential). Each gate G ₁ ~G ₇ functions as a pre-stage logic circuit according (or first circuit) to the gist of the present invention.

Here, the gate G ₁ as a representative of the pre-stage logic circuit, when the bit line drive circuit 29 which receives the output of the gate G ₁ representative of downstream logic circuit, the gate G ₁ is binary one logic level of the logic output (Low logic level) to the first power supply potential (GN
D, 0 V), and the other logic level (high logic level) is set to a potential difference A (A = 5) with respect to the first power supply potential.
V) with the second power supply potential (V _CC , + 5V). Also, the bit line drive circuit 29 outputs the binary logic receives the logic of the gate G _1, the binary logic of the one logic level (low logic level) to the first power supply potential (GND, 0V ), And the other logic level (high logic level) is set to the potential difference A with respect to the first power supply potential.
It is determined by a third power supply potential (V _RC , +4 V) having a smaller potential difference B (B = 4 V).

PMOS transistor T ₃ of the bit line drive circuit 29, the gate
While the transition from the off state to the on state at a "predetermined potential", in the present embodiment, the "predetermined potential" second power supply potential between the output of G ₁ is changed from a high logic to a low logic (V
_CC ) or the third power supply potential (V _RC ).

This can be achieved by adjusting the PMOS transistor T ₃ of the threshold (V _TH). For example, the concentration of an impurity implanted into a channel region of the transistor may be adjusted.

Generally, the threshold value of a PMOS transistor is determined by the relationship between the impurity concentration at both the interface portion of the channel region and the portion deeper than the interface. In adjusting the threshold value, it is necessary to consider the impurity concentration in the deep portion, that is, the initial concentration.

For example, in the case of N conductivity type with a high initial concentration,
By implanting a P-type dopant, the threshold can be adjusted in the intended direction.

In the case of a conductive type having a low initial concentration, P
There are two types: implanting impurities of conductivity type, implanting impurities of N conductivity type, or not implanting any. Which one to use is determined by the initial density. Of the above methods, the one whose final concentration at the interface of the channel region is closer to the P conductivity type is adopted.

As described above, when the threshold value of the PMOS transistor was adjusted, as shown in FIG. 3, the output of the _Vcc gate circuit dropped below the "predetermined potential" in the process of changing from high logic to low logic. At this point, the PMOS transistor starts to transition to the ON state.

Such a “predetermined potential” is determined by the threshold values V _TH and V _RC of the PMOS transistor. In this figure, the “predetermined potential” is located at V _RC +0.4 V = + 4.4 V as a result of adjusting V _TH . ing.

This is because the threshold value V _TH of the conventional example is −0.6 V, and the potential corresponding to the “predetermined potential” is V _RC −0.6 V = + 3.4 V, but increases by about 1 V. I have.

Therefore, the transition of the PMOS transistor to the ON state
Can be earlier by time Td corresponding to 1V, it is possible to eliminate the delay of the signal transmission V _RC system gate circuit.

In the above embodiment, CMOS as V _RC system gate circuit
Although the gate is exemplified, the present invention is not limited to this. For example, Bi-CMOS
It may be a gate. The point is that it only needs to have a PMOS transistor that receives the output of the V _CC system gate circuit and operate with a step-down power supply.

〔The invention's effect〕

According to the present invention, V _RC receiving the output of the V _CC system gate circuit
Since the threshold value of the PMOS transistor of the system gate circuit is adjusted, the transition of the transistor to the ON state can be hastened, and a signal transmission delay can be prevented.

[Brief description of the drawings]

1 is a diagram showing the principle of the present invention, FIGS. 2 and 3 are diagrams showing an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a diagram showing the configuration thereof, and FIG. FIG. 4 and FIG. 5 are diagrams showing a conventional example, FIG. 4 is a connection diagram of the V _CC system gate circuit and the V _RC system gate circuit, and FIG. 5 is a configuration using the PMOS transistor as a switching element. FIG. 24, 25: transfer gate (later logic circuit), 28: equalizing transistor (PMOS transistor), 29: bit line drive circuit (later logic circuit), _T1a , _T1b ... PMOS transistor, _T2a , T _2b ...... PMOS transistor, T _3, T ₄ ...... PMOS transistor, T _5a, T _5b ...... PMOS transistor, G ₁ ~G ₇ ...... gate (front logic circuit), 30 ...... bit line driving circuit (downstream logic 31) Word line drive circuit (later logic circuit), V _CC ... second power supply potential, V _RC ... third power supply potential, GND ... first power supply potential.

Claims (2)

(57) [Claims] 1. A logic level of a binary logic output is determined by a first power supply potential, and the other logic level is determined by a second power supply potential having a potential difference A with respect to the first power supply potential. A first-stage logic circuit, receiving a logic from the first-stage logic circuit, outputting binary logic, determining one logic level of the binary logic by the first power supply potential, and setting the other logic level to the second logic level. A subsequent logic circuit determined by a third power supply potential having a potential difference B smaller than the potential difference A with respect to one power supply potential;
Wherein the subsequent logic circuit is turned off at a predetermined potential while the input logic level changes from a logic level determined by the second power supply potential to a logic level determined by the first power supply potential. A PMOS transistor that transitions from a state to an ON state to determine the other logic level of the output logic, and adjusts the threshold value of the PMOS transistor to change the predetermined potential to a second power supply potential or a third power supply potential. A semiconductor integrated circuit characterized by being brought close to a power supply potential of the semiconductor integrated circuit. 2. A semiconductor integrated circuit comprising: a first circuit that outputs an output signal having a high logic level substantially equal to a predetermined power supply potential; and a second circuit that receives the output signal. A first circuit having a source receiving the predetermined power supply potential and a drain outputting the output signal;
A second transistor including a PMOS transistor; a gate receiving the output signal; a source receiving a power supply potential lower than the predetermined power supply potential;
A second PMOS transistor having a drain connected to an output terminal, wherein the first PMOS transistor and the second PMOS transistor each have a threshold voltage, wherein the threshold voltage is defined as a gate-source voltage. And the threshold voltage of the second PMOS transistor is equal to the first PM
A semiconductor integrated circuit characterized by being higher than a threshold voltage of an OS transistor.