JP2836246B2 - Method of manufacturing thin film transistor and multilayer wiring - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor and a multilayer wiring, and more particularly, to forming a channel protection film of a thin film transistor by exposing the insulating layer of the channel protection film when forming the channel protection film by backside exposure. The present invention relates to a thin film transistor that is also formed as an interlayer insulating layer of a wiring and a method of manufacturing a multilayer wiring.

(Prior Art) Conventional thin film transistors and multilayer wirings are used for various electronic devices, and in particular, may be used for image sensors such as facsimile machines and scanners.

A conventional image sensor will be described. In particular, a conventional contact image sensor converts image information of a document or the like one-to-one.
And converts it into an electric signal. in this case,
The projected image is divided into a large number of pixels (light receiving elements), and the charge generated by each light receiving element is temporarily stored in the load capacitance of the multilayer wiring in a specific block unit using a thin film transistor switching element (TFT), and an electrical signal is generated. From several hundred KHz to several MHz
There is a TFT drive type image sensor that sequentially reads out in time series at speeds up to. This TFT-driven image sensor uses a TFT
The above operation enables reading with a single driving IC, thereby reducing the number of driving ICs for driving the image sensor.

For example, as shown in FIG. 3, an equivalent circuit diagram of the TFT drive type image sensor corresponds to a linear light receiving element array 11 having a length substantially equal to the width of a document, and each light receiving element 11 'has a 1: 1 correspondence. A plurality of thin film transistors Ti, j (i = 1 to N, j = 1)
To n) and a multi-layer wiring 13.

The light receiving element array 11 is divided into N blocks of light receiving element groups, and n light receiving elements 11 'forming one light receiving element group include photodiodes PDi, j (i = 1 to N, j = 1
To n). Each light receiving element 1
1 'is each thin film transistor Ti, j (i = 1 to N, j = 1 to n)
, Respectively. The source electrodes of the thin film transistors Ti and j are connected to n common signal lines 14 and load capacitances CLi (i = 1 to n) for each light receiving element group via a multilayer wiring 13 formed in a matrix. , And the common signal line 14 is connected to the driving IC 15.

A gate pulse generating circuit (not shown) is connected to the gate electrode of each thin film transistor Ti, j so as to conduct each block.
Is connected. The photocharge generated in each light receiving element 11 'is equal to the parasitic capacitance CDi, j (i = 1 to N, j = 1 to 1) of the light receiving element for a certain period of time.
After being accumulated in n) and the overlap capacitance between the drain and the gate of the thin film transistor, the thin film transistor Ti, j is sequentially transferred to the line capacitance CLi of the multilayer wiring 13 for each block by using the thin film transistor Ti, j as a charge transfer switch.

That is, the gate pulse φG1 from the gate pulse generation circuit causes the thin film transistors T1,1 to
T1, n is turned on, and the electric charge generated in each light receiving element 11 'of the first block and accumulated in the parasitic capacitance CDi, j or the like is transferred and accumulated in each line capacitance CLi. Then, the potential of each common signal line 14 is changed by the electric charge accumulated in each line capacitance CLi, and this voltage value is converted to the analog switch SWi (i = 1) in the driving IC 15.
To n) are sequentially turned on to extract the output line 16 in time series.

Then, the thin film transistors T2,1 to T2, n of the second to Nth blocks are converted to TN, 1 to TN, n by the gate pulses φG2 to φGn.
Are turned on, the charge on the light receiving element side is transferred for each block, and sequentially read out to obtain an image signal of one line in the main scanning direction of the document, and the document is fed by a document feeding means (not shown) such as a roller. And the above operation is repeated to obtain an image signal of the entire original (see Japanese Patent Application Laid-Open Nos. 63-9358 and 63-67772).

The specific configuration of the thin film transistor and the multilayer wiring 13 of the conventional charge transfer section 12 will be described with reference to FIG.

A conventional thin film transistor includes a chromium (Cr1) layer as a gate electrode 25 and a silicon nitride (SiN) as a gate insulating film 26 on an insulating substrate 21 such as glass or ceramic.
_X1 ) film, hydrogenated amorphous silicon (a-Si: H) layer as a semiconductor active layer 27, silicon nitride (SiN _X2 ) film as a channel protective film 29, and n ⁺ hydrogenated amorphous as an ohmic contact layer 28 Silicon (n ⁺ a-Si: H) layer,
Chromium (Cr2) layer as stir prevention layer 41 part and 42 part,
A polyimide layer 40 as an insulating layer thereon, an aluminum layer as a drain electrode 43 portion and a source electrode 44 portion thereon, and an aluminum layer 30 as an a-Si: H layer light-shielding metal layer were further laminated thereon. This is an inverted staggered transistor.

The drain electrode 43 is connected to the wiring 30a from the transparent electrode of the light receiving element. Here, the ohmic contact layer 28 is formed separately from the portion 28a that contacts the diffusion preventing layer 41 and the portion 28b that contacts the diffusion preventing layer 42. The chromium (Cr2) layers as the diffusion preventing layers 41 and 42 are the same as the ohmic contact layers 28a and 28a.
It is formed so as to cover the layer b.

The configuration of the conventional multilayer wiring 13 has a matrix-shaped multilayer wiring structure, in which a lower wiring 31 is formed of a chromium layer on a substrate 21, an upper wiring 32 is formed of an aluminum layer, and the upper wiring 31 and the lower wiring are formed. Between 32, a first insulating layer 33a made of a silicon nitride (SiN _x 1) film of a gate insulating film 25 in the thin film transistor, and a hydrogenated amorphous silicon (a-Si: H) layer used as the semiconductor active layer 27 in the thin film transistor An interlayer insulating layer 29 ′ (SiN _X 2) used as a channel protective film 29 in a thin film transistor,
In addition, wiring layers are arranged in a matrix through a second insulating layer 33b made of a polyimide layer 40. The connection portions of the upper and lower wirings are connected by contact holes.

Next, a method for manufacturing a conventional thin film transistor and multilayer wiring will be described.

First, a gate electrode 25 of a thin film transistor is formed on a substrate 21.
And the first Cr (Cr1) layer serving as the lower wiring 31 of the multilayer wiring 13 is D
The film is formed by the C sputtering method. Next, this Cr1 is patterned by a photolithography etching step, so that the pattern of the gate electrode 25 of the thin film transistor and the lower wiring of the multilayer wiring 13 are formed.
31 patterns are formed. A gate insulating film 26 of a thin film transistor on a pattern of Cr1 and a semiconductor active layer 27 thereon
To form a channel protective film 29 thereon,
_{SiN X 1, a-Si:} H, the plasma without breaking the vacuum in the order of SiN _X 2
The film is formed by CVD (P-CVD). The insulating layers of the gate insulating film 26 and the channel protective film 29 simultaneously form the first insulating layer 33a and the interlayer insulating layer 29 'in the multilayer wiring 13.

Next, a resist is applied on the gate insulating film 26 in order to form a pattern of the channel protective film 29 in a shape corresponding to the gate electrode 25, and the shape pattern of the gate electrode 25 is masked from behind the substrate 21. Exposure is performed by using, developed, and etched. Thus, a pattern of the channel protective film 29 is formed. However, in this case, the lower wiring is also exposed in the multilayer wiring 13 by backside exposure.
The interlayer insulating layer 29 ′ of the SiN _X layer of the channel protection film 29 is formed on the channel protection film 31.

An n ⁺ type a− layer is formed thereon as an ohmic contact layer 28.
Si: H is deposited by P-CVD. Next, a second Cr (Cr2) layer to be the diffusion prevention layers 41 and 42 of the thin film transistor is deposited by DC magnetron sputtering.

Next, Cr2 of the diffusion prevention layers 41 and 42 of the thin film transistor are patterned by a photolithography process and an etching process,
The patterns of the diffusion prevention layers 41 and 42 are formed. When the thin film transistor portion is etched using a mixed gas of CF ₄ and O _2, a portion without Cr 2 and SiN _x is etched, that is, a
A pattern of -Si: H layer and n ⁺ a-Si: H layer is formed. Thereby, the ohmic contact layer 28 of the thin film transistor
Then, the n ⁺ -type a-Si: H layer and the a-Si: H layer of the semiconductor active layer 27 are etched.

Next, the multilayer wiring 13 is patterned using another photolithographic mask so that the contact hole 34 is formed in the first insulating layer 33a.

Then, a polyimide layer 40 serving as the second insulating layer 33b is applied so as to cover the entire image sensor, prebaked, and a pattern is formed by a photolithography etching process.
Bake again. As a result, a contact portion of each wiring is formed. Thereafter, Descum is performed to completely remove the remaining polyimide in the contact holes 34 and the like.

Next, aluminum (Al) is deposited by DC magnetron sputtering so as to cover the entire image sensor, and is patterned by a photolithographic etching process to obtain a desired pattern. Thereby, the aluminum layer of the drain electrode 43 portion and the source electrode 44 portion of the thin film transistor, a
An aluminum layer 30 as a light-shielding metal layer of the Si: H layer, a wiring 30a part to the drain electrode 43, a wiring 30b part from the source electrode 44 to the multilayer wiring 13, and an upper wiring 32 in the multilayer wiring 13. It is formed.

Finally, a polyimide as a passivation layer (not shown) is applied, prebaked, patterned by a photolithography etching process, and further baked to form a passivation layer. Thereafter, Descum is performed to remove unnecessary polyimide. Thus, a thin film transistor and a multilayer wiring are manufactured.

As described above, as a conventional technique in which an interlayer insulating film is formed in multiple layers in a multilayer wiring portion, JP-A-62-263680, JP-A-59-191353, and JP-A-57-68050 are described. Technology.

(Problems to be Solved by the Invention) However, in the conventional methods of manufacturing a thin film transistor and a multilayer wiring as described above, when the pattern of the channel protective film 29 of the thin film transistor is formed by backside exposure capable of accurately forming a pattern, The back surface exposure is also performed on the multilayer wiring 13, and a pattern substantially similar to the pattern of the lower wiring 31 is also formed on the interlayer insulating film 29 ′ on the lower wiring 31. Therefore, the first wiring is formed on the pattern of the lower wiring 31.
The pattern of the a-Si: H layer and the interlayer insulating layer 29 'is formed in the same manner via the insulating layer 33a of the above, and the upper wiring 32 is formed thereon via the second insulating layer 33b of polyimide. become.

As shown in FIG. 4, the multilayer wiring 13 thus formed has large irregularities in the upper wiring 32 formed on the second insulating layer 33b of the polyimide layer 40. Therefore, there is a problem that the upper wiring 32 is apt to be disconnected.

Further, when patterning the interlayer insulating layer 29 'used for the channel protective film 29, side etching enters the interlayer insulating layer 29' and is formed in a pattern slightly smaller than the pattern width of the lower wiring 31. In such a portion, since the portion between the upper wiring 32 and the lower wiring 31 is close to each other, there is a problem that a short circuit easily occurs therebetween.

The present invention has been made in view of the above circumstances, and in a method of manufacturing a thin film transistor and a multilayer wiring, a thin film transistor capable of preventing disconnection of an upper wiring in a multilayer wiring and preventing a short circuit occurring between the upper wiring and the lower wiring. An object of the present invention is to provide a method for manufacturing a multilayer wiring.

(Means for Solving the Problems) The present invention for solving the problems of the above-mentioned conventional example is to stack a gate electrode, a gate insulating film, a semiconductor active layer and a channel protective film on a substrate, and to form the channel protective film on the substrate. A thin film transistor in which an ohmic contact layer and a diffusion prevention layer are divided and laminated with a source electrode and a drain electrode formed on the divided diffusion prevention layer, respectively, and a lower wiring and an upper wiring are formed in a matrix on the substrate. A method of manufacturing a multi-layer wiring formed in a shape, wherein a first resist is laminated after forming an insulating layer of the channel protective film.
A first resist pattern including: a resist laminating step; and a first exposing step and a first developing step to leave a portion of the first resist in which the channel protective film is used as an interlayer insulating layer in the multilayer wiring. A forming step, a baking step of baking the first resist pattern, and a second step of laminating a second resist on the first resist pattern.
Resist laminating step, and a second step of exposing from the back surface of the substrate.
An exposure step, a third exposure step of exposing only the multilayer wiring portion from the substrate surface, a second development step of developing the second resist to form a second resist pattern, And etching the insulating layer of the protective film by etching the channel protective film using the first resist pattern and the second resist pattern as masks.

(Operation) According to the present invention, before forming the pattern of the channel protective film of the thin film transistor by back surface exposure, the insulating layer of the gate insulating film, the semiconductor active layer, and the interlayer insulating of the channel protective film are formed on the lower wiring in the multilayer wiring. A first resist pattern is formed widely through the layers, and after baking the first resist pattern, a second resist is applied thereon, and the thin film transistor portion and the multilayer wiring portion are exposed on the back surface to form a multilayer wiring. A second resist pattern is formed by exposing only the portion from the surface to the entire surface, developing the second resist, and etching according to the first resist pattern and the second resist pattern to form a pattern of the channel protective film of the thin film transistor. And the method of forming the pattern of the interlayer insulating layer of the multilayer wiring, so that the interlayer insulating layer is formed in the multilayer wiring. It can be formed wider than the width of the lower wiring, so the upper wiring formed on the insulating layer of polyimide can not have large irregularities, and the upper wiring does not have a large step, so the upper wiring is less likely to break off, Also,
Since the interlayer insulating layer is formed widely between the upper wiring and the lower wiring, the upper wiring and the lower wiring do not approach each other, so that a short circuit between the upper wiring and the lower wiring hardly occurs.

(Example) An example of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory sectional view of a thin film transistor portion and a multilayer wiring portion according to the present embodiment. Parts having the same configuration as in FIG. 4 will be described using the same reference numerals.

First, the structure of the thin film transistor is such that chromium (Cr) as a gate electrode 25 is formed on a transparent insulating substrate 21 such as glass.
1) Silicon nitride (SiN _x 1) as layer and gate insulating film 26
Film, a hydrogenated amorphous silicon (a-Si: H) layer as a semiconductor active layer 27, a silicon nitride (SiN _X 2) film as a channel protective film 29, and n as an ohmic contact layer 28
⁺ Hydrogenated amorphous silicon (n ⁺ a-Si: H) layer, chromium (Cr2) layer as diffusion preventing layers 41 and 42, polyimide layer 40 as an insulating layer thereon, and drain electrode 43 thereon Layer and aluminum layer as light shielding metal layer of the a-Si: H layer
30 are sequentially stacked to form an inverted staggered transistor.

The aluminum layer 30 as a light-shielding metal layer is provided to prevent light from penetrating the channel protective film 29 and entering the a-Si: H layer to cause a photoelectric conversion effect. Here, the ohmic contact layer 28 is a diffusion prevention layer 41.
The portion 28a that contacts the layer and the portion 28b that contacts the diffusion prevention layer 42
It is formed separately from the layers. The chromium (Cr2) layer as the diffusion preventing layers 41 and 42 is formed so as to cover the ohmic contact layers 28a and 28b.

The chromium (Cr2) layers of the diffusion prevention layers 41 and 42 prevent damage during deposition of aluminum on the drain electrode 43 and the source electrode 44 by vapor deposition or sputtering, and provide n ⁺ a-Si: H of the ohmic contact layer 28. Plays the role of maintaining the characteristics.

When the thin film transistor is used for an image sensor, the drain electrode 43 is connected to the wiring 30a from the transparent electrode of the light receiving element, and the source electrode 44 is connected to the aluminum wiring 30b to the multilayer wiring 13. Have been.

Similar effects can be obtained by using another material such as poly-Si for the semiconductor active layer 27.

Next, the configuration of the matrix-shaped multilayer wiring 13 will be described.

The multilayer wiring 13 has a matrix-shaped multilayer wiring structure in which a lower wiring 31 is formed on a substrate 21 by chrome (Cr).
1) In the layer, the upper wiring 32 is formed of an aluminum (Al) layer, and the gate insulating film 26 is provided between the upper wiring 31 and the lower wiring 32.
The first insulating layer 33a made of silicon nitride (SiN _X 1) used in the above, and the hydrogenated amorphous silicon (a-Si:
The wiring layers are arranged in a matrix through an H) layer, an interlayer insulating layer 29 '(SiN _X 2) used as a channel protective film 29 in the thin film transistor, and a second insulating layer 33b made of polyimide. The connection portions of the upper and lower wirings are connected by contact holes.

It is also conceivable to arrange an earth line between the signal lines arranged in parallel in the multilayer wiring 13. Thus, occurrence of crosstalk between adjacent wirings can be prevented.

Next, regarding the method of manufacturing the thin film transistor (TFT) and the multilayer wiring of the present embodiment, FIGS.
This will be described using (k).

First, a first Cr (Cr) serving as a lower electrode 31 of the gate electrode 25 and the multilayer wiring 13 is formed on a substrate 21 such as glass that has been inspected and cleaned.
1) is deposited with a thickness of about 750 mm by DC sputtering.
Next, this Cr1 is patterned by a photolithography process and an etching process using a mixed solution of cerium ammonium nitrate, perchloric acid, and water to form a pattern of the gate electrode 25 and a pattern of the lower wiring 31 of the multilayer wiring 13. ,
The resist is stripped (see FIG. 2A).

Thin film transistor gate insulating film 2 on Cr1 pattern
6, a semiconductor active layer 27 thereon, and a channel protective film 29 thereover, to form SiN _X 1 with a thickness of about 3000 mm and a-Si: H with a thickness of about 1000 mm, 2000 _x SiN _x 2
Plasma CVD (P-CV)
D) (see FIG. 2 (b)). By continuously forming a film without breaking the vacuum, contamination of each interface can be prevented, and the S / N ratio can be improved. The insulating layer of the gate insulating film 26 is simultaneously formed with the first
The insulating layer of the channel protective film 29 also forms the interlayer insulating layer 29 'of the multilayer wiring 13 at the same time.

The conditions for forming the insulating layer (SiN _x 1) of the gate insulating film 26 by P-CVD include a substrate temperature of 300 to 400 ° C., a gas pressure of SiH ₄ and NH ₃ of 0.1 to 0.5 Torr, and a flow rate of SiH ₄ gas. Is 10 ~ 50sccm,
NH ₃ gas flow rate is 100 ~ 300sccm, RF power is 50 ~ 200W
It is.

The conditions for forming the a-Si: H film of the semiconductor active layer 27 by P-CVD are as follows: the substrate temperature is 200 to 300 ° C., and the gas pressure of SiH ₄ is 0.1.
In ～0.5Torr, with SiH ₄ gas flow rate 100~300sccm, RF power is 50～200W.

Conditions of forming the insulating layer of the channel protective film 29 (SiN _X 2) in P-CVD is a substrate temperature of 200 to 300 [° C., gas pressure SiH ₄ and NH ₃ is at 0.1～0.5Torr, SiH ₄ gas flow rate Is 10 ~ 50sccm
In the gas flow rate of NH ₃ is at 100～300Sccm, RF power is 50-2
00W.

Next, in order to form a pattern of the channel protective film 29 in a shape corresponding to the gate electrode 25, the multilayer wiring 13 is formed.
The following processing is performed to form a pattern of the interlayer insulating layer 29 '. On the insulating layer (SiN _X 2) of the channel protective film 29 of the thin film transistor and the interlayer insulating layer 29 'of the multilayer wiring 13,
A first positive resist is applied, and a resist pattern (first resist pattern) that widely covers the upper part of the lower wiring 31 in order to form a pattern of the interlayer insulating layer 29 'in the multilayer wiring 13 using a photolithographic mask. Exposure and development are performed so as to satisfy (45) (see FIG. 2 (c)). Then, after post-baking at about 150 ° C. for 15 minutes using the first resist pattern 45, a second positive resist 46 ′ is further applied (see FIG. 2D).

Thereafter, a back surface exposure is performed from the back surface of the substrate 21. Thereafter, only the multilayer wiring 13 is entirely exposed from the surface of the substrate 21 and developed with a developing solution, and the channel is aligned with the gate electrode 25 of the thin film transistor. A second resist pattern 46 is formed to be a resist pattern of the protective film 29. In this case, the second resist pattern 46 is formed on the channel protective film 29 in the thin film transistor, and the first resist pattern 45 is formed on the interlayer insulating layer 29 'in the multilayer wiring 13. (See FIG. 2 (e)).

That is, the first resist pattern formed on the lower wiring 31 when the back surface exposure is performed on the multilayer wiring 13 portion
Since the post-bake 45 is performed, the first resist pattern 45 is hardly exposed to light by the back surface exposure, and thus becomes insoluble in the developing solution. Therefore, even if the exposed portion of the second positive resist 46 'is developed and dissolved,
Is left on the interlayer insulating layer 29 '.

According to the first resist pattern 45 and the second resist pattern 46 thus formed, etching is performed with a mixed solution of HF and NH ₄ F, the resist is stripped off, and the pattern of the channel protective film 29 in the thin film transistor and the multilayer are formed. wiring
The pattern of the interlayer insulating layer 29 'in 13 is formed.

Further, a BHF treatment is performed, and an n ⁺ type a-Si: H is deposited thereon as an ohmic contact layer 28 by P-CVD using a mixed gas of SiH and PH ₃ to a thickness of about 1000 °. Next, the second anti-diffusion layers 41 and 42 of the thin film transistor
A Cr (Cr2) layer is deposited to a thickness of about 1500 ° by DC magnetron sputtering (see FIG. 2 (f)). At this time, alkali cleaning is performed before each deposition.

Next, patterning is performed on Cr2 to be the Cr layers of the diffusion prevention layers 41 and 42 of the thin film transistor by a photolithography process and an etching process using a mixed solution of cerium ammonium nitrate, perchloric acid and water (FIG. 2 (g) )reference). However, the resist 47 on the diffusion prevention layers 41 and 42 is not peeled off and is left.

Then, the thin film transistor part and the multilayer wiring 13 part are
When dry etching using a mixed gas of CF ₄ and O ₂ or wet etching based on hydrofluoric-nitric acid is performed, a portion without Cr and SiN _X 2 is etched, that is, a-Si: H layer and n ⁺ a-Si:
An H-layer pattern is formed (see FIG. 2 (h)).

Thereby, the n ⁺ -type a-Si: H layer of the ohmic contact layer 28 of the thin film transistor and the a-
The Si: H layer is etched. Also, in the multilayer wiring 13 part, the part without Cr2 and SiN _X 2 is etched, and the a-Si: H layer and the n ⁺ a-Si: H layer in the multilayer wiring 13 part are patterned. Then, the resist 47 on the diffusion prevention layers 41 and 42 is peeled off, and a pattern of the diffusion prevention layers 41 and 42 is formed.

Next, to form the entire pattern of the gate insulating film 26 of the thin film transistor on the substrate 21 and the contact hole 34 in the first insulating layer 33a of the multilayer wiring 13,
The iN _X 1 is patterned by a photolithographic etching process using a mixed gas of SF ₆ + C ₂ ClF ₅ (see FIG. 2 (i)).

Then, a polyimide to be the second insulating layer 33b is applied to a thickness of about 1 μm so as to cover the whole, pre-baked at about 160 ° C., a pattern is formed by a photolithographic etching process, and baked again (second Fig. (J)). Accordingly, in the thin film transistor, the contact portion to which the aluminum drain electrode 43 is connected, the contact portion to which the source electrode 44 is connected, and the contact hole in the multilayer wiring 13 for connecting the upper and lower wirings
34 are formed. Thereafter, in order to completely remove the remaining polyimide in the holes 34 and the like, the exposed polyimide is exposed to plasma with O _2.
do scum.

Next, aluminum (Al) is deposited with a thickness of about 1 μm so as to cover the whole by DC magnetron sputtering,
In order to obtain a desired pattern, the resist is removed by patterning in a photolithographic etching process using a phosphoric acid-based solution. Thus, the wiring to the drain electrode 43 portion and the source electrode 44 portion of the thin film transistor, and the wiring to the drain electrode 43
The upper wiring 32 is formed for the part 30a, the part of the wiring 30b from the source electrode 44 to the multilayer wiring 13, and the multilayer wiring 13 (see FIG. 2 (k)).

Finally, a passivation layer (not shown) of polyimide is applied to a thickness of about 3 μm, prebaked, patterned by a photolithography etching process, and further baked to form a passivation layer. Thereafter, Descum is performed to remove unnecessary polyimide.

According to the present embodiment, before the pattern of the channel protective film 29 of the thin film transistor is formed by back surface exposure, the first layer of the gate insulating film 26 on the lower wiring 31 in the multilayer wiring 13 is formed.
A first resist pattern 45 is formed widely via the insulating layer 33a of the semiconductor device, the a-Si: H layer of the semiconductor active layer 27, and the interlayer insulating layer 29 'of the channel protective film 29.
After baking 45, a second resist 46 'is applied thereon, and the thin film transistor portion and the multilayer wiring 13 are exposed on the back surface, and only the multilayer wiring portion is exposed on the entire surface from the front surface. Develop the second resist pattern
This is a manufacturing method in which a pattern 46 is formed and etched according to the first resist pattern 45 and the second resist pattern 46 to form a pattern of the channel protective film 29 of the thin film transistor and a pattern of the interlayer insulating film 29 ′ of the multilayer wiring 13. ,
In the multilayer wiring 13, the interlayer insulating layer 29 ′ can be formed wider than the width of the lower wiring 31, so that the upper wiring 32 formed on the polyimide layer 40 does not have large irregularities, and the shape of the upper wiring 32 has a large step. Therefore, disconnection of the upper wiring 32 is less likely to occur, and since the interlayer insulating layer 29 'is formed widely between the upper wiring 32 and the lower wiring 31, the space between the upper wiring 32 and the lower wiring 31 is not formed. Without approaching,
As a result, a short circuit between the upper and lower wiring is less likely to occur,
There is an effect that a highly reliable semiconductor device can be provided.

In this embodiment, after the first resist pattern 45 is formed and the second positive resist 46 'is applied, the entire substrate 21 is first exposed to the back, and then only the multilayer wiring 13 is exposed to the entire surface. However, the backside exposure of the entire substrate 21 and the entire surface exposure of only the multilayer wiring 13 portion may be simultaneously performed, or the multilayer wiring 13 portion alone is exposed first, and then the entire substrate 21 is exposed. The same effect can be obtained by exposing the back surface.

(Effects of the Invention) According to the present invention, before forming a pattern of a channel protective film of a thin film transistor by back surface exposure, an insulating layer of a gate insulating film, a semiconductor active layer, and a channel protective film are formed on a lower wiring in a multilayer wiring. Forming a first resist pattern widely through the interlayer insulating layer, baking the first resist pattern, applying a second resist thereon, and exposing the thin film transistor portion and the multilayer wiring portion to the back surface, Exposing the entire surface of only the multilayer wiring portion, developing the second resist, forming a second resist pattern, and etching according to the first resist pattern and the second resist pattern, thereby forming a channel protective film of the thin film transistor. Since the manufacturing method is to form the pattern of the multilayer wiring and the pattern of the interlayer insulating layer of the multilayer wiring, The edge layer can be formed wider than the width of the lower wiring, so that the upper wiring formed on the polyimide insulating layer cannot have large irregularities, and the upper wiring does not have a large step, so the upper wiring has a step break. Less likely to occur,
Since the interlayer insulating layer is formed widely between the upper wiring and the lower wiring, the upper wiring and the lower wiring do not come close to each other, so that a short circuit between the upper wiring and the lower wiring does not easily occur and the reliability is improved. There is an effect that a semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory sectional view of a thin film transistor part and a part of a multilayer wiring according to one embodiment of the present invention, and FIGS.
(K) is a cross-sectional explanatory view for explaining a manufacturing process of a thin film transistor portion and a multilayer wiring portion, FIG. 3 is an equivalent circuit diagram of a conventional image sensor, and FIG. FIG. 11 ... Light receiving element array 12 ... Charge transfer unit 13 ... Multilayer wiring 14 ... Common signal line 15 ... Drive IC 16 ... Output line 21 ... Substrate 25 ... Gate electrode 26 ... Gate insulating film 27 ... Semiconductor active layer 28 ... Ohmic contact layer 29 ... Channel protective film 29 '... Interlayer insulating layer 30 ... Aluminum layer 31 ... Lower wiring 32 ... Upper wiring 33 ... Insulating layer 34 ... Contact hole 40 ... Polyimide layers 41, 42 ... Diffusion prevention layer 43 ... Drain electrode 44 ... Source electrode 45 ... First resist pattern 46 ... Second resist pattern 47 ... Resist on diffusion prevention layer

Claims (1)

(57) [Claims] 1. A gate electrode, a gate insulating film, a semiconductor active layer, and a channel protective film are laminated on a substrate, and an ohmic contact layer is divided and laminated with a diffusion prevention layer sandwiching the channel protective film. A method of manufacturing a thin film transistor in which a source electrode and a drain electrode are respectively formed on a diffusion prevention layer and a multilayer wiring in which a lower wiring and an upper wiring are formed in a matrix on the substrate. A first resist laminating step of laminating a first resist after depositing a layer, and a first exposure to leave a portion of the first resist in which the channel protective film is used as an interlayer insulating layer in the multilayer wiring. A first resist pattern forming step having a step and a first developing step; a baking step of baking the first resist pattern; A second resist laminating step of laminating a second resist on the resist pattern, a second exposing step of exposing from the back surface of the substrate, and a third exposing step of exposing only the multilayer wiring portion from the substrate surface.
An exposure step, a second development step of developing the second resist to form a second resist pattern, and forming an insulating layer of the channel protective film on the first resist pattern and the second resist pattern. A step of etching an insulating layer of a channel protective film for etching and removing the film using the mask as a mask.