JP2830480B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a complementary MOS field effect transistor (hereinafter referred to as CMOS), and more particularly to a circuit of a semiconductor device in which switching noise generated due to switching of an output signal is reduced. Regarding the configuration.

[0002]

2. Description of the Related Art A conventional CMOS IC output circuit is shown in FIG.
As shown in the figure, P-channel MOS transistors P and N
A channel MOS transistor N is connected in series between the higher power supply and ground.

A resistor R ₁ is connected in series to the input, and a capacitor C ₁ is connected between the gate and the ground.

[0004] Now, when the load capacitance C _L is connected to the output circuit, the time t for charging and discharging the capacitor C _L is,

[0005]

[0006]

At this time, noise is generated due to a sudden current change. The magnitude N of this noise is determined by the time derivative of the current,

[0008]

## EQU1 ##

This noise is considered as a cause of recent EMI.

In a conventional CMOS IC, in order to reduce this noise, a resistor R ₁ and a capacitor C ₁ are provided on the input side of the output circuit.
Is provided to smooth the waveform of the input signal so as to reduce the time differential represented by the equation (2).

[0012]

However, the countermeasures against noise by the above-mentioned method have a disadvantage that the equivalent switching time becomes longer because the output pulse waveform is blunted.

This is a serious problem in that each terminal needs to be switched at a high speed with the high-speed operation of the IC.

[0014]

Means for Solving the Problems Now, in an output circuit,
Assuming that the charging / discharging current for the load capacitance C _L is a constant current, and assuming that the high-level potential of the output signal has been lowered to the TTL level (１ ／ of the conventional high level),
When a charge / discharge current for obtaining the same charge / discharge time as the charge / discharge time t expressed by the equation (1) is obtained,

[0015]

Therefore, it can be seen that a half of the charge / discharge current in the conventional output circuit is sufficient.

A semiconductor device according to the present invention is based on the above-described principle, and uses a first signal of an active low in a control system.
An active-high second signal in the control system;
And a third signal different from the second signal.
In semiconductor devices that output via various output terminals,
A first output circuit having a CMOS configuration for outputting the first signal;
And outputting the second signal and the third signal.
And a second output circuit having a CMOS configuration
The high level of the first output circuit is equal to the power supply potential.
Output a signal whose low level is equal to the ground potential,
The second output circuit has a high level lower than the power supply potential.
A signal having a low level equal to the ground potential is output .

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a preferred embodiment of the present invention.

FIG. 1 is a circuit diagram showing a circuit configuration of a first embodiment of the present invention.

In this embodiment, as shown in FIG.
And an output level generating voltage source 2.

The output point N ₂ of the output level generating voltage source ₂ is
Source follower transistors with multiple output pins (Fig. 1
In the middle, a potential is applied to the gate of an N-channel MOS transistor M ₄ of the first output circuit 3 (described later).

The output section 1 includes a first output circuit 3 and a second output circuit 4 provided separately from the first output circuit 3.

The first output circuit 3 includes three MOS transistors N N connected in cascade between a higher power supply and ground.
Channel MOS transistor M ₄ , P channel MO
And S transistors M ₅ and N-channel MOS transistor M _6, comprising an output terminal 5 from the P-channel MOS transistor M ₉ Metropolitan to pull up.

The output of the output level generating voltage source 2 is input to the gate of the N-channel MOS transistor M ₄ . The gate of the P-channel MOS transistor M ₅ and N-channel MOS transistor M ₆ is connected to a common, where the signal from the preceding circuit (not shown) is input to.

The N-channel MOS transistor M ₄
The potential of the connection point N ₃ between the source and the source of P-channel MOS transistors M ₅ of is controlled by an output level generation voltage source 2 as will be described later, in the present embodiment is set to TTL levels.

On the other hand, the second output circuit 4 has a structure in which a P-channel MOS transistor M ₇ and an N-channel MOS transistor M ₈ are vertically connected between a high-potential power supply and the ground, and includes two MOS transistors. , A signal from a preceding circuit (not shown) is input to a common gate, and an output signal is output to a common drain.

Here, consider the case where the semiconductor device of the present embodiment having the above configuration is applied to, for example, a microcomputer.

Normally, signals used by the microcomputer include signals for handling data on the address buses ABφ to ABn and data buses DBφ to DBn, and control signals for read strobe, write strobe, chip enable, and the like.

Among them, in a signal system mainly dealing with data,
Although the time ratio between "1" and "0" cannot be specified, the control signal includes "1" such as read strobe, write strobe, chip enable, and the like.
There are things that are longer to maintain.

Of course, the control signal includes "0"
Some signals have a longer time to maintain.

In a logic circuit using CMOS, if "1" is a power supply potential and "0" is a ground potential,
Since a through current does not flow through the input gate receiving this signal and power consumption can be reduced, it is convenient that the control signal having a long time of maintaining "1" as described above is a normal CMOS level. .

Since the frequency of the level change of these signals is not so intense as that of the signal of the data system, it does not pose a serious problem as a noise source in practical use.

On the other hand, a signal system for handling data frequently changes between "1" and "0", and therefore becomes a noise source.

In this embodiment, for these signals,
By lowering the high-level potential of the signals based on the above-described principle, the intensity of noise generated by these signals can be reduced .

That is, according to this embodiment, the data signal is mainly input to the first output circuit 3 whose output high level is TTL level, while the time when the control signal is "1" is longer. By inputting a signal that is longer than “0” to the second output circuit 4, noise due to switching of the output signal can be reduced.

[0036] Note that in FIG. 1, P-channel MOS transistor M ₉ connected to the output terminal 5 of the first output circuit 3 is a pull-up, such as when the special state standby state and does not output the power level And other ICs consume power, and are provided to prevent this. The P when channel MOS transistor M ₉ is turned on, N-channel MOS transistor M ₆ is required to have off.

In FIG. 1, an N-channel MO
The S transistor M ₄ and P-channel MOS transistors M _5, may be connected to the position interchanged.

Next, the output level generating voltage source 2 will be described.

As shown in FIG. 1, the output level generating voltage source 2 of this embodiment includes a reference voltage source section 6 and a voltage follower section 7.

The reference voltage source unit 6 is composed of a high-potential power supply and the resistor R ₂ and the N-channel MOS transistor M ₁ connected in series between a ground resistor R ₃ Prefecture. N channel MO
The gate and drain of the S transistor M ₁ are connected, and this connection point is the output point N ₁ of the reference voltage source 6.

The voltage follower unit 7 includes an operational amplifier (referred to hereinafter as op-amp) 8, made of a constant current source 9, N-channel MOS transistor M ₂ and P-channel MOS transistor M ₃ Prefecture.

N-channel MOS transistors M ₂ and P
The channel MOS transistor M ₃ is an N channel M
The drain of the OS transistor M ₂ is connected to the high-potential power supply, a grounded drain of P-channel MOS transistor M ₃ is also the gate and source form a non-inverting amplifier circuit are commonly connected. And these two MOS
The output of the operational amplifier 8 is input to the common gate of the transistors, and the common source is the output point N _{2 of the} output level generating voltage source 2.

The output point N ₂ of the voltage follower 7
, As described above, it is connected to the gate of N-channel MOS transistor M ₄ of the plurality of first output circuit 3.

[0044] The constant current source 9 provided in parallel with the P-channel MOS transistor M ₃ between the output point N ₂ and ground, P-channel MOS transistor M ₃ when high-potential power supply voltage V _D becomes lower Are intended to help the operation slow down due to the substrate bias effect.

In this voltage follower unit 2, the output point N of the reference voltage source unit 6 in the preceding stage is connected to the plus input of the operational amplifier 8.
Output from the ₁ is input, and an output from the output point N ₂ of the voltage follower unit 2 is input to the negative input of the operational amplifier 8.

The output level generating voltage source 2 configured as described above operates as follows.

First, the reference potential V _R is generated by dividing the high-order power supply V _D by the resistance in the reference voltage source section 6. The N-channel MOS transistor M ₁ having a gate and a drain connected is provided to compensate for a potential drop generated by the N-channel MOS transistor M ₄ of the first output circuit 3.

Now, the high-level potential V _d of the output signal,
That is, the drain potential of the N-channel MOS transistor M ₄ of the first output circuit 3, the output level generation voltage source 2
If the output point N ₂ potential V _O, the threshold voltage of the N-channel MOS transistors M ₄ and V _TM4, a _{V d = V O -V TM4 (} 3).

Here, an operational amplifier 8, an N-channel MO
Since S transistor M ₂ and P-channel MOS transistor M ₃ are forming a voltage follower is equal to the potential of the negative input of the plus input of Opeanfu 8. _{That, V R = V O (4} ) In addition, the current flowing through the N channel MOS transistor M ₁ of the reference voltage source unit 6 and i, when the threshold voltage of the MOS transistor and V _TM1, V _R = _{R 2} I = V _TM1 (5), where V _D is the higher power supply voltage, i = (V _D −V _TM1 ) / (R ₂ + R ₃ ) (6) (3) , (6), V _d = {R ₃ / (R ₂ + R ₃ )}｝ (V _D −V _TM1 ) + V _TM1 −V _TM4 (7) Here, V _TM1 and V _TM4 are the same. N channel MO
Since they are threshold voltages of the S transistor, they are almost equal.
Therefore, equation (7) is given by: V _d = {R ₃ / (R ₂ + R ₃ )} · (V _D −V _TM1 ) (8) Here, according to equation (8), the high level of the output signal in this embodiment is obtained. try to determine the level variation of the level V _d.

In the equation (8), the resistances R ₂ and R
Since _3, but are the ratio does not change the resistance value itself varies with variations in the manufacturing process, R ₃ / (R ₂
+ R ₃ ) is always constant.

The higher power supply voltage V _D is a system power supply, and is guaranteed at 5V ± 5% or 5V ± 10%.

The threshold voltage V _TM1 of the N-channel MOS transistor M ₁ changes by about 0.7 V ± 30% because it is sensitive to temperature and is affected by fluctuations in the manufacturing process. ± 4%.

[0053] Therefore, a ± 9 to 14% to match the variation of the high-potential power supply voltage V _D threshold V _TM1 of change and N-channel MOS transistor M ₁ of the.

Here, since the high level of the output signal is the TTL level, V _d ≒ V _D / 2, that is, R ₂ = R ₃ . Therefore, the above fluctuation is halved to be ± 4.5 to 7%.

Since the high-level standard of the TTL output is 2.4 V or higher, the output voltage can be maintained at 2.6 V ± 7% according to the output level generating voltage source 2 of the present embodiment, which is sufficient. Accuracy can be obtained.

The output level generating voltage source 2 of the present embodiment may be the simplest circuit as far as possible to minimize the influence of a MOS transistor having a large temperature change.

The output point N of the voltage follower unit 2
₂ and the constant current source has entered between the ground 9 is of the order to reduce the substrate bias effect on P-channel MOS transistor M _3, as described above, the output as in this embodiment is V _d If / 2 is not near at greatly changed may be only one of the constant current source 9 or P-channel MOS transistor M _3.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing a circuit configuration of a second embodiment of the present invention. This embodiment differs from the first embodiment shown in FIG. 1 in that a constant voltage source 10 is provided and that the output level is adjusted by an operational amplifier 8 for each output unit 1.

In this embodiment, the output of the constant voltage source 10 is connected to the plus input of the operational amplifier 8. The constant voltage source 10 is also used as a constant voltage source for another output level generating voltage source 2.

The operational amplifier 8 has an N-channel MO output.
It is connected to the gate of the S transistor M _10.

The N-channel MOS transistor M ₁₀ is
The drain is connected to the higher power supply and the source is a constant current source 9
And is also connected to the minus input of the operational amplifier 8 to form a voltage follower.

Therefore, N-channel MOS transistor M
_{The 10} sources are the output of this voltage follower.

[0064] Then, source and output of the aforementioned voltage follower P-channel MOS transistors M ₅ constituting the output buffer, that is connecting the source of N-channel MOS transistor M _10, the P-channel M
A common drain of the OS transistor M ₁₀ and the N-channel MOS transistor M ₅ is the output point.

In the present embodiment, in the first embodiment, the reference voltage is received by the voltage follower, and this level is additionally supplied by the source follower. On the other hand, the voltage follower is connected to each output pin. Although there is a difference in the connection point, the circuit operation is the same as that of the first embodiment, and the same effect is obtained.

Although various combinations are conceivable for the combination of the reference voltage source, the voltage follower, and the output unit described above, any combination can provide the same effect as that of the embodiment. .

[0067]

As described above, according to the present invention, an output signal of a semiconductor device is divided into an active high control signal system, a data signal system that frequently changes levels, and an active low control signal system. The former high level of the signal system is greatly reduced from the power supply potential to halve the load driving current.

Therefore, the noise generated when these output signals are switched becomes very small.

On the other hand, since the active-low control signal system always outputs a high level, in order to prevent a through current from flowing through the input gate receiving the active-low control signal system, only the high level of this active-low signal system is supplied to the power supply. It has the potential <br/>.

At this time, unlike the other data signal systems, the level of the active low control signal system does not change frequently, so that the switching noise level generated by this circuit is small and poses no problem.

As described above, according to the present invention, it is possible to provide a semiconductor device which operates at a high speed despite the fact that noise due to switching of an output signal is very small as compared with a conventional semiconductor device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional CMOS IC output circuit.

[Explanation of symbols]

 Reference Signs List 1 output section 2 output level generating voltage source 3 first output circuit 4 second output circuit 5 output terminal 6 reference voltage source section 7 voltage follower section 8 operational amplifier 9 constant current source 10 constant voltage source

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 17/16 H03K 17/687 H03K 19/003 H03K 19/0175

Claims (3)

(57) [Claims] An active-low first signal in a control system.
An active-high second signal in the control system;
And a third signal different from the second signal.
In a semiconductor device which outputs via respective output terminals, a first output circuit of a CMOS configuration for outputting the first signal is provided.
A path and a signal for outputting the second signal and the third signal
A second output circuit having a CMOS configuration provided for each
For example, the first output circuit, a high level is equal to the power supply potential
A signal whose low level is equal to the ground potential is output, and the second output circuit outputs a signal whose high level is higher than the power supply potential.
A semiconductor device which outputs a signal whose low level is equal to the ground potential . (2) The semiconductor device according to claim 1, The third signal has a signal level switching frequency equal to the first signal.
Signal and a signal larger than the second signal.
Characteristic semiconductor device. (3) The semiconductor device according to claim 1.
At The second output circuit outputs an output signal according to a source potential.
P-channel MOS field-effect transistor driven to
Output signal to low level by transistor and source potential
Driving n-channel MOS field-effect transistor
And the potential obtained by stepping down the power supply voltage.
Source potential of the MOS field-effect transistor
Means for forcing to a potential lower than The p-channel MOS field-effect transistor itself
Beforehand, the high level of the output signal is
A semiconductor device characterized by the following: