JP2827579B2 - Semiconductor memory cell and method of forming the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell, and more particularly to a one-transistor / one-capacitor semiconductor memory cell and a method of forming the same.

[0002]

2. Description of the Related Art MOS dynamic memories are available in 1970.
1kbit dynamic random access of the year
With the launch of memory as a starting point, the scale has been increased by a factor of four in three years, and the memory cell area has been reduced to 0.3 per generation.
It has been reduced to 0.4 times. In order not to reduce the soft error resistance even if the memory cell is reduced, securing the cell capacity is an important issue.

One of the solutions to this problem is 1989
Symposium on VSI Technology Digest of Technical Papers (198
9SYMPOSIUM ON VLSI TECHNO
LOGY DIGESTOF TECHNICAL P
APERS), page 69.

In this method, a hollow, columnar conductive member 8 is formed as a storage electrode on one source / drain region 5-1 of a MOS transistor formed on a P-type silicon substrate 1 as shown in FIG. And not only its outer walls,
By using the inner wall as a capacitor, a large capacity is to be secured while suppressing an increase in cell area.

[0005]

The conductive member 8 is formed by depositing a conductive film on an insulating film existing around the conductive member 8 and etching it back. Therefore, as shown in FIG. 8, the upper end of the conductive member 8 is sharp and pointed. For this reason, electric field concentration occurs in this portion, and the withstand voltage of the insulating film forming the capacitance is reduced,
This causes a decrease in the reliability of the memory cell.

An object of the present invention is to form a highly reliable storage electrode by flattening the upper end surface of such a hollow and columnar storage electrode, thereby eliminating electric field concentration on this portion. It is an object of the present invention to provide a semiconductor memory cell and a method for forming the same.

[0007]

Means for Solving the Problems] The semiconductor memory cell of the present invention, and one MOS transistor, said MOS capacitor unit to one of the source and drain regions of the transistor is connected, the bit line to the other of the source and drain regions In the connected semiconductor memory cells, the silicon oxide film
The lower interlayer insulating film formed by laminating a silicon nitride film
Covers the OS transistor and penetrates the lower interlayer insulating film
Through the opening to the one source / drain region
The capacitor section connected is subjected to the gate electrode of the MOS transistor from one of the source and drain regions on the
And the one source is provided through the lower interlayer insulating film.
Hollow columnar connected to the drain region and, with its upper end face is flat conductive member, a dielectric film formed on the entire surface of the conductive member, opposite which is formed over the entire surface of the dielectric film and an electrode, the upper layer of the lower interlayer insulating film and the capacitor portion
The bit line is covered with an interlayer insulating film.
Selectively covering the film, the upper interlayer insulating film and the lower layer
The other source through a contact hole penetrating the inter-insulation film.
Connected to the source / drain region.
You.

The method of forming a semiconductor memory cell according to the present invention comprises:
Forming a MOS transistor on a semiconductor substrate, acid
Lower layer consisting of silicon nitride film laminated on silicon nitride film
The MOS transistor is covered with an insulating film,
One source source of the MOS transistor is connected to the interlayer insulating film.
Forming an opening reaching the rain region; and
A step of applying a conductive film that is connected to one of the source / drain regions of the MOS transistor through a portion to cover the lower interlayer insulating film, and that a resist film is used as a mask.
By etching, among the conductive film, thin the conductive film in a portion except for the one of the source and drain regions above, and forming the projections on the conductive film, the resist
The film is removed, and a silicon oxide film is deposited on the entire surface.
Etch back the recon film to selectively select the side walls of the protrusion.
Forming an etching-resistant member made of the silicon oxide film to cover , and thereafter, etching the conductor film,
The conductive film of the outer portions of the etch resistant member stops etching at the time of the complete removal of the lower side of the resistant etched member, columnar hollow, and its upper surface is flat, further the bottom forming a conductive member connected to said one of the source and drain of the etching-resistant member
Selectively removing, forming a dielectric film on the conductive member surface, an opposing electrode is formed on the conductive film
Forming a capacitor portion, and the lower interlayer insulating film and
Forming an upper interlayer insulating film covering the capacitor portion;
The MOS transistor penetrates an insulating film and the lower interlayer insulating film.
Contour reaching the other source / drain region of the transistor
A contact hole, and the other source through the contact hole.
Forming a bit line connected to a drain region
It is comprised including.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of a memory cell according to the present invention. This memory cell has a MOS transistor and a capacitor. The MOS transistor includes an N-type source / drain region 5 formed on a P-type silicon substrate 1.
-1, 5-2 and a gate electrode 4 laminated with a gate oxide film 3 interposed therebetween . This MOS transistor
Is nitrided on the first interlayer insulating film 6 made of a silicon oxide film.
Lower layer formed by laminating a second interlayer insulating film made of silicon film
It is covered with an interlayer insulating film. Capacitance part is between lower layers
From above the N-type source / drain region 5-1 via the insulating film
It is provided over the gate electrode 4 and further has a lower interlayer insulation.
The N-type source / drain is opened through an opening provided in the edge film.
In region 5-1. Capacitance part and second layer
The insulating film 7 is a third interlayer insulating film 11 which is an upper interlayer insulating film.
Coated with Third interlayer insulating film 11, second interlayer
Via a contact hole 12 formed through the insulating film 7 and the first interlayer insulating film 6, a bit line 13 and the N-type source and drain regions 5-2 is connected.

The capacitance portion is an N-type source / drain region 5-1.
The storage electrode and the cell plate 10 (opposite electrode) are formed of a conductive member 8 having a columnar shape, a hollow shape (in other words, a ring shape), and a flat upper end surface. And a film 9 (dielectric film). The cell plate 10 and the bit line 13 are separated by a third interlayer insulating film 11, and element isolation is performed by a silicon oxide film 2 formed on a silicon substrate 1.

FIGS. 2 to 7 are sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of a method for forming a memory cell according to the present invention.

First, as shown in FIG.
A mask oxide film (not shown) of about 40 nm is formed on the P-type silicon substrate 1 by thermal oxidation, and a silicon nitride film (not shown) is deposited to a thickness of about 120 nm by a CVD method. After that, patterning is performed so that a mask oxide film and a silicon nitride film remain on a predetermined region, and then a silicon oxide film 2 having a thickness of 600 nm is formed by thermal oxidation to partition an element region. Then, the silicon nitride film and the mask oxide film are removed by wet etching.

Next, a gate oxide film 3 having a thickness of 20 nm is formed in the element region by oxidation in an oxidizing atmosphere at 950.degree. CVD
The polycrystalline silicon film is deposited to a thickness of 500 nm by the method,
The gate electrode 4 is formed by a normal photolithography technique and a dry etching technique.

Next, as shown in FIG. 3, arsenic is implanted at an acceleration energy of 100 keV and a dose of 5 × 10 ¹⁵ / cm ² to form N-type source / drain regions 5-1 and 5-2. Next, other portions are removed by wet etching except for the gate oxide film 3 immediately below the gate electrode 4. Then CV
A silicon oxide film is deposited by the method D, and this is used as a first interlayer insulating film 6. Subsequently, a silicon nitride film is deposited by a CVD method, and this is used as a second interlayer insulating film 7.

Next, as shown in FIG. 4, a part of the first interlayer insulating film 6 and a part of the second interlayer insulating film 7 on the N-type source / drain region 5-1 are formed by ordinary photolithography and dry etching. Etching using N-type source
An opening reaching the drain region 5-1 is formed. CVD
After the polycrystalline silicon film 16 is deposited by the method and the phosphorus is thermally diffused, the resist film 14 is patterned by using a normal photolithography technique, and then, by using a dry etching technique, a portion without the resist film 14 is formed. The polycrystalline silicon film 16 is etched and thinned to form a projection on the polycrystalline silicon film 16 as shown in FIG. Next, the resist film 14 is removed, and CVD is performed on the entire surface.
After depositing a silicon oxide film by the method, an etch back is performed, and only the side wall of the convex portion of the polycrystalline silicon film 16 is formed.
A silicon oxide film 15 (which is an etching-resistant member) is formed. Further, from this state, the polycrystalline silicon film 16 is etched using a dry etching technique, and the etching is stopped when the polycrystalline silicon film 16 outside the silicon oxide film 15 disappears, as shown in FIG. The upper side of the N-type source / drain region 5-1 and the silicon oxide film 1 according to the height of the convex portion of the polycrystalline silicon film 16 formed.
Below the 5, polycrystalline silicon film 16 is Ru residue. Silicon oxide
By selectively etching away the con film 15,
The conductor member 8 shown in FIG. 6 is formed.

Next, after the conductor member 8 is thermally oxidized, the CV
A polycrystalline silicon film is deposited by the method D, phosphorus is thermally diffused, and is patterned by a photolithography technique and a dry etching technique to obtain the capacitance insulating film 9 and the cell plate 10 shown in FIG.

Next, after depositing a third interlayer insulating film 11 made of a silicon oxide film by the CVD method, the contact hole 1 is formed.
2 is formed, and the bit line 13 is formed of an aluminum film, whereby the memory cell having the structure shown in FIG. 1 is obtained.

In the above description, a thermal oxide film of silicon is used as the capacitor insulating film 9, but one of the silicon oxide film and the silicon nitride film is mainly used for increasing the capacity and improving the reliability. Or a single-layer to three-layer structure using both.

In this embodiment, the bit line 13
Is an aluminum film and passes through the upper side of the storage electrode. However, aluminum may be changed to a polycide or the like having a higher separation point than the aluminum film and may pass through the lower side of the storage electrode.

[0021]

As described above, according to the present invention, a columnar, hollow, and flat upper end surface is used as a component of the storage electrode.
The withstand voltage of the capacitive insulating film is higher than when sharply pointed.
The effect is that the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of a memory cell of the present invention.

FIG. 2 is a cross-sectional view for explaining one embodiment of a method for forming a memory cell according to the present invention.

FIG. 3 is a cross-sectional view for explaining one embodiment of a method for forming a memory cell of the present invention.

FIG. 4 is a cross-sectional view for explaining one embodiment of a method for forming a memory cell according to the present invention.

FIG. 5 is a cross-sectional view for explaining one embodiment of a method for forming a memory cell according to the present invention.

FIG. 6 is a cross-sectional view for explaining one embodiment of a method for forming a memory cell according to the present invention.

FIG. 7 is a cross-sectional view for explaining one embodiment of a method for forming a memory cell according to the present invention.

FIG. 8 is a cross-sectional view illustrating an example of a conventional memory cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Silicon oxide film 3 Gate oxide film 4 Gate electrode 5-1 and 5-2 N-type source / drain region 6 First interlayer insulating film 7 Second interlayer insulating film 8 Conductor member 9 Capacitive insulating film 10 Cell plate 11 Third layer insulating film 12 Contact hole 13 Bit line 14 Resist 15 Silicon oxide film 16 Polycrystalline silicon film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (2)

(57) [Claims] 1. One MOS transistor and the MOS transistor
In a semiconductor memory cell in which a capacitance portion is connected to one source / drain region of a transistor and a bit line is connected to the other source / drain region , a lower layer in which a silicon nitride film is stacked on a silicon oxide film
An inter-layer insulating film covers the MOS transistor and the one side through an opening penetrating the lower interlayer insulating film.
Said capacitor section connected to the source and drain regions, the MOS transients from the <br/> one of the source and drain regions
Over the gate electrode of the star through the lower interlayer insulating film.
Provided hollow columnar connected to one source-drain region of the, and, with its upper end face is flat conductive member, a dielectric film formed on the entire surface of the conductive member, of the dielectric film
And a counter electrode formed over the entire surface, the lower interlayer insulating film and the capacitor portion is the upper interlayer insulating film covering
And the bit line selectively covers the upper interlayer insulating film.
And penetrates the upper interlayer insulating film and the lower interlayer insulating film.
The other source / drain region through the contact hole
A semiconductor memory cell connected to the region . 2. A step of forming a MOS transistor on a semiconductor substrate, and a lower layer formed by laminating a silicon nitride film on a silicon oxide film.
The MOS transistor is covered with an insulating film between the
One source of the MOS transistor is connected to the interlayer insulating film.
Forming an opening reaching the drain region; and connecting the lower interlayer insulating film to one of the source / drain regions of the MOS transistor through the opening.
A step of depositing a conductor film covering, by etching using the resist film as a mask, of the conductive film, thin the conductive film in a portion except for the one of the source and drain regions above said conductive Forming a convex portion on the body film, removing the resist film, and depositing a silicon oxide film on the entire surface
And, by etching back the silicon oxide film, wherein forming the anti-etch member made of silicon oxide film which selectively covers the side wall of the convex portion, and thereafter, etching the conductive film, said etching resistant the conductive film of the outer portion of the member to etch stops when it is completely removed, the lower side of the resistant etched member, columnar hollow and its top surface
It is flat, further formed a step of its bottom to form a conductive member connected to the source and drain of the one, a step of selectively removing the etching-resistant member, a dielectric film on the conductive member surface a step, by forming the counter electrode on the conductive film, and forming a capacitor portion, the upper interlayer insulating covering the lower interlayer insulating film and the capacitor portion
Forming a film, forming the upper interlayer insulating film and the lower interlayer insulating film.
Through the other source / drain of the MOS transistor.
Forming a contact hole reaching the
Connected to the other source / drain region via a hole
Forming a bit line .