JP2817834B2 - LCD substrate inspection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a liquid crystal substrate, and more particularly to a method for identifying a failure mode of a liquid crystal substrate.

[0002]

2. Description of the Related Art As a conventional method of identifying a failure mode of a liquid crystal substrate, as shown in FIG. 7, an operator visually inspects a substrate to be inspected using a microscope or the like, or forms a pattern by a defect inspection using a pattern inspection device. Inspection was underway.

[0005] Referring to FIG. 8, there are a conventional electric inspection apparatus (electric tester) for probing a wiring to measure a current between wirings, and one for probing a pixel electrode.

[0004] In any case, when the failure mode is specified by using these devices, the operation has solely relied on the work of a skilled technician (see FIG. 8).

[0005]

However, these conventional techniques have the drawbacks that when performing a shape inspection by hand, the number of human steps is increased, erroneous judgment is made, and the inspection time is lengthened. Further, there is a disadvantage that the shape abnormality does not always lead to an electrical failure.

Further, in the conventional electrical inspection, it is often not possible to detect a failure or to specify a failure mode in detail. Then, when trying to identify a failure mode, there is a problem that a skilled technician cannot take it for a long time.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problem and to provide an inspection method for automatically guiding a failure mode of a liquid crystal substrate in a short time.

[0008]

To achieve the above object, according to an aspect of the liquid crystal substrate inspection method of the present invention, the wiring and the liquid crystal substrate and a plurality of pixel electrodes and a plurality supplies a signal to the pixel electrode wiring In a method for inspecting a failure mode including a physical failure of a short circuit / open circuit between electrodes , an electric signal generating unit for applying an electric signal to at least a part of the plurality of wirings, and a pixel potential observing unit for observing a potential of the pixel electrode And
And an electric signal generating pattern for one or more tests, one also
Pair combinations of the pixel electrode potential expected value before <br/> Symbol crystal substrate against the said electrical signal generation patterns of a plurality of test
(Referred to as "test expected value vector")
A database stored corresponding to the mode ,
The electric signal generation pattern is applied to the liquid crystal substrate, and a set (referred to as a “test result vector”) including observation results of the pixel electrode potential by the pixel potential observation unit for each test and the pixel electrode potential It collates the set of expected value, both matches
The failure mode corresponding to the set of expected pixel electrode potentials.
The failure mode is identified as having occurred .

In the present invention, preferably, a plurality of test blocks including at least one type of test for generating an electric signal and observing the pixel electrode potential are provided. After executing a series of tests belonging to one test block, the execution result is compared with the expected value of the database, and the next test block to be executed is selected based on the comparison result.

[0010]

According to the present invention, in accordance with the present invention, a test result is collated with a database storing correspondence between a failure mode and an expected test value by an electrical test to select a next test to be performed or a failure mode. Is automatically performed, the cause of the failure can be specified in a short time and with high accuracy without relying on a skilled person.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

[0012]

Embodiment 1 FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, an electrical test signal generator
11 applies an electrical test signal to the liquid crystal substrate 12 and
The potential of the pixel electrode on 12 is observed by the pixel electrode potential observing section 13.

A test signal from the electric test signal generator 11 is applied to a row (ROW) gate signal line and a column (COLUMN) data line of the liquid crystal substrate 12 by probing. Note that the gate signal line is connected to the gate electrode of a thin film transistor (TFT) constituting the pixel, selects the pixel, and writes a signal to the pixel via the data line.

As a means for observing the potential in the pixel electrode potential observing section 13, for example, an electro-optic device (electrooptic device) is used.
The displacement of the potential is detected by light probing using ice) or the like. In addition, the optical probing using the electro-optical element, for example, a transparent electrode is provided at one end of the electro-optical crystal, a reflective film is provided at the other end facing the transparent electrode, laser light is incident on the electro-optical crystal, While the laser light reciprocates in the electro-optic crystal, the polarization of the laser light, which changes in proportion to the intensity generated between the object to be measured and the transparent electrode, is detected by optical means, and this is photoelectrically converted into an electric signal. What you get.

The test result obtained by the pixel electrode potential observing section 13 is compared with the failure database 16 by the comparing means 14.
Based on the result of the collation, the failure mode estimation means 15
The failure mode of is specified.

As a matching method in the matching means 14, first, a plurality of combinations of test signal generation and potential observation are executed, and a test result vector is generated from the result.

For example, if the result of Test 1 is Low, the result of Test 2 is High, and the result of Test 3 is High, the test result vector is (0, 1, 1).

Next, a test expected value vector and a test result vector corresponding to one failure mode 1 in the failure database that associates the failure mode with the test expected value are compared.

If the test expected value vector and the test result vector are equal to each other, it is estimated that the failure mode 1 has occurred.

If these vectors are different, the test expected value vector corresponding to failure mode 2 and the test result vector are compared. In this way, the test expected value vector that is equal to the test result vector is searched in the failure database 16, and it is concluded that the failure mode having the expected value vector is the probable cause.

[0021]

Second Embodiment A second embodiment of the present invention will be described below.
As shown in FIG. 2, the present embodiment has a plurality of test blocks including one or a plurality of tests. For example, the test block 1 includes a sequence such as a test 1.1 and a test 1.2, and a series of tests belonging to one test block are collectively executed.

After executing all the tests in one test block, the execution result is checked against the failure database, and the next test block to be executed is selected and executed. In this way, the test blocks are executed one after another according to the execution result, and the failure mode is determined.

FIG. 3 shows an execution flow of these test blocks. Referring to FIG. 3, for example, as a result of execution of test block 1, test block 5 is executed when a pass (Pass) (that is, a non-defective product), and test block 3 is executed when a failure occurs. And the failure mode is determined.

As described above, the failure mode is determined by executing the shortest test block.

The method of executing the test block in this embodiment is an expert system for specifying a failure mode of the liquid crystal, so that the failure mode can be automatically specified in a short time.

Next, a specific example in the case where the present invention is applied to the specification of a failure mode of a liquid crystal substrate will be described.

FIG. 4 shows a specific example of the configuration of the liquid crystal substrate and the failure mode. Referring to FIG. 4, the gate signal on the ROW side is connected to the gate electrode of the TFT, the TFT is turned on, and the data signal on the COLUMN side is led from the drain electrode of the TFT to the pixel electrode. There are shorts / opens between signal lines and electrodes. Note that a liquid crystal layer (not shown) is sealed between the pixel electrode and a counter electrode (not shown).

FIG. 5 shows an example of a test pattern in this embodiment, and FIG. 6 shows an example of a failure database.

As shown in FIG. 5, the gate signal and the data signal are driven at a High or Low potential, and a potential observation strobe measures the potential of the pixel electrode at the High timing.

FIG. 6 shows the relationship between the failure mode and the expected test value in this case.

That is, referring to FIG. 5, in test 1, a High level is written to a pixel electrode via a data signal, a gate electrode of the TFT is set to Low, and a drain electrode is set to Hig.
As h, the potential of the pixel electrode is electro-optically observed with a potential observing strobe, a low level is written to the pixel electrode in test 2, and the gate electrode and the drain electrode of the TFT are set to Hig.
The potential of the pixel electrode is observed as h, the High level is written to the pixel electrode in Test 3, the gate electrode and the drain electrode of the TFT are set to Low, and the potential of the pixel electrode is observed.
In Test 4, the Low level is written to the pixel electrode, and TF
When a series of tests in which the gate electrode of T is set to Low and the drain electrode is set to High and the potential of the pixel electrode is observed, and the liquid crystal substrate to be tested is a non-defective product, a test 1 is performed as shown in FIG. The observed potentials of ~ 4 are "HLHL"
Becomes

On the other hand, if there is a short circuit between the source and the drain of the TFT, the observation potential of Tests 1 to 4 becomes “HLLH”, and the observation potential of Tests 1 to 4 becomes constant, for example, “LLLL”. In this case, it is estimated that there is an open failure between the source and the drain of the TFT.

This example of a test pattern specifies a failure mode in each pixel. However, a test pattern can be created in the same manner when specifying a failure between adjacent pixels or between electrodes. I can do it.

In this embodiment, the present invention has been described as a method of observing a pixel potential based on an example of optical probing using an electro-optical element. However, observation of a potential change due to capacitive coupling, observation of a CCD after mounting a panel, etc. The same can be applied to the observation method by.

[0035]

As described above, the present invention (claim 1)
According to the configuration described above, the electrical test is configured to automatically estimate the failure mode by comparing the obtained test result with a database indicating the correspondence between the failure mode and the test expected value. This has the effect of estimating the cause of a failure in a short time without relying on the test, and achieves automation and efficiency of the inspection process, improvement of the inspection accuracy, and drastically reduces the test cost.

Further, according to the present invention (claim 2), the test result is compared with the database storing the correspondence between the failure mode and the expected test value by the electrical test, and the selection of the next test is automatically performed. This makes it possible to automatically estimate the failure mode by executing the shortest test block, thereby achieving automation and efficiency of the inspection process, improvement of inspection accuracy, and reduction of test cost. Further, according to the present invention (claim 3), a failure location is specified,
Further, it is possible to automatically derive a failure mode such as an open failure or a short-circuit failure, thereby making the inspection process more efficient and greatly reducing the test cost.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration example of a liquid crystal substrate and an example of a failure mode.

FIG. 5 is a timing chart showing an example of a test pattern according to the present invention.

FIG. 6 is a diagram showing an example of a failure database according to the present invention.

FIG. 7 is a diagram illustrating a conventional inspection method.

FIG. 8 is a diagram illustrating another conventional inspection method.

[Explanation of symbols]

 Reference Signs List 11 Electric test signal generation unit 12 Liquid crystal substrate 13 Pixel electrode potential observation unit 14 Matching unit 15 Failure mode estimation unit 16 Failure database

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/00 G01R 31/28 G01R 31/302-31/3163

Claims (3)

(57) [Claims] A liquid crystal substrate having a plurality of pixel electrodes and a plurality of wirings for supplying signals to the pixel electrodes ;
In a method of inspecting a failure mode including a short-circuit / open physical failure, an electric signal generation unit that applies an electric signal to at least a part of the plurality of wirings, and a pixel potential observation unit that observes a potential of the pixel electrode. comprising an electric signal generating pattern for one or more tests, one also
Pair combinations of the pixel electrode potential expected value before <br/> Symbol crystal substrate against the said electrical signal generation patterns of a plurality of test
(Referred to as "test expected value vector")
Includes a database storing in correspondence with the mode, and applying said electrical signal generating pattern to the liquid crystal substrate, consisting watch <br/> measurement results for each test pixel electrode potential by the pixel potential observation unit collating the set of pairs ( "test result vector") and the pixel electrode potential expected value numbers match
The failure mode corresponding to the set of expected pixel electrode potentials.
A method for inspecting a liquid crystal substrate, wherein a failure mode is specified as a state in which a failure has occurred . A plurality of test blocks each including at least one test for generating an electric signal and observing the pixel electrode potential, and a series of test blocks belonging to one test block among a plurality of test blocks different from each other. 2. The liquid crystal substrate inspection method according to claim 1, wherein after executing the test, the execution result is compared with an expected value in the database, and a test block to be executed next is selected based on the comparison result. 3. The database stores in advance a pixel potential expected value corresponding to a failure mode between the wiring and the electrode, and automatically determines a failure location and a failure mode based on the observation result of the pixel electrode potential. 2. The liquid crystal substrate inspection method according to claim 1, wherein the method is derived.