JP2815264B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device comprising, for example, an active matrix type liquid crystal display panel and a data driver having a bus line for inputting an analog data signal such as a video signal to the liquid crystal display panel. .

[0002]

2. Description of the Related Art Conventionally, the above-mentioned liquid crystal display device is known which is configured as shown in FIG. This liquid crystal display device includes a liquid crystal display panel 31 and a data driver 30. The data driver 30 includes a shift register circuit 1 and a plurality of shift register output bus lines 2 having one ends connected to the shift register circuit 1. . The other end of each shift register output bus line 2 is connected to a thin film transistor 7 which is an analog switch.

Each thin film transistor 7 is turned on and off between two terminals under the control of an output signal from the shift register circuit 1. One of the two terminals has R, G, B
One of the video signal input bus lines 3, 4, and 5 is connected via an analog switch input bus line 6, and the other terminal is connected to a sampling capacitor 8 and a display bus line 10 of a liquid crystal display panel 31. Are connected in parallel. The other end of the sampling capacitor 8 is connected to the common electrode 9. The thin film transistor 7 and the sampling capacitor 8 form a sample and hold circuit.

On the other hand, the liquid crystal display panel 31 includes the above-described display bus line 10 and the scan-side display bus line 11 wired so as to intersect with the display bus line 10. A pixel electrode 14 is provided in a region surrounded by the display bus lines 10 and 11, and a thin film transistor 12 which is an analog switch is provided between the display bus lines 10 and 11 and the pixel electrode 14. Between the thin film transistor 12 and the common electrode 9.
3 are provided.

[0005]

By the way, in the conventional liquid crystal display device, since the input bus lines 3, 4, and 5 are formed close to each other, each of the input bus lines 3, 4, and 4 is formed. And 5 have parasitic capacitances 16, 1 and 2, respectively.
6 results. Further, a parasitic capacitance 19 is generated between the shift register output bus line 2 and the analog switch input bus line 6. Further, between the pixel electrode 14 and the display bus line 10 approaching each other, and the similar pixel electrode 1
Parasitic capacitances 21 and 22 are generated between the scan bus 4 and the scan-side display bus line 11, respectively.

In addition, shift register output bus line 2
Wiring portions where the input bus lines 3, 4, and 5 intersect;
A wiring portion where the input bus line 5 and the analog switch input bus line 6 intersect, and a display bus line 10
In a wiring portion or the like where the scanning bus line 11 intersects with the scan side, an interlayer insulating film is usually provided to perform multilayer wiring. However, when the thickness of the interlayer insulating film is small,
A parasitic capacitance that cannot be ignored is generated in the above-mentioned crossing wiring portion. Specifically, parasitic capacitances 17, 17, and 17 occur between the shift register output bus line 2 and the input bus lines 3, 4, and 5, respectively, and the input bus line 5 and the analog switch input bus line 6 Between the display bus line 10 and the display bus line 11 on the scan side.
Will occur.

For this reason, in the conventional liquid crystal display device, signals having different phases and amplitudes are input to the input bus line and the display bus line despite the occurrence of the parasitic capacitance described above. As a result, there is a problem that crosstalk occurs in the analog data signal and image quality on the liquid crystal display panel is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and prevents the occurrence of parasitic capacitance.
It is an object of the present invention to provide a liquid crystal display device capable of suppressing occurrence of crosstalk and deterioration of image quality of a liquid crystal display panel.

[0009]

According to a liquid crystal display device of the present invention, picture element electrodes are arranged in a matrix.
A liquid crystal display comprising: an active matrix type liquid crystal display panel having a display bus line formed in a display area including the picture element electrode; and a data driver having an input bus line for inputting an analog data signal to the liquid crystal display panel. In the device, both the input bus line of the data driver and part or all of the display bus line of the liquid crystal display panel are provided .
On the side, a shield wiring formed in the same layer as the bus line and grounded is provided, thereby achieving the above object. The input bus line and the display bus line
Cover part or all of the inside via an insulating film, and
Other seal connected to the shield wiring via the insulating film
May be provided.

The shield wiring is provided for the display bus line and the picture element electrode, an interlayer insulating film is interposed between the display bus line and the picture element electrode, and 1 μm or more and 10 μm or more. You may form so that it may overlap below.

A thin film transistor connected to the display bus line and the picture element electrode to provide a thin film transistor; and a thin film transistor group constituting a data driver for inputting analog data to a liquid crystal display panel; and the input bus. Another thin film transistor may be provided so as to be connected to the line and the display bus line, and each of the thin film transistor group forming the thin film transistor and the data driver and the other thin film transistor may be formed using polycrystalline Si.

[0012]

According to the present invention, a part or all of the input bus line of the data driver and the display bus line of the liquid crystal display panel is provided with a shielded wire grounded. For this reason, it is possible to eliminate the influence of the parasitic capacitance and to prevent the occurrence of crosstalk of the analog data signal.

Further, a shield wiring is provided between the display bus line and the picture element electrode with an interlayer insulating film interposed therebetween, and
When formed so as to overlap with each other in a range of μm or more and 10 μm or less, light leakage caused by distortion of the electric field distribution around the pixel electrode is prevented.

Further, when a data driver for inputting analog data to a liquid crystal display panel using polycrystalline Si is integrally formed on the same substrate, a control signal for operating the data driver and an output of the data driver are provided. Although crosstalk occurs due to the influence of signals, etc., by forming the shield wiring between the data driver and the analog data signal line, it is possible to eliminate the influence of the parasitic capacitance and prevent the occurrence of crosstalk. Becomes possible.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below.

FIG. 1 is an equivalent circuit diagram showing the liquid crystal display device of the present embodiment. The liquid crystal display device includes a liquid crystal display panel 31 and a data driver 30 formed on the same substrate. The data driver 30 includes a shift register circuit 1 and a plurality of shift registers each having one end connected to the shift register circuit 1. It includes a shift register output bus line 2 and a thin film transistor 7 as an analog switch connected to the other end of each shift register output bus line 2.

Each thin film transistor 7 has a gate electrode formed on one side with a semiconductor layer made of polycrystalline Si interposed therebetween, and a source electrode and a drain electrode formed on the other side. A shift register output bus line 2 is connected to the gate electrode, and an R, G, B video signal input bus line 3 via an analog switch input bus line 6 to the source electrode.
The sampling capacitor 8 and the display bus line 10 of the liquid crystal display panel 31 are connected in parallel to the drain electrode. The thin film transistor 7 is turned on and off between two terminals, a source electrode and a drain electrode, under the control of an output signal from the shift register circuit 1.

The other end of the sampling capacitor 8 is connected to a common electrode 9, and the thin film transistor 7 and the sampling capacitor 8 constitute a sample and hold circuit.

As shown in FIG. 2, shield wirings 16a and 16b are formed between the input bus lines 3, 4 and 5, and shield wirings are similarly provided outside the input bus lines 3 and 5. Wirings 16c and 16d are formed,
An insulating film 17a is formed to cover the shield wirings 16a, 16b, 16c, 16d and the input bus lines 3, 4, 5. As shown in FIG. 3, the shield wiring 16f is formed over the entire length of the analog switch input bus line 6 with the upper and lower layers interposed between interlayer insulating films 17a and 17b. Similarly, also for the shift register output bus line 2, the shield wiring 16e is formed over the entire length by being sandwiched between upper and lower interlayer insulating films (not shown). Shield wirings 16a, 16b, 16c, 16d, 1
Each end of 6f and 16e is grounded. The shield wirings 16f and 16e described above are always provided at the portions where the input bus lines 3, 4 and 5 intersect, but they may be omitted in other portions without any problem.

On the other hand, the liquid crystal display panel 31 includes the above-described display bus line 10 and the scan-side display bus line 11 wired so as to cross the display bus line 10. A pixel electrode 14 is provided in a region surrounded by the display bus lines 10 and 11, and a thin film transistor 12 which is an analog switch is provided to be connected to the display bus lines 10 and 11 and the pixel electrode 14. . The thin film transistor 12 has a configuration in which a gate electrode is formed on one side of a semiconductor layer made of polycrystalline Si, and a source electrode and a drain electrode are formed on the other side, and the display bus line 11 is connected to the gate electrode. The display bus line 10 is connected to the source electrode, and the picture element electrode 14 is connected to the drain electrode. A storage capacitor 13 is provided between the thin film transistor 12 and the common electrode 9.

With respect to the display bus line 10, a shield wiring 16g is formed so as to be sandwiched between upper and lower interlayer insulating films (not shown) over the entire length. In the display area where the electrode 14 is provided, the shield wiring 16h is formed by sandwiching the upper and lower portions between interlayer insulating films (not shown). These shield wirings 16g and 16h have their respective ends grounded. In addition, the shield wiring 16g described above,
16h is always provided at a portion where the display bus line 10 and the scan-side display bus line 11 intersect with each other and at a portion passing near the pixel electrode 14; There is no. However, in the portion passing near the pixel electrode 14, these shield wirings 16g and 16h
Represents an interlayer insulating film interposed between the display bus lines 10 and 11 and the picture element electrode 14, and 1 μm to 10 μm
It forms so that it may overlap below.

Therefore, in the liquid crystal display device thus constructed, the input bus lines 3, 4, 5, the shift register output bus line 2, and the analog switch input bus line 6 are grounded as described above. The shield buses 16a, 16b, 16c, and 16d are provided, so that even if analog data signals having different phases and amplitudes are input, the input bus lines 3,
No parasitic capacitance is formed between the fourth and fifth shift register lines and between the shift register output bus line 2 and the analog switch input bus line 6, and no crosstalk occurs.

Further, since the shield wirings 16g and 16h are provided between the display bus lines 10 and 11 and the pixel electrodes 14, a parasitic capacitance is generated near the display bus lines 10 and 11. Therefore, the occurrence of crosstalk can be prevented. In addition, shield wiring 16g, 16h
Are formed so as to overlap the display bus lines 10 and 11 and the pixel electrodes 14 by 1 μm or more and 10 μm or less, so that light leakage caused by distortion of the electric field distribution around the pixel electrodes 14 Prevented by the presence of 16g, 16h.

Further, when a data driver for inputting analog data to a liquid crystal display panel using polycrystalline Si is integrally formed on the same substrate, a control signal for operating the data driver and an output of the data driver are provided. Although crosstalk occurs due to the influence of signals, etc., by forming the shield wiring between the data driver and the analog data signal line, it is possible to eliminate the influence of the parasitic capacitance and prevent the occurrence of crosstalk. Becomes possible.

For the above reasons, according to the present invention,
Since the occurrence of crosstalk can be prevented, a high-quality display can be obtained.

[0026]

As described above, according to the present invention, since the shield wiring is provided at the place where the parasitic capacitance is likely to occur, the occurrence of the crosstalk between the analog data signals can be prevented. The display quality can be improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a liquid crystal display device of the present embodiment.

FIG. 2 is a sectional view showing the vicinity of an input bus line in FIG. 1;

FIG. 3 is a sectional view showing the vicinity of an input bus line (including an analog switch input bus line) in FIG. 1;

FIG. 4 is an equivalent circuit diagram showing a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register circuit 2 Shift register output bus line 3 R video signal input bus line 4 G video signal input bus line 5 B video signal input bus line 6 Analog switch input bus line 7 Thin film transistor 8 Sampling capacitor 9 Common electrode 10 Display bus line 11 Display bus line on scan side 12 Thin film transistor 13 Storage capacitance 14 Pixel electrode 16a Shield wiring 16b Shield wiring 16c Shield wiring 16d Shield wiring 16f Shield wiring 16e Shield wiring

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-213981 (JP, A) JP-A-63-97919 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/136 G02F 1/133 G02F 1/1343 G02F 1/1345

Claims (2)

(57) [Claims] 1. An active matrix type liquid crystal display panel in which picture element electrodes are arranged in a matrix and a display bus line is formed in a display area including the picture element electrodes. A liquid crystal display device comprising a data driver having an input bus line for inputting to a liquid crystal display panel, wherein the data driver has an input bus line and a part or all of the display bus line of the liquid crystal display panel. bus
A liquid crystal display device provided with a shield wiring which is formed in the same layer as a line and is grounded. 2. The input bus line and the display bus.
Covering part or all of the line via an insulating film, and
Other shields connected to the shield wiring via the insulating film
2. The liquid crystal display device according to claim 1 , further comprising a ground wiring .