JP2814922B2 - Balance clock input signal abnormality detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a balance clock input signal abnormality detection circuit for detecting an abnormality in a reception clock between packages.

[0002]

2. Description of the Related Art A circuit of this type for detecting an abnormality by inputting a clock from a balanced signal in which two clock signals having opposite phases to each other are transmitted as a set of signals,
It is configured as shown in FIG. That is, in FIG. 3, reference numeral 1 denotes a clock reception package. The clock reception package 1 includes a balance input gate 2 for receiving a balance signal from a clock transmission package described later and outputting a clock signal 8, and a balance input gate 2 for receiving the balance signal. A pull-up or pull-down resistor for setting the potential of the balance signal to a predetermined potential at the input stage (the corresponding signal is TTL
(A pull-up resistor in the case of the level, a pull-down resistor in the case of the ECL level) 12 and a clock loss detecting unit 15 which detects a clock loss from the clock signal 8 and outputs a clock loss alarm 14.

The above-mentioned clock transmission package 9 for transmitting a balance signal to the clock reception package 1 is described.
Is composed of a balance output gate 11 which converts an input clock signal 10 into a balance signal and sends it out. Next, the operation of the balanced output gate 11 and the balanced input gate 2 in the circuit configured as described above will be described. First, in the balance output gate 11, a clock (positive phase) in phase with the input clock signal 10 is input.
And a clock whose logic is inverted (opposite phase), and generates and outputs a balance signal having one set of signals. On the other hand, the balanced input gate 2 outputs an "H" level signal when the input voltage level of the normal phase clock is higher than the input voltage level of the negative phase clock when two clocks of the normal phase and the negative phase are input. If the voltage level of the negative-phase clock is higher, an "L" level signal is output. As a result, a clock having the same phase as the input positive-phase clock is output as the clock signal 8.

[0004] From the clock signal 8 thus output,
Clock interruption is detected as follows. That is, the clock signal 8 output from the balance input gate 2 is input to the clock loss detection unit 15, and the clock loss detection unit 15
The clock signal 8 is monitored for a certain time (protection time).
If the logic level of the clock signal 8 does not change for a certain period of time ("H" level fixed or "L" level fixed), it is determined that the clock has been cut off, and the clock cutoff alarm signal 14 is set to, for example, "H". And output it as a "level alarm presence signal". On the other hand, the clock disconnection detector 1
If the clock signal 8 input to 5 changes within a certain period of time, the clock loss alarm signal 14 is output as an "L" level alarmless signal.

[0005]

In a conventional circuit for detecting a clock break by inputting a balance signal composed of two clock signals of a normal phase and a negative phase, the input side of the balance input gate 2 becomes open, for example. When both clock signals are fixed at the “H” level or fixed at the “L” level, no difference in voltage level occurs on the input side. In such a case, when noise is input from the positive phase input terminal or the negative phase input terminal of the balance input gate 2, the balance input gate 2 operates to output a signal due to the noise,
This is erroneously detected as a clock signal by the clock disconnection detection unit 15. Therefore, there is a problem that an alarm signal cannot be output from the clock-disconnection detecting unit 15 despite the clock-disconnection.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to reliably detect a clock break when a balance signal composed of two clock signals of a normal phase and a negative phase is input.

[0007]

According to the present invention, there is provided a balance signal comprising a first clock signal having a positive phase and a second clock signal having a phase opposite to that of the first clock signal. And a balance input gate for inputting a balance signal and outputting one of a first clock signal and a second clock signal, the balance input gate comprising: A first abnormality detection unit connected to the input side of the first circuit and detecting abnormality of the first clock signal; a second abnormality detection unit connected to the input side of the balance input gate and detecting abnormality of the second clock signal; , Rutotomoni provided a first logical sum unit by entering the respective detection outputs of the first and second abnormality detection section for outputting a logical sum of the detection outputs, the first and second abnormality
A low-pass filter that averages an input clock signal and outputs the signal as a DC voltage level signal to a detection unit; and a determination unit that determines whether an output of the low-pass filter is within a predetermined voltage level range. only set the door, and the determination section, a positive
Normal clock signal and averaged DC voltage level and clock
Threshold value set during the "H" logic level of the lock signal
Is compared with the output level of the low-pass filter.
The comparison unit and the DC voltage level where the normal clock signal is averaged.
Between the bell and the "L" logic level of the clock signal.
The second threshold value and the output level of the low-pass filter.
A second comparison unit to be compared, and each comparison of the first and second comparison units
The second theory that inputs the output and outputs the logical sum of each comparison output
And a Riwa section .

Further, the first and second thresholds are set in association with the duty ratio of a clock signal.

[0009]

A first abnormality detecting section for detecting an abnormality of a first clock signal which is a normal phase clock and a second detecting section for detecting an abnormality of a second clock signal which is a reverse phase clock are provided at the input side of a balance input gate. Is provided, and the respective detection outputs of the first and second abnormality detection units are inputted, and the logical sum thereof is output as an alarm signal. As a result, even if any one of the clock signals becomes abnormal, the clock abnormality can be detected. Further, the input clock signal is averaged and output as a DC voltage level, and it is determined whether or not this output level is within a predetermined voltage level range. As a result, even if the input side of the balance input gate is open and the clock is cut off, and the input result of each clock signal is fixed at the “H” level or fixed at the “L” level, the clock is abnormal. Can be accurately detected.

A first threshold is set as a level between the DC voltage level and the "H" logic level of the clock signal, and a second threshold is set as a level between the DC voltage level and the "L" logic level of the clock signal. Set the threshold of
The clock signal is determined to be normal when the output level of the low-pass filter exists between the threshold value and the second threshold value.
As a result, the correctness of the clock signal can be accurately determined. Further, the first and second threshold values are set in association with the duty ratio of the clock signal. As a result, the deterioration of the duty of the clock signal can be detected.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the same parts as those of the conventional circuit shown in FIG. That is, in the circuit of this embodiment, 31 and 32 are low-pass filters,
Reference numerals 1 and 42 denote positive voltage abnormality detectors, 51 and 52 denote negative voltage abnormality detectors, and 61, 62 and 7 denote OR gates.

Here, in the clock transmitting package 9, when the clock signal 10 is converted into a balanced signal by the balance output gate 11 and output to the clock receiving package 1 as positive and negative phase clocks, respectively, The balance input gate 2 receives the positive phase clock and the negative phase clock of the balance signal and generates a clock signal 8. The positive-phase and negative-phase clocks forming the balance signal are input to respective low-pass filters 31 and 32 connected to the input side of the balance input gate 2.

The cut-off frequency of the low-pass filter 3 is set to a value sufficiently smaller than the frequency of the clock signal, and a DC level signal whose input is averaged is output from the output side of the low-pass filter 3. You. The output of the low-pass filter 31 to which such a positive-phase clock is input is supplied to the + side voltage abnormality detection section 41 and the − side voltage abnormality detection section 51, respectively.
Is input to Here, in the + side voltage abnormality detecting section 41,
If the input voltage is higher than the threshold voltage, for example, an "H" level alarm is output, and if not, an "L" level no alarm is output. If the input voltage is smaller than the threshold voltage, the "-" side voltage abnormality detection section 51 outputs "H" level alarm presence, otherwise outputs "L" level alarm absence.

On the other hand, the outputs of the low-pass filter 31 for inputting the negative-phase clocks are output from the + side voltage abnormality detectors 42 and-, respectively.
It is input to the side voltage abnormality detection section 52. Here, the operations of the + side voltage abnormality detection section 42 and the − side voltage abnormality detection section 52 are the same as the above-described operations of the + side voltage abnormality detection section 41 and the − side voltage abnormality detection section 51. + Side voltage abnormality detector 4
The-and-side voltage abnormality detection unit 5 includes a comparator 40 (first comparison unit) and a comparator 50 (second comparison unit) as shown in FIG. The presence or absence of an alarm is detected by comparing the threshold voltages with each other.

Here, the threshold voltage of the + side voltage abnormality detecting section 4 is set to a value higher than a voltage level obtained by averaging a normal clock (duty: 50%) and smaller than a logic level indicating the "H" level of the clock. Set. On the other hand, the threshold voltage of the negative voltage abnormality detector 5 is set to a value slightly smaller than a voltage level obtained by averaging a normal clock and larger than a logic level indicating the “L” level of the clock.

As described above, by setting the threshold voltage to each of the + side voltage abnormality detection section 4 and the − side voltage abnormality detection section 5, when the clock input of the balance signal is fixed at the "H" level, the + side voltage abnormality is detected. When the voltage abnormality is detected by the voltage abnormality detection unit 4 and the voltage is fixed at the “L” level, the clock abnormality is detected by the negative voltage abnormality detection unit 5 and an alarm indicating the clock abnormality is output.

Further, by improving the accuracy of the threshold voltages of the + side voltage abnormality detection section 4 and the − side voltage abnormality detection section 5, deterioration of the clock duty can be detected. That is, for example, if the set value of the + side voltage abnormality detection unit 4 is set to be exactly halfway between the voltage level obtained by averaging the clock with the duty of 50% and the logic level of the signal “H”, When the duty is reduced to 75%, a clock abnormality alarm can be output.

In a logical sum unit 61 (second logical sum unit) which inputs each output of the + side voltage abnormality detection unit 41 and the − side voltage abnormality detection unit 51 and outputs a logical sum of them, each detection unit 41
If there is a clock abnormality detection output in any of
For example, an "H" level alarm is output. on the other hand,
A logical sum unit 6 that receives the outputs of the + side voltage abnormality detection unit 42 and the − side voltage abnormality detection unit 52 and outputs a logical sum of them.
2 (the second OR unit) is the same as the OR unit 61. If any of the detection units 42 and 52 has a clock abnormality detection output, it outputs an "H" level alarm.

The OR unit 7 (first OR unit) receives the outputs of the OR units 61 and 62, performs an OR operation on them, and outputs an alarm signal 13 indicating a clock abnormality. That is, if any one of the outputs of the respective OR units 61 and 62 is at the "H" level (even if both outputs the "H" level), the alarm signal 13 is used as the alarm signal 13, for example. An "H" level alarm presence signal is output. If all the outputs are at the "L" level, an "L" level no alarm signal is output as the alarm signal 13.

As described above, the abnormality detection circuit for detecting the abnormality by inputting the positive and negative phase clocks to the balance input gate 2 is provided, and the output of each abnormality detection circuit is OR-operated to generate the alarm signal. Is output. Therefore, even if both clocks of the input balance signal are fixed at "H" level or abnormal at "L" level, this is always detected and an alarm is output. can do.

[0021]

As described above, according to the present invention, the first input which is the positive-phase clock is applied to the input side of the balance input gate.
A first abnormality detection unit for detecting an abnormality of the clock signal and a second abnormality detection unit for detecting an abnormality of a second clock signal that is a reverse-phase clock, and each of the first and second abnormality detection units is provided. Since the detection output is input and the logical sum thereof is output as an alarm signal, even if any one of the clock signals becomes abnormal, it can be detected as a clock abnormality. Further, the input clock signal is averaged and output as a DC voltage level, and it is determined whether or not this output level is within a predetermined voltage level range. Therefore, the input side of the balance input gate is opened. Even if the clock is cut off and the input result of each clock signal is fixed at the “H” level or fixed at the “L” level, the clock abnormality can be accurately detected.

A first threshold is set as a level between the DC voltage level and the "H" logic level of the clock signal, and a second threshold is set as a level between the DC voltage level and the "L" logic level of the clock signal. Set the threshold of
The clock signal is determined to be normal when the output level of the low-pass filter exists between the threshold value and the second threshold value, so that the correctness of the clock signal can be determined accurately. Further, since the first and second thresholds are set in association with the duty ratio of the clock signal, it is possible to detect deterioration of the duty of the clock signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram of a + side voltage abnormality detection unit and a − side voltage abnormality detection unit which constitute the circuit of the embodiment.

FIG. 3 is a block diagram of a conventional circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Clock reception package, 2 ... Balanced input gate, 31 and 32 ... Low-pass filter, 41 and 42 ... + side voltage abnormality detection part, 51 and 52 ...- side voltage abnormality detection part, 6
1, 62, 7 ... OR section, 8, 10 ... clock signal, 9
... Clock sending package, 11 ... Balance output gate, 40,50 ... Comparator, 13 ... Alarm signal.

Claims (2)

(57) [Claims] A first clock signal having a positive phase;
A balance clock input signal abnormality detection circuit for detecting a balance signal abnormality by inputting a balance signal composed of a second clock signal having a phase opposite to that of the clock signal; A balanced input gate for outputting one of the clock signals,
A first abnormality detection unit connected to the input side of the balance input gate for detecting an abnormality of the first clock signal; and a first abnormality detection unit connected to the input side of the balance input gate for detecting an abnormality of the second clock signal a second abnormality detector, the Ru and a first logical sum unit for outputting a logical sum of the detection output to input detection outputs of the first and second abnormality detection section
In both cases, the input clock signal is supplied to the first and second abnormality detection units.
Signal to average and output as DC voltage level signal
The output of the low-pass filter
A determination unit that determines whether the voltage is within the range of the voltage level.
And the determination unit has a function of determining whether the normal clock signal is averaged.
Current level and the "H" logic level of the clock signal.
A first threshold value set between the first threshold value and the low-pass filter;
A first comparator for comparing the output level with a normal clock;
The DC voltage level at which the signal is averaged and the clock signal
The second threshold set between the “L” logic levels of
A second ratio comparing the output level of the low-pass filter with the output level
A comparison unit and each comparison output of the first and second comparison units
And a second OR unit that outputs a logical sum of each comparison output
And the determination unit is configured to determine between the first threshold value and the second threshold value.
When the output level of the low-pass filter exists
A balance clock input signal abnormality detection circuit, wherein each clock signal is determined to be normal . 2. The clock signal according to claim 1, wherein the first and second thresholds are set to a duty cycle of the clock signal.
A balance clock input signal abnormality detection circuit, which is set in association with the input / output ratio .