JPH0887422A - Digital signal circuit - Google Patents

Abstract

PURPOSE: To obtain the digital signal circuit which decides that a circuit constituent element or wiring part is defective on the basis of the detection signal of a digital signal. CONSTITUTION: The digital signal circuit is equipped with a 1st circuit 20 which outputs a detection signal by detecting one of the ON or OFF, and 'H'-level or 'L'-level state of the inputted digital signal, a 2nd circuit 21 which outputs a detection signal by detecting one of the ON or OFF state and 'H'-level or 'L'-level state of the digital signal, and an abnormality deciding means 43 which decides the abnormality of the circuit to which the digital signal is inputted on the basis of the detection signal outputted from the 1st circuit 20 and the detection signal outputted from the 2nd circuit 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal circuit for identifying an abnormality occurring in a circuit based on a signal output from the circuit.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional digital signal circuit using a photocoupler, for example, used as an input circuit or an output circuit of a digital signal transmission line, or a signal input circuit to a CPU or a signal output circuit from a CPU. It is a circuit diagram which shows a structure. In the figure, 1 and 2 are switches 3
An input terminal for inputting a contact signal by turning on / off of, a current limiting resistor circuit composed of two resistors connected in series and a capacitor connected between the connection point of these resistors and the ground, and 5 a light emitting diode A photocoupler composed of a phototransistor, 6 is an input side power supply line to which the anode side terminal of the light emitting diode is connected, and 7 and 8 are input side ground terminals, which are commonly connected.

Reference numeral 9 is a load resistor connected between the collector terminal of the phototransistor of the photocoupler 5 and the power supply terminal 10 on the output side. Reference numeral 11 is an inverter circuit 13 which outputs a digital signal by turning on / off the phototransistor of the photocoupler 5. Input resistance to be supplied to the inverter circuit 12 is an inverter circuit 13
Is a capacitor connected to the input terminal of, and 14 is a ground terminal on the output side, and the ground terminals 14 and 15 on the output side are commonly connected.

In this digital signal circuit, the switch 3
Is turned on, a predetermined current flows from the power supply line 6 on the input side to the ground terminal 8 on the input side through the light emitting diode of the photocoupler 5 and the current limiting resistance circuit 4, causing the light emitting diode of the photocoupler 5 to emit light. As a result,
The phototransistor of the photocoupler 5 is turned on, the potential of the collector terminal of the phototransistor drops to about ground level, and this'L 'level signal is input resistance 1
It is supplied to the input terminal of the inverter circuit 13 via 1 and is output as an'H 'level signal inverted by the inverter circuit 13.

When the switch 3 is off, the light emitting diode of the photocoupler 5 does not emit light, and as a result, the phototransistor of the photocoupler 5 is off.
Therefore, the potential of the collector terminal of the phototransistor is the power supply voltage on the output side that is applied to the power supply terminal 10 on the output side, and this'H 'level signal is input to the input terminal of the inverter circuit 13 via the input resistor 11. The signal is supplied and output as an'L 'level signal inverted by the inverter circuit 13.

[0006]

Since the conventional digital signal circuit is constructed as described above, if a defect occurs in the photocoupler 5, other circuit constituent elements, or the wiring portion, the inverter circuit 13 will not operate. The output is fixed at'H 'level or'L' level. Therefore, if attention is paid only to the output signal of the inverter circuit 13, is the output signal of the inverter circuit 13 fixed at the “H” level or the “L” level depending on the result of the normal operation of the digital signal circuit? Alternatively, there is a problem that it is impossible to determine whether the signal is fixed at the “H” level or the “L” level due to an abnormality that has occurred in the digital signal circuit.

The invention of claim 1 is to solve the above problems, and an object thereof is to obtain a digital signal circuit capable of discriminating a defect occurring in a circuit component or a wiring portion. .

It is an object of the present invention to provide a digital signal circuit which can discriminate a defect that has occurred in a circuit constituent element or a wiring section.

It is an object of the invention of claim 3 to obtain a digital signal circuit capable of outputting a signal indicating that a defect has occurred in a circuit constituent element or a wiring portion.

It is an object of the present invention to obtain a digital signal circuit capable of preventing erroneous signal transmission due to a defect generated in a circuit component or a wiring section.

According to a fifth aspect of the present invention, reliability of abnormality determination is prevented by preventing erroneous output of a determination signal indicating that a circuit component or a wiring portion is defective due to noise generated in the circuit. The purpose is to obtain a digital signal circuit with improved performance.

[0012]

According to a first aspect of the present invention, there is provided a digital signal circuit, wherein an input digital signal such as a contact signal or a non-contact signal is turned on or off, or an'H 'level or an'L' level. A first circuit that detects one of the states and outputs a detection signal; and a detection circuit that outputs the detection signal by detecting the on or off state of the digital signal or the other of the'H 'level or'L' level Abnormality determining means for determining an abnormality of the circuit to which the digital signal is input, based on the second circuit, the detection signal output from the first circuit, and the detection signal output from the second circuit. It is equipped with and.

In the digital signal circuit according to the second aspect of the present invention, the detection of one of the states of the input digital signal is blocked by the first circuit, and the detection of the one state is blocked. It is considered that the other state of the digital signal is detected because the one state of the digital signal is not detected by the first circuit, and a detection signal indicating that the other state is detected is output. The second circuit is provided.

According to a third aspect of the present invention, a digital signal circuit compares the detection signals output from the first circuit and the second circuit, respectively, and based on the comparison result, the digital signal is input to the digital signal circuit. A determination signal output circuit that outputs a determination signal indicating abnormality or normality is provided.

According to another aspect of the digital signal circuit of the present invention, the first signal is detected on condition that the determination signal output circuit does not output the determination signal indicating the abnormality of the circuit to which the digital signal is input. An output circuit for outputting a detection signal of one state of the digital signal is provided.

A digital signal circuit according to a fifth aspect of the present invention comprises an erroneous decision signal removing circuit for eliminating an erroneous decision signal output from the decision signal output circuit due to noise and indicating an abnormality.

[0017]

In the digital signal circuit according to the present invention, when an abnormality occurs in the circuit to which the digital signal is input, the relationship between the detection signal of the first circuit and the detection signal of the second circuit is changed from that in a normal state. By making them different, it is possible to discriminate a defect that has occurred in a circuit constituent element or a wiring portion of the circuit to which the digital signal is input.

According to a second aspect of the present invention, the second circuit detects the other state of the digital signal, depending on whether the first circuit detects one state of the input digital signal. , Output the detection signal of the other state,
From the relationship between the detection signal of the first circuit and the detection signal of the second circuit, it is possible to discriminate a defect that has occurred in a circuit constituent element or a wiring portion of the circuit to which the digital signal is input.

According to the third aspect of the invention, the determination signal output circuit determines whether the circuit to which the digital signal is input is abnormal or normal based on the comparison result of the detection signals output from the first circuit and the second circuit. By generating and outputting the determination signal shown, it is possible to know from the determination signal that a defect has occurred in the circuit component element or the wiring portion.

The output circuit in the invention of claim 4 outputs the detection signal of one state of the input digital signal only when there is no defect in the circuit constituent element or the wiring portion of the circuit to which the digital signal is input. An erroneous signal due to a defect that occurs in the circuit component or wiring by blocking the output of the detection signal in one state of the digital signal that is output when there is a defect in the circuit component or wiring Prevent the transmission of.

The erroneous decision signal removing circuit in the fifth aspect of the present invention removes an erroneous decision signal indicating an abnormality due to noise generated in a circuit to which a digital signal is input or a digital signal source, and thereby a circuit constituent element or a wiring. The reliability of abnormality determination by an abnormality determination signal indicating that a defect has occurred in a part is improved.

[0022]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of the digital signal circuit of this embodiment. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 17 is a current limiting resistor, 18 is a capacitor for bypassing high frequency components such as noise to the input side ground terminal 19 via the input side ground terminal 19, 20 is a first circuit,
Reference numeral 21 is a second circuit.

22 is a current limiting resistor 17 and a capacitor 1
Between the connection point with 8 and the cathode terminal of the light emitting diode of the photocoupler 23, the diode is connected in the forward direction with respect to the light emitting diode, and 24 is the input side power line 2
5, a resistor connected between the anode terminal of the light emitting diode of the photocoupler 23, 26 is a constant voltage diode connected between the anode terminal of the light emitting diode of the photocoupler 23 and the anode terminal of the light emitting diode of the photocoupler 28, Reference numeral 27 is a resistor connected between the anode terminal of the light emitting diode of the photocoupler 28 and the input side ground terminal 19.

Reference numeral 29 is a load resistance connected between the output side power supply line 30 and the collector terminal of the phototransistor of the photocoupler 23, and 31 is the first detection signal output circuit 33.
And 32 is a capacitor connected between the input terminal of the first detection signal output circuit 33 and the output side ground terminal 40. The output side ground terminal 39 for grounding the emitter terminal of the phototransistor of the photocoupler 23 and the output side ground terminal 40 are commonly connected.

Reference numeral 34 is a load resistance connected between the output side power supply line 35 and the collector terminal of the phototransistor of the photocoupler 28, and 36 is a second detection signal output circuit 38.
And 37 is a capacitor connected between the input terminal of the second detection signal output circuit 38 and the output side ground terminal 42. Reference numeral 41 is an output side ground terminal for grounding the emitter terminal of the phototransistor of the photocoupler 28. Output side ground terminal 39 and output side ground terminal 4
0, output side ground terminal 41 and output side ground terminal 42
Are commonly connected, and the output side power supply line 30 and the output side power supply line 35 are commonly connected. An abnormality determining unit 43 determines a defect that has occurred in a circuit component or a wiring portion based on the detection signals output from the first detection signal output circuit 33 and the second detection signal output circuit.

Next, the operation of this digital signal circuit will be described. First, the operation when the switch 3 is in the on state and the off state in a normal state in which there is no defect in the circuit components and the wiring section will be described.

When the switch 3 is turned on, a current flows from the input side power supply line 25 to the input side ground terminal 19 through the resistor 24, the light emitting diode of the photocoupler 23, the diode 22 and the current limiting resistor 17. Flowing. As a result, the phototransistor of the photocoupler 23 is turned on, its collector terminal drops to almost the ground level, and this'L 'level signal is supplied to the first detection signal output circuit 33 and inverted to turn on the switch 3. It is output as the'H 'level detection signal A indicating the state.

On the other hand, the voltage level applied to the cathode terminal of the constant voltage diode 26 is the same as the light emitting diode of the photocoupler 23 because the switch 3 is turned on and a current flows through the switch 3 to the input side ground terminal 19. The voltage level corresponding to the voltage drop amount in the diode 22 and the current limiting resistor 17 becomes lower than the voltage value formed by the sum of the Zener voltage of the constant voltage diode 26 and the voltage drop of the resistor 27, and the light emitting diode of the photocoupler 28. The current flowing through is zero. As a result, the phototransistor of the photocoupler 28 is turned off, and the input terminal of the second detection signal output circuit 38 is supplied with the signal of the “H” level which is the power supply voltage of the output power supply line 35 and is inverted,
It is output as the detection signal B of'L 'level. This'L 'level detection signal B indicates non-detection of the OFF state of the switch 3. Then, when the detection signal A is in the “H” level and the detection signal B is in the “L” level, it is determined that the switch 3 is in the ON state.

Next, when the switch 3 is turned off, from the input side power supply line 25 to the resistor 24, the light emitting diode of the photocoupler 23, the diode 22 and the current limiting resistor 17, the switch 3 is turned to the input side ground terminal. 1
The current flowing into 9 becomes zero. As a result, the voltage level applied to the cathode terminal of the constant voltage diode 26 rises, the constant voltage diode 26 is made conductive, and the input side ground terminal 1 passes through the light emitting diode of the photocoupler 28.
An electric current flows through 9 to turn on the phototransistor of the photocoupler 28. Therefore, the detection signal B output from the second detection signal output circuit 38 becomes the “H” level.
On the other hand, the detection signal A output from the first detection signal output circuit 33 becomes the “L” level. This'L 'level detection signal A indicates that the ON state of the switch 3 is not detected. Then, when the detection signal A is in the “L” level and the detection signal B is in the “H” level, it is determined that the switch 3 is in the off state.

Next, the operation when the switch 3 is in the on state and the off state in the state where the circuit component and the wiring portion are defective will be described. in this case,
The defective portion is the phototransistor of the photocoupler 23, which is fixed in an open state and is in a non-switchable defective state.

In such a defective state, the phototransistor of the photocoupler 23 does not conduct even if the switch 3 is turned on. Therefore, the detection signal A output from the first detection signal output circuit 33 is at the'L 'level. Further, at this time, on the input side, the switch 3 is turned on, and the input side power line 25 passes through the resistor 24, the light emitting diode of the photocoupler 23, the diode 22 and the current limiting resistor 17, and then passes through the switch 3 to the input side ground terminal 1.
The constant voltage diode 26 is in the off state because the current flows through the switch 9, and the detection signal B output from the second detection signal output circuit 38 is at the “L” level. In this way, when the detection signal A is at the “L” level and the detection signal B is also at the “L” level, that is, when the states of the detection signals A and B are the same, the abnormality determination means 43 determines that the operation is abnormal due to a circuit failure.

In addition, the defective portions are the phototransistor of the photocoupler 23 and the phototransistor of the photocoupler 28, and in the case of a defective state in which switching is not possible and fixed in the open state, the switch 3 is turned on or off. Without detection signal A and detection signal B
Since both are at the'L 'level, in this case also, the abnormality determination means 43 can recognize the abnormal operation due to the circuit failure.

In the above-described embodiment, the abnormality detecting operation for the defect that occurs in the phototransistor of the photocoupler, especially the defect that is fixed in the open state has been described. In the case of a defect in which one or both of the phototransistors are short-circuited, the detection signal A,
Since the state of B may be the same state, the abnormality determination means 43 can recognize the abnormal operation even when such a defect occurs.

Further, in the above-described embodiment, the photo-coupler 2 has not been described for all the failure occurrence modes.
If a defect occurs, it is detected when the switch 3 is in the ON state or the OFF state, except for a circuit element defect or a defect such as a disconnection or a short circuit that has occurred in the circuit portion including the light emitting diode 3 of FIG. 3, the diode 22 and the current limiting resistor 17. The signals A and B may be in the same state, and the abnormality determination means 43 can recognize the abnormality.

Example 2. FIG. 2 is a circuit diagram showing the configuration of the digital signal circuit according to the second embodiment. 2, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 51 is the first detection signal output circuit 33.
Detection signal A output from the second detection signal output circuit 3
ExO for determining the coincidence with the detection signal B output from 8
An R circuit (determination signal output circuit) 52 is an output buffer circuit.

In this embodiment, when a defect occurs in a circuit component or a wiring part, a detection signal A output from the first detection signal output circuit 33 and a detection signal output from the second detection signal output circuit 38. Since the state where B and B coincide, occurs,
The output C of the exOR circuit 51 becomes the “L” level, and this “L” level signal C can be output to the outside as an abnormality determination signal.

Example 3. FIG. 3 is a circuit diagram showing the configuration of the digital signal circuit according to the third embodiment. 3, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 61 is the first detection signal output circuit 33.
It is an AND circuit (output circuit) that performs a logical product operation of the detection signal A output from the signal and the signal C output from the exOR circuit 51.

As described in the second embodiment, when a defect occurs in a circuit component element or a wiring portion, the signal C becomes "L" level, and in a normal state where no defect occurs, it becomes "H" level. . In addition, as described in the first embodiment,
When the switch 3 is turned on, the detection signal A output from the first detection signal output circuit 33 becomes the “H” level. Therefore, the AND circuit 61 outputs an “H” level signal D indicating the ON state of the switch 3 only when there is no defect in the circuit constituent element or the wiring portion.

Embodiment 4 FIG. FIG. 4 is a circuit diagram showing the configuration of the digital signal circuit according to the fourth embodiment. 4, the same parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 71 and 72 are D flip-flops which read data supplied to the data input terminal D at the rising edge of the clock signal and output the data to the Q output terminal and the QC output terminal. 73 is reset by the falling edge of the signal output from the QC output terminal of the D flip-flop 71, and when the count value of the clock signal reaches a predetermined set value, the time-up signal is sent to the clock of the D flip-flop 72. It is a timer that outputs to the signal input terminal. The exNOR circuit 100 and D
The flip-flops 71 and 72 and the timer 73 form an erroneous determination signal removing circuit.

Next, the operation of the fourth embodiment will be described with reference to the timing charts shown in FIGS. In this embodiment, a chattering pulse generated by chattering when the switch 3 is turned on / off is prevented from being output as an abnormality determination signal. FIG. 5 is a timing chart showing waveforms of various parts when the switch 3 is switched from off to on.

When chattering occurs in the switch 3, chattering pulses due to chattering when the switch 3 is switched from OFF to ON appear in the signals A and B as shown in (b) and (c) of FIG. In the state where no defect occurs in the circuit component or the wiring portion, the signal A and the signal B which are output depending on whether the switch 3 is turned on or off originally have different polarities. As shown in (c), chattering pulses appearing in the signal A and the signal B may appear as signals of the same polarity. On the other hand, if a defect occurs in the circuit component or the wiring part, the signal C
The abnormality determination signal output as is output when the signal A and the signal B have the same polarity.
The chattering pulse having the same polarity, which appears in the signal B and the signal B, is output as the abnormal signal, which causes the error determination to be erroneous. The signal A and the signal B having the chattering pulse of the same polarity, which causes the error determination to be incorrect, are exNOR.
The coincidence determination is performed by the circuit 100, so that the signal C is converted into the waveform of the signal C shown in FIG.

The D flip-flop 71 reads this signal C at the rising edge of the clock signal and outputs it to the output terminal Q as the signal of the'H 'level shown in FIG. 5E, and also to the output terminal QC of FIG. The “L” level signal shown in (f) is output. The timer 73 counts the clock signal toward a predetermined set value by the fall of the signal of the'L 'level output from the output terminal QC of the D flip-flop 71. However, since the chattering pulse is usually shorter than the timer setting value, the signal A has a polarity different from that of the “H” level and the signal B has the “L” level before the timer times out, and the output of the signal C is It becomes'L 'level. This signal C is read from the rising edge of the clock signal and output to the output terminal Q as a signal of the'L 'level shown in FIG. 5E, and at the same time to the output terminal QC'H' shown in FIG. Output level signal. The timer 73 is reset by the rising of the "H" level signal output from the output terminal QC of the D flip-flop 71, and thereafter the clock signal is not counted in the timer reset state while this signal is "H" level. In this way, chattering below the timer set value is removed, and it is not recognized as abnormal.

At some time, a defect occurs in the circuit that outputs the signal A, and the signal A is output even though the switch 3 is on.
Assuming that is fixed to the'L 'level, both the signals A and B are at the'L' level, which causes the signal C to be at the'H 'level. This signal C is read at the rising edge of the clock signal, and the'L 'level signal shown in (f) of FIG. 5 is output to the output terminal QC. With this'L 'level output, the timer 73 counts clock signals toward a predetermined set value. Eventually, the timer outputs a time-up signal, and the D flip-flop 72 reads the signal shown in (e) of FIG. 5 output from the output terminal Q of the D flip-flop 71 at the rising edge of the time-up signal. The output terminal Q of the D flip-flop 72 outputs the signal shown in FIG. The output from the output terminal Q of the D flip-flop 72 is output as a signal C ′, and the output from the output terminal QC is subjected to a logical product operation with the signal A shown in (b) of FIG. It is output as the signal D shown in FIG.

As described above, in the digital signal circuit of this embodiment, the chattering pulse generated when the switch 3 is switched is removed to prevent the chattering pulse from being output as the abnormality determination signal.

[0045]

As described above, according to the first aspect of the present invention, the digital signal such as the input contact signal or the non-contact signal is turned on or off, or one of the'H 'level and the'L' level. And a second circuit for detecting the ON state or OFF state of the digital signal or the other of the'H 'level and the'L' level and outputting the detection signal. And the abnormality determining means for determining the abnormality of the circuit based on the detection signals output from the first circuit and the second circuit. There is an effect that a digital signal circuit capable of determining the normal state and the abnormal state of is obtained.

According to the second aspect of the present invention, the first circuit for detecting one state of the input digital signal and the interlocking operation depending on whether or not the first circuit detects the one state. And a second circuit for detecting the other state of the digital signal and outputting a detection signal of the other state, the detection signal of the first circuit and the second circuit of the second circuit are provided. From the relationship with the detection signal, there is an effect that a digital signal circuit capable of discriminating a defect that has occurred in a circuit constituent element or a wiring portion of a circuit to which the digital signal is input is obtained.

According to the third aspect of the present invention, the detection signals output from the first circuit and the second circuit are compared, and based on the comparison result, it is determined whether the circuit to which the digital signal is input is abnormal or normal. Since the determination signal output circuit that outputs the determination signal shown is provided, there is an effect that a digital signal circuit that can output a signal indicating that a defect has occurred in a circuit component or a wiring portion can be obtained.

According to the invention of claim 4, the detection signal indicating one state of the digital signal detected by the first circuit is provided on condition that the determination signal output circuit does not output the determination signal indicating abnormality. Since the output circuit for outputting is provided, it is possible to obtain a digital signal circuit capable of preventing transmission of an erroneous signal due to a defect caused in a circuit constituent element or a wiring portion.

According to the invention of claim 5, the erroneous decision signal removing circuit for preventing the erroneous decision signal indicating an abnormality from being outputted from the decision signal output circuit is provided. It is possible to prevent the judgment signal that indicates that a defect has occurred in the circuit from being erroneously generated and output due to noise that occurs in the circuit or the signal source of the input digital signal, and to improve the reliability of the abnormality judgment by the judgment signal. There is an effect that a digital signal circuit that can be improved is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a digital signal circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a digital signal circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a digital signal circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a digital signal circuit according to a fourth embodiment of the present invention.

FIG. 5 is a timing chart showing a signal waveform of each part of the erroneous determination signal removal circuit of the digital signal circuit according to the fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a conventional digital signal circuit.

[Explanation of symbols]

20 first circuit, 21 second circuit, 43 abnormality determination means, 51 exOR circuit (determination signal output circuit, erroneous determination signal removal circuit), 61 AND circuit (output circuit), 7
1, 72 D flip-flop (erroneous decision signal removing circuit), 73 timer (erroneous decision signal removing circuit).

Claims (5)

[Claims] 1. A first signal for detecting an ON or OFF state of a digital signal such as an input contact signal or a non-contact signal, or a state of one of'H 'level and'L' level and outputting a detection signal. A circuit, a second circuit for detecting the on or off state of the digital signal, or the other of the'H 'level and the'L' level and outputting a detection signal, and the first circuit. A digital signal circuit comprising an abnormality determining means for determining abnormality of the circuit to which the digital signal is input, based on the detection signal and the detection signal output from the second circuit. 2. The second circuit prevents detection of the one state of the input digital signal by the first circuit detecting the one state of the input digital signal, and the second circuit receives the input state of the digital signal. 2. A detection signal of the other state is output on the condition that one state of the digital signal is not detected by the first circuit, and a detection signal of the other state is output. The described digital signal circuit. 3. The abnormality determining means compares the detection signals output from the first circuit and the second circuit, and based on the comparison result, the abnormality of the circuit to which the digital signal is input. 3. The digital signal circuit according to claim 1 or 2, further comprising a determination signal output circuit that outputs a determination signal indicating time or normal time. 4. One state of the digital signal detected by the first circuit, provided that the determination signal output circuit does not output a determination signal indicating an abnormality of the circuit to which the digital signal is input. 4. The digital signal circuit according to claim 3, further comprising an output circuit for outputting the detection signal of. 5. The digital signal circuit according to claim 4, further comprising an erroneous determination signal removing circuit for removing an erroneous determination signal indicating an abnormality output from the determination signal output circuit due to noise.