JP2814176B2 - Semiconductor wafer splitting method - Google Patents
Semiconductor wafer splitting methodInfo
- Publication number
- JP2814176B2 JP2814176B2 JP5027115A JP2711593A JP2814176B2 JP 2814176 B2 JP2814176 B2 JP 2814176B2 JP 5027115 A JP5027115 A JP 5027115A JP 2711593 A JP2711593 A JP 2711593A JP 2814176 B2 JP2814176 B2 JP 2814176B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- chip
- back surface
- polishing
- dicing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体ウェーハの分割
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for dividing a semiconductor wafer.
【0002】[0002]
【従来の技術】従来、薄くて小さいチップを形成するに
は半導体ウェーハのダイシングに先立って裏面を研磨
し、所定の厚さになるまで研磨した後に半導体ウェーハ
をダイシングしてチップに分割していた。ところが、こ
の方法だと直径150mm、200mm等の大型の半導
体ウェーハの場合、例えば300μm程度に薄く研磨し
て仕上げると研磨後に破損、欠け等の損傷が生じ易くな
って取り扱いが難しくなる。又、半導体ウェーハをダイ
シングすると、裏面チッピングが生じるという難点もあ
る。2. Description of the Related Art Conventionally, in order to form a thin and small chip, the back surface is polished prior to dicing of a semiconductor wafer, polished to a predetermined thickness, and then the semiconductor wafer is diced and divided into chips. . However, according to this method, in the case of a large-sized semiconductor wafer having a diameter of 150 mm, 200 mm or the like, if it is polished and finished to a thickness of, for example, about 300 μm, damage such as breakage or chipping is likely to occur after polishing, and handling becomes difficult. Further, there is also a disadvantage that backside chipping occurs when dicing a semiconductor wafer.
【0003】[0003]
【発明が解決しようとする課題】本発明は、このような
従来の問題を解決するためになされ、特に大型の半導体
ウェーハであっても損傷なく、薄くて小さいチップを形
成でき、しかも裏面チッピングも解消できるようにした
半導体ウェーハの分割方法を提供することを課題とす
る。SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem. In particular, a thin and small chip can be formed without damaging even a large semiconductor wafer, and backside chipping can be achieved. An object of the present invention is to provide a method for dividing a semiconductor wafer which can be eliminated.
【0004】[0004]
【課題を解決するための手段】この課題を技術的に解決
するための手段として、本発明は、半導体ウェーハをチ
ップに分割する方法であって、半導体ウェーハの裏面を
研磨するに先立ち、半導体ウェーハをダイシングする工
程と、ダイシングによって分割されたチップを収納する
基板の収納孔に、裏面を上にして該チップを収納する工
程と、該基板に固定されたチップの裏面を研磨する工程
と、から構成される半導体ウェーハの分割方法を要旨と
する。SUMMARY OF THE INVENTION As a means for technically solving this problem, the present invention is a method for dividing a semiconductor wafer into chips, wherein the semiconductor wafer is polished prior to polishing the back surface of the semiconductor wafer. Dicing, and a step of storing the chip with the back side up in a storage hole of a substrate that stores the chip divided by dicing, and a step of polishing the back surface of the chip fixed to the substrate. The gist is a method of dividing a semiconductor wafer to be configured.
【0005】[0005]
【作 用】半導体ウェーハを先にダイシングし、そのダ
イシングにより分割された半導体ウェーハの裏面を研磨
する、つまりチップにしてからその裏面を薄く研磨する
ので大型の半導体ウェーハのまま裏面を研磨する必要が
なくなると共に、ダイシングによって生じる裏面チッピ
ングを研磨により除去することができる。[Operation] A semiconductor wafer is diced first and the back surface of the semiconductor wafer divided by the dicing is polished. In other words, since the back surface is thinly polished into chips, it is necessary to polish the back surface of a large semiconductor wafer. At the same time, backside chipping caused by dicing can be removed by polishing.
【0006】[0006]
【実施例】以下、本発明の実施例を添付図面に基づいて
詳説する。図1において、1はチャックテーブルであ
り、ダイシングにより分割された半導体ウェーハ2がフ
レーム3を介して固定されている。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a chuck table on which a semiconductor wafer 2 divided by dicing is fixed via a frame 3.
【0007】前記半導体ウェーハ2は、図2に示すよう
に公知のダイシング装置(例えば特公平3−11601
号公報)等で予めダイシングされてチップ4に分割され
ており、これらのチップ4はダイシング後に裏面4aを
上にして前記フレーム3の粘着テープ5に貼着されてい
る。As shown in FIG. 2, the semiconductor wafer 2 is placed in a known dicing apparatus (for example, Japanese Patent Publication No. 3-11601).
No. 2, pp. 157-334, etc., the chips 4 are divided into chips 4 in advance, and these chips 4 are attached to the adhesive tape 5 of the frame 3 with the back surface 4a facing up after dicing.
【0008】6は研磨砥石であり、前記チャックテーブ
ル1上にフレーム3を介して固定された半導体ウェーハ
2即ちチップ4の裏面4aを研磨できるようにしてあ
る。このような研磨砥石6及びチャックテーブル1を含
む研磨装置7としては、例えば特公昭64−3620号
公報に記載のもの等を使用することができる。Reference numeral 6 denotes a polishing grindstone which can polish the back surface 4a of the semiconductor wafer 2, that is, the chip 4 fixed on the chuck table 1 via the frame 3. As the polishing apparatus 7 including such a polishing grindstone 6 and the chuck table 1, for example, the one described in Japanese Patent Publication No. 64-3620 can be used.
【0009】このようにして、半導体ウェーハ2を先に
ダイシング工程によってチップ4に分割し、ダイシング
後にこれらのチップ4を裏面4aを上にして前記のよう
にフレーム3の粘着テープ5上に貼着し、そのフレーム
3を研磨装置7のチャックテーブル1上に固定し、研磨
砥石6でチップ4の裏面4aを研磨する研磨工程を遂行
する。In this manner, the semiconductor wafer 2 is first divided into chips 4 by a dicing step, and after dicing, these chips 4 are attached to the adhesive tape 5 of the frame 3 with the back surface 4a facing upward as described above. Then, the frame 3 is fixed on the chuck table 1 of the polishing device 7, and a polishing step of polishing the back surface 4 a of the chip 4 with the polishing stone 6 is performed.
【0010】先にダイシング工程で半導体ウェーハ2を
ダイシングすると、通常図3に示すようにチップ4の裏
面4aの周囲にはチッピング4bが発生するが、後の研
磨工程においてチップ4の裏面4aが研磨されるため、
図4に示すように研磨されたチップ4′はチッピングが
綺麗に削り取られて消滅し、裏面チッピングの問題が解
消する。When the semiconductor wafer 2 is diced first in the dicing step, chipping 4b usually occurs around the back surface 4a of the chip 4 as shown in FIG. 3, but the back surface 4a of the chip 4 is polished in a subsequent polishing step. To be
As shown in FIG. 4, the chip 4 'which has been polished is wiped off so that the chipping is sharply removed and the chipping problem is solved.
【0011】又、従来のように薄く研磨した大型の半導
体ウェーハを取り扱う必要がないので、半導体ウェーハ
が破損したり欠けたりする等の損傷を未然に防止するこ
とができる。Further, since it is not necessary to handle a large-sized semiconductor wafer which has been thinly polished as in the prior art, damage such as breakage or chipping of the semiconductor wafer can be prevented.
【0012】ダイシング後に裏面を上にしてチップを貼
り替える作業は、例えばダイシング後のフレームに別途
新しいフレームを被せてその粘着テープに、分割された
半導体ウェーハ(ダイシングされたチップ全部)を貼着
し、先に貼着されていたフレームの粘着テープを剥がせ
ば各チップの裏面が上になった状態で新フレームに簡単
に貼り替えることが可能である。ダイシング後のウェー
ハ即ちチップの裏面を研磨するには1つ1つ個別に行っ
ても良いが、生産性を高めるために複数個のチップを同
時に研磨するのが好ましい。[0012] After the dicing, the operation of replacing the chip with the back side facing upward is performed, for example, by separately placing a new frame on the frame after the dicing, and sticking the divided semiconductor wafers (all the diced chips) to the adhesive tape. If the adhesive tape of the previously attached frame is peeled off, it is possible to easily replace the chip with a new frame with the back surface of each chip facing upward. The back surface of the wafer after dicing, that is, the chip, may be polished individually one by one, but it is preferable to simultaneously polish a plurality of chips in order to increase productivity.
【0013】チップの貼り替え作業は適当な治具を用い
て行うことも可能であり、例えば図5はその一例を示す
もので、基板8の上面にチップ4を嵌め込むための収納
孔8aが所定の間隔をあけて多数並設され、各収納孔8
aの底面には図6に示すように複数の吸引孔8bが基板
8の底面に貫通させて並設されており、これらの吸引孔
8bはチャックテーブル1の吸引孔(図略)に連通させ
た構成にしてある。従って、各収納孔8aにダイシング
後のチップ4をその裏面4aを上にして嵌め込むと共
に、チャックテーブル1の吸引孔及び基板8の吸引孔8
bを介して吸引すると、チップ4を固定することができ
る。この際、固定されたチップ4は研磨工程のために基
板8の上面より突出するようにする。又、更に固定力を
高めるためにチップを基板8に水等で凍結固定しても良
い。The chip replacement operation can be performed by using an appropriate jig. For example, FIG. 5 shows an example of such a case, in which a storage hole 8a for fitting the chip 4 to the upper surface of the substrate 8 is provided. A large number of them are arranged side by side at predetermined intervals,
As shown in FIG. 6, a plurality of suction holes 8b penetrate the bottom surface of the substrate 8 and are juxtaposed on the bottom surface of the substrate a. These suction holes 8b communicate with suction holes (not shown) of the chuck table 1. Configuration. Therefore, the diced chip 4 is fitted into each of the storage holes 8a with its back surface 4a facing upward, and the suction holes of the chuck table 1 and the suction holes 8 of the substrate 8 are formed.
By suction through b, the chip 4 can be fixed. At this time, the fixed chip 4 is made to protrude from the upper surface of the substrate 8 for a polishing process. Further, the chip may be frozen and fixed to the substrate 8 with water or the like in order to further increase the fixing force.
【0014】このようにして治具9を用いてチップ4を
固定した後、前記と同様に研磨砥石6で研磨工程を遂行
し、チップ4の裏面4aを研磨し所定の厚さに仕上げる
ことができる。After the chip 4 is fixed by using the jig 9 in this manner, a polishing process is performed by the polishing grindstone 6 in the same manner as described above, and the back surface 4a of the chip 4 is polished and finished to a predetermined thickness. it can.
【0015】[0015]
【発明の効果】以上説明したように、本発明によれば、
半導体ウェーハを先にダイシングして各チップに分割し
た後、そのチップの裏面を上にして研磨するようにした
ので、大型の半導体ウェーハを薄く研磨した後にダイシ
ングする必要がなくなり、半導体ウェーハの破損や欠け
等の損傷を未然に防止すると共に、チップの裏面チッピ
ングを防止できる等の優れた効果を奏する。As described above, according to the present invention,
Since the semiconductor wafer is first diced and divided into chips, and then polished with the back side of the chip facing up, there is no need to dice after polishing a large semiconductor wafer thinly. Excellent effects such as prevention of damage such as chipping can be prevented and chip backside chipping can be prevented.
【図1】 本発明の一実施例を示す研磨工程の説明図で
ある。FIG. 1 is an explanatory view of a polishing step showing one embodiment of the present invention.
【図2】 半導体ウェーハのダイシング後フレームの粘
着テープに貼着された状態を示す平面図である。FIG. 2 is a plan view showing a state where the semiconductor wafer is attached to an adhesive tape of a frame after dicing.
【図3】 ダイシング後チップの裏面にチッピングが生
じた状態を示す斜視図である。FIG. 3 is a perspective view showing a state in which chipping has occurred on the back surface of the chip after dicing.
【図4】 チップの裏面を研磨してチッピングが消滅し
た状態を示す斜視図である。FIG. 4 is a perspective view showing a state where chipping has disappeared by polishing the back surface of the chip.
【図5】 チップを固定するための治具の実施例を示す
斜視図である。FIG. 5 is a perspective view showing an embodiment of a jig for fixing a chip.
【図6】 その治具の使用状態を示す説明図である。FIG. 6 is an explanatory diagram showing a use state of the jig.
1…チャックテーブル 2…半導体ウェーハ 3…
フレーム 4…チップ 4a…裏面 4b…チッ
ピング 5…粘着テープ 6…研磨砥石 7…研磨装置 8…基板 8a…収納孔 8b…
吸引孔 9…治具1. Chuck table 2. Semiconductor wafer 3.
Frame 4 Chip 4a Back surface 4b Chipping 5 Adhesive tape 6 Polishing grindstone 7 Polishing device 8 Substrate 8a Storage hole 8b
Suction hole 9 ... Jig
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/78 H01L 21/304──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/78 H01L 21/304
Claims (1)
あって、半導体ウェーハの裏面を研磨するに先立ち、半
導体ウェーハをダイシングする工程と、 ダイシングによって分割されたチップを収納する基板の
収納孔に、裏面を上にして該チップを収納する工程と、 該基板に固定されたチップの裏面を研磨する工程と、 から構成される半導体ウェーハの分割方法。1. A method for dividing a semiconductor wafer into chips, comprising: a step of dicing the semiconductor wafer prior to polishing the back surface of the semiconductor wafer; and a step of: A method for dividing a semiconductor wafer, comprising: a step of housing the chip with the back surface facing upward; and a step of polishing the back surface of the chip fixed to the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5027115A JP2814176B2 (en) | 1993-01-25 | 1993-01-25 | Semiconductor wafer splitting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5027115A JP2814176B2 (en) | 1993-01-25 | 1993-01-25 | Semiconductor wafer splitting method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06224299A JPH06224299A (en) | 1994-08-12 |
JP2814176B2 true JP2814176B2 (en) | 1998-10-22 |
Family
ID=12212075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5027115A Expired - Lifetime JP2814176B2 (en) | 1993-01-25 | 1993-01-25 | Semiconductor wafer splitting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2814176B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4615095B2 (en) * | 2000-06-08 | 2011-01-19 | 株式会社ディスコ | Chip grinding method |
CN111571413B (en) * | 2020-06-02 | 2021-04-27 | 重庆水利电力职业技术学院 | Automatic burnishing device of ornamental material processing usefulness |
CN113471069A (en) * | 2021-05-10 | 2021-10-01 | 中国电子科技集团公司第十一研究所 | Infrared detector, hybrid chip and back thinning scratch processing method thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5552235A (en) * | 1978-10-13 | 1980-04-16 | Toshiba Corp | Fastening of semiconductor wafer on substrate |
JPS63117445A (en) * | 1986-11-05 | 1988-05-21 | Citizen Watch Co Ltd | Processing of semiconductor wafer |
JPS63261851A (en) * | 1987-04-20 | 1988-10-28 | Nec Corp | Manufacture of semiconductor element |
-
1993
- 1993-01-25 JP JP5027115A patent/JP2814176B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH06224299A (en) | 1994-08-12 |
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