JP2812067B2 - Waveform equalizing circuit and magnetic storage device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform equalizing circuit, and more particularly to a waveform equalizing circuit used for a reproducing circuit of a magnetic storage device having a thin film head.

[0002]

2. Description of the Related Art A conventional waveform equalizing circuit used in a reproducing circuit of a magnetic storage device having a thin film head has a delay circuit like a delay circuit A in FIG. 6 and a delay circuit D in FIG. In addition, the main signal and a correction signal having a different signal level by shifting the timing by a predetermined delay time by these delay circuits are configured to be added or subtracted, thereby eliminating the undershoot of the main signal.

The waveform equalizing circuit shown in FIG. 6 uses a reflection type, and FIG. 8 shows a signal waveform of each part. A slimming signal B108 and an undershoot correction signal J118, which are correction signals whose delay time is different from that of the pre-equalization read signal B101 which is a main signal and whose level is reduced by an attenuator, are J118.
Is added and subtracted to output a post-equalization signal 119.

The waveform equalizing circuit shown in FIG. 7 uses a transmission type, and FIG. 9 shows signal waveforms at various parts. A slimming signal B2, 129, a slimming signal B3, 130, a slimming signal B3, 130, an undershoot correction signal B2, 131, and an undershoot, which are delay signals having different delay times from the main signal, ie, the pre-equalization read signal B101, whose levels have been reduced by an attenuator An equalized signal 119 is output by adding and subtracting the correction signal B3 · 132.

[0005]

However, as described above, in the circuit of FIG. 6 of the waveform equalizing circuit of the reproducing circuit of the conventional magnetic storage device, as shown in FIG. When there is a difference, it is possible that one is optimally corrected while the other is not optimally corrected or deteriorated. Therefore, Tr and T
There is a disadvantage that only a thin film head having a small difference from f can perform the optimum correction.

In the waveform equalizing circuit shown in FIG. 7, even when Tr and Tf are different from each other, correction can be made by appropriately selecting the delay time. However, the characteristic of the delay circuit D is the same as that of the delay circuit A. However, there is a drawback that a delay circuit having a delay time about twice as long is required, so that the shape of the delay circuit becomes large and the price becomes high.

[0007]

According to a first aspect of the present invention, there is provided a waveform equalizing circuit used for a reproducing circuit of a magnetic storage device having a thin film head, wherein a waveform obtained by inputting an output signal of the reproducing circuit and delaying the signal by a predetermined time is provided. A first delay circuit that outputs a pre-equalization read signal, a slimming signal that is a reflection signal of the pre-equalization waveform read signal, and a plurality of undershoot correction signals having different delay times, and inputs the waveform slimming signal. A first attenuator for changing and outputting the level of the signal, the waveform equalization pre-reading signal and the output signal of the first attenuator being input, and the first signal from the waveform pre-equalization readout signal.
A subtractor for subtracting the output signal of the attenuator to output a signal after slimming and equalizing, and a second delay for receiving the signal after slimming and equalizing and outputting a plurality of slimming and equalized signals delayed by a predetermined time Circuit, the plurality of delayed slimming-equalized signals and a delayed signal input to the second delay circuit.
A first selector for selecting and outputting one of the post-slimming equalized signals , a second selector for selecting and outputting one of the plurality of undershoot correction signals, A third delay circuit that inputs the undershoot correction signal selected by the selector and outputs a plurality of undershoot correction signals delayed by a predetermined time; a plurality of delayed undershoot correction signals ;
Undelayed undershoot input to the delay circuit
A third selector for selecting and outputting one of the correction signals, a second attenuator for inputting the undershoot correction signal selected by the third selector, changing the level of the signal, and outputting the changed signal. An adder for adding a post-slimming equalized signal output from the first selector and an undershoot correction signal output from the second attenuator and changing the level, and outputting a post-equalized signal; A control circuit for inputting a control signal and outputting a switching signal for switching output signals of the first selector, the second selector, and the third selector.

According to a second invention, in the waveform equalization circuit according to the first invention, the third delay circuit and the third selector are eliminated, and the second attenuator is replaced by the second selector. The undershoot correction signal to be selected is inputted.

A third invention is the waveform equalizer of the first invention, the reduced adder and the second delay circuit and the first
And a readout signal before waveform equalization output from the first delay circuit, a waveform slimming signal obtained by changing a level of a signal output from the first attenuator, and a second slimming signal. And an adder / subtractor for adding and subtracting an undershoot correction signal obtained by changing the level of a signal output from the output unit and outputting a signal after the equal change.

A fourth invention is characterized in that the control circuit comprises a read-only storage circuit (ROM).

According to a fifth aspect of the present invention, there is provided a magnetic storage device using the waveform equalizing circuit according to any one of the first to fourth aspects, wherein the control circuit determines in advance a characteristic of a reproduced output waveform as a characteristic of the thin film head. The position of an undershoot is stored, and when the control signal is input from the upper circuit to the control circuit, the control circuit outputs a predetermined switching signal based on characteristics of the thin film head to switch the sectors. It is characterized by doing.

A sixth aspect of the present invention is characterized in that the characteristic of the thin film head is a difference between a first half position Tf and a second half position Tr of the undershoot of the reproduced output waveform.

According to a seventh aspect of the present invention, there is provided a thin film head having the Tf side larger than the Tr, and the waveform equalizing circuit of the second aspect.

An eighth invention comprises a thin film head whose Tr side is larger than Tf, and the waveform equalization circuit of the third invention.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing signal waveforms at various parts in FIG.

The delay circuit A1 includes a read signal A1 before equalization.
00 as an input, outputs the pre-equalization read signal B101 to the subtractor A7, and outputs the waveform slimming signal A102 to the attenuator A.
9 to the subtractor A7, and outputs the undershoot correction signals A103, B104, C105, D106, E10
7 to the selector A4. The subtractor A7 receives the pre-equalization read signal B101 and the slimming signal B108, and converts the pre-equalization read signal B101 to the slimming signal B10.
The slimming-equalized signal A109 obtained by subtracting 8 is output to the delay circuit C3 and the selector C6.

The delay circuit C3 outputs the slimming-equalized signal A1.
09, and inputs the slimming-equalized signals B110 and C1.
11 to the selector C6. The selector C6 selects the input slimming-equalized signals A109, B110, and C111 based on the input selector C switching signal 123, and outputs the slimming-equalized signal D112 to the adder B8. The selector A4 receives the input selector A switching signal 12
1, the undershoot correction signals A103, B10
4, C105, D106, and E107, and outputs the undershoot correction signal F114 to the delay circuit B2 and the selector B.
5 and output.

The delay circuit B2 receives the undershoot correction signal F114 as an input and the undershoot correction signal G11.
5, H116 are output to the selector B5. Selector B5
Are input undershoot correction signals F114, G115, and H11 by an input selector B switching signal 122.
6 and outputs an undershoot correction signal I117 to the adder B8 via the attenuator B10 and an undershoot correction signal J118 to the adder B8.

The adder B8 adds the input slimming equalized signal D112 and the undershoot correction signal J118 and outputs an equalized signal 119 to a data detector (not shown). The control circuit (ROM) 13 receives a control signal A120
To output the selector A switching signal 121 to the selector A4, the selector B switching signal 122 to the selector B5, and the selector C switching signal 123 to the selector C6.

Next, the operation of the present invention will be described.

The pre-equalization read signal A100 shown in FIG.
Is obtained by amplifying an output from a magnetic head of a magnetic storage device to an appropriate amplitude using an amplifier. 2 and 3, an isolated waveform is used for describing the waveform equalizing circuit of the present invention. Further, in a read output using a thin film head as a magnetic head, undershoots occur on both sides of a solitary wave. Here, the front side of the solitary wave is Tf and the rear side is Tf.
r (FIGS. 1 and 2). The present invention relates to a waveform equalizing circuit for correcting this undershoot,
This is a waveform equalizing circuit in the case where the magnitudes of Tf and Tf are different.

Since the delay circuit A1 has no terminating resistor, the pre-equalization read signal A100 is totally reflected, and a reflected signal corresponding to a predetermined time of the delay circuit A1 is a slimming signal A102 and an undershoot correction signal A103, B1
04, C105, D106, and E107. The pre-equalization read signal B101 is the pre-equalization read signal A10.
This is a signal obtained by delaying 0 by a predetermined time, and is input to one input terminal of the subtractor A7. The slimming signal B
108 is a slimming signal A102 attenuated to an appropriate size (to minimize the bit shift) by the attenuator A9.
And is input to the other input terminal of the subtractor A7.

The subtractor A7 outputs a pre-equalization read signal B101.
Is subtracted from the slimming signal B108 to obtain a slimming-equalized signal A109 having a compressed time width.
This is a conventional cosine equalization method. Then, the equalized signal A
109 is output to the delay circuit C3 and the selector C6, respectively. Since the delay circuit C3 is terminated by the resistor B12 having the same resistance value as the internal resistance of the delay circuit, the input slimming-equalized signal A109 is delayed by a predetermined time to obtain the slimming-equalized signals B110 and C111 as sectors. C6
Output to The selector C6 receives the selector C switching signal 1
23, the signals A109 and B1 after the input slimming equalization.
10, and outputs a post-slimming-equalized signal D112 in which only one signal is selected from C111 to the adder B8.

On the other hand, the selector A4 receives the input undershoot correction signal A by the selector A switching signal 121.
103, B104, C105, D106, and E107 are selected so that the delay amount is equal to the time of the undershoot. This time refers to the pre-equalization read signal B101 and the undershoot correction signal
The difference from the delay time of 103, B104, C105, 2, 106, and E107 is exactly (Tr + Tf) / 2. Also, undershoot correction signals A103, B
104, C105, D106 and E107 are delay circuits A1
2 is also output, so that the waveform has two peaks at an interval of (Tf + Tr) as shown in FIG.

The undershoot correction signal F114 output from the selector A4 is output to the delay circuit B2 and the selector B5. The delay circuit B2 outputs the same to the delay circuit B2 and the selector B5 as the internal resistance of the delay circuit. Delay circuit B2
Is terminated by the resistor A11 having the same resistance value as the internal resistance of the delay circuit.
The undershoot correction signals G115 and H116 which are obtained by delaying 114 by a predetermined time are output to the selector B5. The selector B5 receives the input undershoot correction signals F114, G115, and H1 according to the selector B switching signal 122.
An undershoot correction signal I117 in which only one signal is selected from 16 is output. The undershoot correction signal I117 is attenuated by the attenuator B10 to an appropriate level (optimizing the correction) and output to the adder B8 as the undershoot correction signal J118. The adder B8 adds the input slimming equalized signal D112 and the undershoot correction signal J118 to correct the undershoot, and outputs an equalized signal 119.

Here, the operation of the selectors B5 and C6 will be described.

First, as shown in FIG. 2, when Tf is large between the undershoot positions Tf and Tr, the selector B5 selects an undelayed undershoot correction signal F114 from among the inputs to select the undershoot correction signal F114. A shoot correction signal I117 is output. The selector C6 selects from the output of the delay circuit C3 a time-delayed signal of the slimming-equalized signal A109 (Tf-Tr) / 2 from among the inputs.
Output as a signal D112 after slimming equalization. By selecting the selector B5 and the selector C6 in this way, the position of the undershoot of the slimming-equalized signal D112 matches the position of the undershoot correction signal J118. This is the optimal correction.

Next, as shown in FIG. 3, when Tr among the undershoot positions Tf and Tr is larger, the selector C6 selects the undelayed slimming-equalized signal A109 from the inputs. Signal D1 after slimming equalization
12 is output. The selector B5 selects a signal obtained by delaying the undershoot correction signal F114 by (Tr-Tf) / 2 from the output of the delay circuit B2, and outputs the selected signal as the undershoot correction signal I117. By selecting the selector B5 and the selector C6 in this manner, the position of the undershoot of the slimming equalized signal D112 matches the position of the undershoot correction signal J118. Is the optimal correction.

The undershoot positions Tf and Tr
Are equal, the selector B5 and the selector C6 output the undershoot correction signal F which is not delayed from the input.
114 and the slimming-equalized signal A109,
An undershoot correction signal I117 and a slimming-equalized signal D112 are output. This is similar to the conventional method.

The control circuit 13 is provided to cope with the difference in the size of the undershoot position Tf and Tr due to the position of the magnetic head and the cylinder, and the difference in the difference between Tr and Tf due to the magnetic head. , The input control signal A12
0 (for example, head address, cylinder address), selectors A 4, B 5, and selector C switching signal 123 output selector A switching signal 121, selector B switching signal 122, and selector C switching signal 123 so that correction is always optimal.
Switch C6. Thus, optimum correction can be performed even when the size of the undershoot position Tf is different from the size of Tr.

The control circuit 13 may be a read-only storage circuit (ROM).

When Tf is larger than Tf and Tr, the selector B5 selects the undelayed undershoot correction signal F114.
2, the selector B5 and the resistor A11 can be omitted, resulting in a block diagram as shown in FIG. Similarly, when Tr is large, the delay circuit C3, the selector C6, and the resistor B12 can be omitted, resulting in a block diagram as shown in FIG. At this time, the heads Tf and Tr used in the magnetic storage device are selected in advance according to the magnitude of the heads, and the respective circuits can be selectively used. This is to reduce signal degradation by simplifying the circuit configuration. In particular, in the block diagram shown in FIG. 5, since the number of circuits through which the pre-equalization read signal serving as the main signal passes is small, signal deterioration due to the circuits is small. Further, since Tf and Tr are determined by the thickness of the magnetic pole of the magnetic circuit when manufacturing the thin film head, Tr is always made to be large including the variation, and the Tf and Tr are made by using the circuit shown in FIG. Is also good.

[0034]

As described above, the waveform equalizing circuit according to the present invention corrects the output signal of the magnetic head so as to obtain the optimum compensation state even when there is a difference between the position Tf of the undershoot and Tr. Thus, there is an effect that the margin of operation of the reproducing circuit is increased and a stable operation can be performed. Further, there is an effect that the use yield of the magnetic head can be improved.

Further, since the waveform equalization circuit of the present invention uses a reflection type, a delay circuit having half the delay time of the conventional waveform equalization circuit for performing the same correction can be used. Can be configured. Further, compared to the conventional reflection type waveform equalization circuit, the delay time of the added delay circuit is Tr and T
A half of the difference of f, that is, a delay time of | (Tf−Tr) / 2 | is sufficient, and signal deterioration by a circuit is small.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms of respective units in the embodiment of FIG.

FIG. 3 is a diagram showing signal waveforms at various parts in the embodiment of FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional waveform equalization circuit.

FIG. 7 is a block diagram showing another conventional waveform equalization circuit.

8 is a diagram showing signal waveforms at various parts in the conventional example of FIG.

9 is a diagram showing signal waveforms at various parts in the conventional example of FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 delay circuit A 2 delay circuit B 3 delay circuit C 4 selector A 5 selector B 6 selector C 7 subtractor A 8 adder B 9 attenuator A 10 attenuator B 11 resistor A 12 resistor B 13 control circuit (ROM ) 14 adder / subtracter C 15 delay circuit D 16 adder / subtractor D 17 attenuator C 18 attenuator D 19 attenuator E 20 attenuator F 100 read signal before equalization A 101 read signal before equalization B 102 slimming signal A 103 undershoot Correction signal A 104 Undershoot correction signal B 105 Undershoot correction signal C 106 Undershoot correction signal D 107 Undershoot correction signal E 108 Slimming signal B 109 Signal after slimming equalization A 110 Signal after slimming equalization B111 After slimming equalization Signal C 112 Slimming equalized signal D 11 Undershoot correction signal F 115 Undershoot correction signal G 116 Undershoot correction signal H 117 Undershoot correction signal I 118 Undershoot correction signal J 119 Equalized signal 120 Control signal A 121 Selector A switching signal 122 Selector B switching signal 123 Selector C switching signal 124 Slimming signal A2 126 Slimming signal A3 127 Undershoot correction signal A2 128 Undershoot correction signal A3 129 Slimming signal B2 130 Slimming signal B3 131 Undershoot correction signal B2 132 Undershoot correction signal B3

Claims (8)

(57) [Claims] 1. A waveform equalization circuit used in a reproduction circuit of a magnetic storage device equipped with a thin film head, comprising: a read signal before waveform equalization, which receives an output signal of the reproduction circuit and is delayed by a predetermined time; A first delay circuit for outputting a slimming signal, which is a reflection signal of the previous readout signal, and a plurality of undershoot correction signals having different delay times, and a second delay circuit for receiving the waveform slimming signal, changing the level of the signal and outputting the signal 1 attenuator, the readout signal before waveform equalization and the output signal of the first attenuator, and subtracts the output signal of the first attenuator from the readout signal before waveform equalization to perform slimming or the like. A subtractor that outputs the post-slimming signal; a second delay circuit that receives the post-slimming equalization signal and outputs a plurality of post-slimming post-slimming signals; Equalization signal and the second delay time
A first selector for selecting and outputting one of the slimming-equalized signals that are not delayed and input to the path, and a second selector for selecting and outputting one of the plurality of undershoot correction signals. A selector, a third delay circuit that receives the undershoot correction signal selected by the second selector and outputs a plurality of undershoot correction signals delayed by a predetermined time, and a plurality of the delayed undershoot correction signals . The delay input to the third delay circuit
A third selector that selects and outputs one of the undershoot correction signals that are not output, and a second selector that inputs the undershoot correction signal selected by the third selector, changes the level of the signal, and outputs the changed signal. And the first attenuator.
And the second signal output from the selector
An adder that outputs an equalized signal by adding the undershoot correction signal having the changed level and output by the attenuator,
A waveform equalizing circuit, comprising: a control circuit that receives a control signal from an upper circuit and outputs a switching signal for switching output signals of the first selector, the second selector, and the third selector. 2. The waveform equalizer according to claim 1, wherein:
Removing the third delay circuit and the third selector,
The waveform equalizer circuit, wherein the second attenuator receives the undershoot correction signal selected by the second selector. 3. The waveform equalizer according to claim 1, wherein
Remove and said and said and said decrease adder second delay circuit first selector, said a read signal before the waveform equalization first delay circuit outputs a signal of the first attenuator output And an adder-subtracter for adding and subtracting an undershoot correction signal obtained by changing the level of the signal output from the second attenuator and outputting an equal-changed signal. Equalization circuit. 4. The waveform equalizing circuit according to claim 1, wherein said control circuit comprises a read-only storage circuit (ROM). 5. A magnetic storage device using the waveform equalization circuit according to claim 1, wherein the control circuit determines in advance a position of an undershoot of a reproduction output waveform as a characteristic of the thin film head. And when the control signal is input from the higher-level circuit to the control circuit, the control circuit outputs a predetermined switching signal based on characteristics of the thin-film head to switch the sectors. Magnetic storage device. 6. The characteristics of the thin film head include a first half position Tf and a second half position Tf of undershoot of the reproduced output waveform.
6. The magnetic storage device according to claim 5, wherein the difference is r. 7. A magnetic memory device comprising: a thin film head having a Tf side larger than the Tr; and the waveform equalizing circuit according to claim 2. 8. A magnetic storage device comprising: a thin-film head whose Tr side is larger than Tf; and the waveform equalizing circuit according to claim 3.