JPH0737212A - Wave form equalizing circuit and magnetic storage device using the same - Google Patents

Abstract

PURPOSE:To perform an optimum correction even when a difference is present between the front half position and the rear half position of an undershoot in the undershoot correction in a magnetic storage device using a thin film head. CONSTITUTION:A delay circuit A1 delays a read-out signal before equalization A100 being an input signal by a prescribed time and reflected waves from outputs are present in respective signals 102 to 107. Next, a signal after slimming equalization A109 is obtained by excuting the subtraction between a slimming signal B108 and a read-out signal before equalization B101. Then, the correction of the undershoot is performed by adding an undershoot correction signal F114 selected from undershoot correcting signals A103, B104..., E107 and the signal after slimming equalization A109, however, the optimum correction can not be performed since the deviation of a balance is generatred when the difference is present between positions of the front and the rear of the undershoot. For that reason, the balance is adjusted in accordance with a large difference between the front half position Tf and the rear half position Tr of the undershoot with a delay circuit C3 and a delay circuit B2 so that the correction becomes optimum.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform equalizer circuit, and more particularly to a waveform equalizer circuit used in a reproducing circuit of a magnetic storage device equipped with a thin film head.

[0002]

2. Description of the Related Art A waveform equalizing circuit used in a reproducing circuit of a conventional magnetic memory device having a thin film head has a delay circuit such as delay circuit A in FIG. 6 and delay circuit D in FIG. Therefore, the main signal and the correction signal whose signal level is different by shifting the timing by a predetermined delay time by these delay circuits are added and subtracted, and the undershoot of the main signal is eliminated.

The waveform equalizing circuit shown in FIG. 6 is of a reflection type, and FIG. 8 shows the signal waveform of each part. The delay time is different from the pre-equalization read-out signal B101 which is the main signal, and the slimming signal B108 and the undershoot correction signal J118 which are correction signals whose levels are reduced by an attenuator.
An equalized signal 119 is output by adding and subtracting and.

The waveform equalizer circuit shown in FIG. 7 is of a transmissive type, and FIG. 9 shows the signal waveform of each part. The delay time is different from that of the pre-equalization read-out signal B101 which is the main signal, and the slimming signal B2.129, the slimming signal B3.130, and the undershoot correction signal B2.131 and the undershoot, which are correction signals whose levels are reduced by an attenuator. The equalized signal 119 is output by adding / subtracting the correction signal B3 · 132.

[0005]

However, as described above, in the circuit of FIG. 6 of the waveform equalizing circuit of the reproducing circuit of the conventional magnetic storage device as described above, as shown in FIG. When there is a difference, even if one is optimally corrected, the other may not be optimally corrected or may be deteriorated. Therefore, Tr and T
There is a drawback that only a thin film head having a small difference from f can perform optimum correction.

Further, in the waveform equalizing circuit shown in FIG. 7, it is possible to correct even when Tr and Tf are different by appropriately selecting the delay time, but the characteristics of the delay circuit D are the same as those of the delay circuit A. However, since a delay circuit having a delay time of about twice is required, the size of the delay circuit becomes large and the cost becomes high.

[0007]

According to a first aspect of the present invention, in a waveform equalizing circuit used in a reproducing circuit of a magnetic storage device having a thin film head mounted thereon, an output signal of the reproducing circuit is inputted and delayed by a predetermined time. A first delay circuit that outputs a pre-equalization read signal, a slimming signal that is a reflection signal of the pre-equalization read signal, and a plurality of undershoot correction signals having different delay times, and the waveform slimming signal are input. A first attenuator that outputs by changing the level of the signal, the read signal before waveform equalization and the output signal of the first attenuator are input, and the first attenuator reads the read signal before waveform equalization.
A subtractor for subtracting the output signal of the attenuator to output a signal after slimming equalization, and a second delay for inputting the signal after slimming equalization and outputting a plurality of slimming equalized signals delayed by a predetermined time A circuit, a first selector that selects and outputs one of the delayed slimming equalized signals, and a second selector that selects and outputs one of the plurality of undershoot correction signals Selector, a third delay circuit that inputs the undershoot correction signal selected by the second selector and outputs a plurality of undershoot correction signals delayed by a predetermined time, and the plurality of delayed undershoot correction signals A third selector that selects and outputs one of the above, and the undershoot correction signal selected by this third selector is input and the level of the signal is changed and output. A second attenuator, a slimming equalized signal output from the first selector, and an undershoot correction signal with the changed level output from the second attenuator are added, and an equalized signal is output. And a control circuit that inputs a control signal from a higher-order circuit and outputs a switching signal for switching the output signals of the first selector, the second selector, and the third selector.

A second invention is the waveform equalization circuit of the first invention, wherein the third delay circuit and the third selector are deleted, and the second attenuator is the second selector. It is characterized in that the undershoot correction signal to be selected is input.

A third invention is the waveform equalizing circuit according to the first invention, wherein the attenuator, the second delay circuit and the first circuit are provided.
Of the waveform delaying signal before the waveform equalization output by the first delay circuit, the waveform slimming signal in which the level of the signal output by the first attenuator is changed, and the second attenuation An adder / subtractor for adding / subtracting an undershoot correction signal in which the level of the signal output by the converter is changed and outputting a signal after the equal change is provided.

A fourth aspect of the invention is characterized in that the control circuit comprises a read-only memory circuit (ROM).

A fifth aspect of the present invention is a magnetic memory device using the waveform equalizing circuit according to any one of the first to fourth aspects of the present invention, wherein the control circuit previously sets the reproduction output waveform as a characteristic of the thin film head. The position of the undershoot is stored, and when the control signal is input to the control circuit from the upper circuit, the control circuit outputs a predetermined switching signal based on the characteristics of the thin film head so as to switch each sector. It is characterized by doing.

A sixth aspect of the invention is characterized in that the characteristic of the thin film head is a difference between a position Tf in the first half and a position Tr in the second half of the undershoot of the reproduction output waveform.

A seventh invention comprises a thin film head whose Tf side is larger than Tr and a waveform equalizing circuit of the second invention.

An eighth invention comprises a thin film head whose Tr side is larger than Tf and a waveform equalizing circuit of the third invention.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing signal waveforms at respective portions of FIG.

The delay circuit A1 includes a pre-equalization read signal A1.
00 as an input, the pre-equalization read-out signal B101 is output to the subtractor A7, and the waveform slimming signal A102 is output as the attenuator A7.
And outputs to the subtractor A7 via the undershoot correction signals A103, B104, C105, D106, E10.
7 is output to the selector A4. The subtractor A7 inputs the pre-equalization read-out signal B101 and the slimming signal B108, and outputs the pre-equalization read-out signal B101 to the slimming signal B10.
The slimming equalized signal A109 after subtracting 8 is output to the delay circuit C3 and the selector C6.

The delay circuit C3 outputs the slimmed equalized signal A1.
09 to input the slimmed and equalized signals B110 and C1.
11 and 11 are output to the selector C6. The selector C6 selects the input slimmed and equalized signals A109, B110, and C111 by the input selector C switching signal 123 and outputs the slimmed and equalized signal D112 to the adder B8. The selector A4 is an input selector A switching signal 12
1, the undershoot correction signals A103, B10
4, C105, D106, and E107 are selected to output the undershoot correction signal F114 to the delay circuit B2 and the selector B.
5 and output.

The delay circuit B2 receives the undershoot correction signal F114 as an input and the undershoot correction signal G11.
5, H116 are output to the selector B5. Selector B5
Input selector B switching signal 122 causes input undershoot correction signals F114, G115, H11
6, the undershoot correction signal I117 is output via the attenuator B10, and the undershoot correction signal J118 is output to the adder B8.

The adder B8 adds the input slimmed and equalized signal D112 and the undershoot correction signal J118, and outputs the equalized signal 119 to a data detector (not shown). The control circuit (ROM) 13 has a control signal A120.
, The selector A switching signal 121 is output to the selector A4, the selector B switching signal 122 is output to the selector B5, and the selector C switching signal 123 is output to the selector C6.

Next, the operation of the present invention will be described.

Pre-equalization read-out signal A100 shown in FIG.
Is an output from a magnetic head of a magnetic storage device amplified to an appropriate amplitude by using an amplifier. Further, in FIGS. 2 and 3, an isolated waveform is used for explaining the waveform equalizing circuit of the present invention. Further, in a read output using a thin film head as a magnetic head, undershoot occurs on both sides of a solitary wave. Here, the front side of the solitary wave is Tf and the rear side is T
r (FIGS. 1 and 2). The present invention relates to a waveform equalization circuit for correcting this undershoot, and
2 is a waveform equalization circuit when the magnitudes of Tf and Tf are different.

Since the delay circuit A1 is not provided with a terminating resistor, the pre-equalization read signal A100 is totally reflected, and a reflected signal corresponding to a predetermined time of the delay circuit A1 is a slimming signal A102 and an undershoot correction signal A103, B1
04, C105, D106, and E107. The pre-equalization read signal B101 is the pre-equalization read signal A10.
It is a signal obtained by delaying 0 by a predetermined time, and is input to one input terminal of the subtractor A7. Also, the slimming signal B
Reference numeral 108 denotes a slimming signal A102 attenuated by an attenuator A9 to an appropriate size (so that the bit shift is minimized).
And is input to the other input terminal of the subtractor A7.

The subtractor A7 is a pre-equalization read signal B101.
By subtracting the slimming signal B108 from the signal, a slimming equalized signal A109 having a compressed time width is obtained.
This is a conventional cosine equalization method. And the equalized signal A
109 are output to the delay circuit C3 and the selector C6, respectively. Since the delay circuit C3 is terminated by the resistor B12 having the same resistance value as the internal resistance of the delay circuit, the input slimmed and equalized signal A109 is delayed by a predetermined time, and the slimmed and equalized signals B110 and C111 are output as sectors. C6
Output to. Selector C6 is selector C switching signal 1
The input signals after slimming equalization A109, B1 by 23
The slimming-equalized signal D112 in which only one signal is selected from 10 and C111 is output to the adder B8.

On the other hand, the selector A4 receives the undershoot correction signal A of the input according to the selector A switching signal 121.
It is selected from 103, B104, C105, D106, and E107 so that the delay amount is the same as the undershoot time. This time means the pre-equalization read-out signal B101 and the undershoot correction signal A which are the outputs of the delay circuit.
The difference between the delay times of 103, B104, C105, 2, 106, and E107 is just (Tr + Tf) / 2. Also, undershoot correction signals A103, B
104, C105, D106, E107 are delay circuits A1
Since the reflected wave of the output of is also output, the waveform has two peaks at intervals of (Tf + Tr) as shown in FIG.

The undershoot correction signal F114 output from the selector A4 is output to the delay circuit B2 and the selector B5. The delay circuit B2 has the same internal resistance as the delay circuit and is output to the delay circuit B2 and the selector B5. Delay circuit B2
Is terminated by the resistor A11 having the same resistance value as the internal resistance of the delay circuit, the input undershoot correction signal F
Undershoot correction signals G115 and H116 obtained by delaying 114 by a predetermined time are output to the selector B5. The selector B5 uses the selector B switching signal 122 to input the undershoot correction signals F114, G115, H1.
An undershoot correction signal I117 in which only one signal is selected from 16 is output. The undershoot correction signal I117 is attenuated by the attenuator B10 to an appropriate size (correction is optimized) and output to the adder B8 as an undershoot correction signal J118. The adder B8 adds the input slimming equalized signal D112 and the undershoot correction signal J118 to correct the undershoot, and outputs the equalized signal 119.

The operation of the selectors B5 and C6 will be described.

First, as shown in FIG. 2, when Tf of the undershoot positions Tf and Tr is large, the selector B5 selects the undershoot correction signal F114 which has not been delayed from the input and selects the undershoot correction signal F114. The shoot correction signal I117 is output. The selector C6 selects, from the output of the delay circuit C3, a signal delayed by the time after slimming equalization A109 (Tf-Tr) / 2 from the input,
The signal is output as a signal D112 after slimming equalization. By selecting the selector B5 and the selector C6 in this manner, the undershoot position of the slimming equalized signal D112 and the position of the undershoot correction signal J118 coincide with each other, so that the equalized signal 119 of the adder output is Optimal correction.

Next, as shown in FIG. 3, when Tr of the undershoot positions Tf and Tr is large, the selector C6 selects the undelayed slimming equalized signal A109 from the input. After slimming equalization signal D1
12 is output. The selector B5 selects, from the output of the delay circuit B2, a signal obtained by delaying the undershoot correction signal F114 by (Tr-Tf) / 2 from the input, and outputs it as the undershoot correction signal I117. By selecting the selector B5 and the selector C6 in this manner, the undershoot position of the slimming equalized signal D112 and the position of the undershoot correction signal J118 coincide with each other, so that the equalized signal 119 of the adder output is obtained. Is the optimum correction.

Undershoot positions Tf and Tr
Are equal, the selector B5 and the selector C6 do not delay the undershoot correction signal F from being input.
114 and the signal after slimming equalization A109 are selected,
Undershoot correction signal I117 and post-slimming equalization signal D112 are output. This is similar to the conventional method.

The control circuit 13 is for coping with the difference in size between the undershoot positions Tf and Tr due to the positions of the magnetic head and the cylinder, and the difference in the difference between Tr and Tf due to the magnetic head. , Input control signal A12
The selector A switching signal 121, selector B switching signal 122, and selector C switching signal 123, which are output so that the correction is always optimum by 0 (for example, head address and cylinder address), select A4, B5.
Switch C6. Thus, even if the undershoot positions Tf and Tr have different sizes, optimum correction can be performed.

The control circuit 13 may be a read-only memory circuit (ROM).

When Tf is larger than Tf and Tr, the selector B5 selects the undelayed undershoot correction signal F114.
2, the selector B5 and the resistor A11 can be omitted, and the block diagram is as shown in FIG. Similarly, when Tr is large, the delay circuit C3, the selector C6, and the resistor B12 can be omitted, and the block diagram shown in FIG. 5 is obtained. At this time, it is possible to select the heads Tf and Tr used in the magnetic storage device in advance according to the size of the heads and use the respective circuits properly. This is to reduce the signal deterioration by simplifying the circuit configuration. In particular, in the block diagram shown in FIG. 5, since there are few circuits through which the pre-equalization read-out signal which is the main signal passes, the deterioration of the signal by the circuit can be small. Further, since Tf and Tr are determined by the thickness of the magnetic pole of the magnetic circuit when manufacturing the thin film head, Tr is always made to be large in consideration of the variation, and the circuit shown in FIG. 4 is used. Good.

[0034]

As described above, the waveform equalization circuit of the present invention corrects the optimum compensation state even when there is a difference between the undershoot positions Tf and Tr of the output signal of the magnetic head. Therefore, there is an effect that the margin of operation of the reproducing circuit is increased to enable stable operation. Further, there is an effect that the yield of use of the magnetic head can be improved.

Further, since the waveform equalizer circuit of the present invention uses the reflection type, a delay circuit having a delay time which is half that of the conventional waveform equalizer circuit for performing the same correction is sufficient, so that the characteristic is good and the cost is low. Can be configured. In addition, compared with the conventional reflection type waveform equalization circuit, the delay time of the added delay circuit is Tr and T
Half the difference of f, that is, the delay time of | (Tf-Tr) / 2 | is sufficient, and the signal deterioration due to the circuit is small.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a signal waveform of each part in the embodiment of FIG.

FIG. 3 is a diagram showing signal waveforms of respective parts in the embodiment of FIG.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional waveform equalization circuit.

FIG. 7 is a block diagram showing another conventional waveform equalization circuit.

8 is a diagram showing signal waveforms of respective parts in the conventional example of FIG.

9 is a diagram showing signal waveforms of respective parts in the conventional example of FIG.

[Explanation of symbols]

 1 Delay Circuit A 2 Delay Circuit B 3 Delay Circuit C 4 Selector A 5 Selector B 6 Selector C 7 Subtractor A 8 Adder B 9 Attenuator A 10 Attenuator B 11 Resistor A 12 Resistor B 13 Control Circuit (ROM ) 14 adder / subtractor C 15 delay circuit D 16 adder / subtractor D 17 attenuator C 18 attenuator D 19 attenuator E 20 attenuator F 100 pre-equalization read-out signal A 101 pre-equalization read-out signal B 102 slimming signal A 103 undershoot Correction signal A 104 Undershoot correction signal B 105 Undershoot correction signal C 106 Undershoot correction signal D 107 Undershoot correction signal E 108 Slimming signal B 109 After slimming equalization signal A 110 After slimming equalization signal B 111 After slimming equalization Signal C 112 Slimming equalized signal D 11 Undershoot correction signal F 115 Undershoot correction signal G 116 Undershoot correction signal H 117 Undershoot correction signal I 118 Undershoot correction signal J 119 Equalized signal 120 Control signal A 121 Selector A switching signal 122 Selector B switching signal 123 Selector C switching signal 124 slimming signal A2 126 slimming signal A3 127 undershoot correction signal A2 128 undershoot correction signal A3 129 slimming signal B2 130 slimming signal B3 131 undershoot correction signal B2 132 undershoot correction signal B3

Claims (8)

[Claims] 1. A waveform equalizing circuit used in a reproducing circuit of a magnetic storage device having a thin film head, wherein an output signal from the reproducing circuit is input and a read signal before waveform equalization delayed for a predetermined time and the waveform equalizing circuit. A first delay circuit that outputs a slimming signal that is a reflection signal of the pre-reading signal and a plurality of undershoot correction signals having different delay times; and a first delay circuit that inputs the waveform slimming signal and outputs the signal while changing the level of the signal. No. 1 attenuator, the read signal before waveform equalization and the output signal of the first attenuator are input, and the output signal of the first attenuator is subtracted from the read signal before waveform equalization to perform slimming or the like. A subtractor for outputting a signal after equalization, a second delay circuit for inputting the signal after the slimming equalization and outputting a plurality of signals after the slimming equalization, and a plurality of the delayed slimming circuits A second selector for selecting and outputting one of the signals after equalization, and a second selector for selecting and outputting one of the plurality of undershoot correction signals; and A third delay circuit that inputs the undershoot correction signal selected by the selector and outputs a plurality of undershoot correction signals delayed by a predetermined time, and selects one from the delayed plurality of undershoot correction signals. And a second attenuator for inputting the undershoot correction signal selected by the third selector and changing the level of the signal and outputting the slimming output by the first selector. An adder for adding the equalized signal and the undershoot correction signal with the changed level output from the second attenuator and outputting the equalized signal, and control by a higher-level circuit It said first selector inputs the items, the second selector and the third waveform equalization circuit, characterized in that it comprises a control circuit for outputting a switching signal for switching the output signal of the selector. 2. The waveform equalizing circuit according to claim 1, wherein
Deleting the third delay circuit and the third selector,
The waveform equalizer circuit, wherein the second attenuator inputs the undershoot correction signal selected by the second selector. 3. The waveform equalization circuit according to claim 1, wherein
The attenuator, the second delay circuit, and the first selector are deleted, and the pre-waveform equalization read signal output by the first delay circuit and the signal output by the first attenuator are A waveform including an adder / subtractor for adding / subtracting a waveform slimming signal of which level is changed and an undershoot correction signal of which the level of the signal output from the second attenuator is changed to output an after-equal signal Circuit. 4. The waveform equalizing circuit according to claim 1, wherein the control circuit comprises a read only memory circuit (ROM). 5. A magnetic memory device using the waveform equalization circuit according to claim 1, wherein the control circuit previously positions the undershoot of the reproduction output waveform as a characteristic of the thin film head. And when the control signal is input to the control circuit from the upper circuit, the control circuit outputs a predetermined switching signal based on the characteristics of the thin film head to switch each sector. And magnetic storage device. 6. The characteristics of the thin film head are such that the first half position Tf and the second half position T of the undershoot of the reproduction output waveform.
6. The magnetic storage device according to claim 5, wherein the difference is r. 7. A magnetic memory device comprising: a thin film head whose Tf side is larger than said Tr; and a waveform equalizing circuit according to claim 2. 8. A magnetic memory device comprising: a thin film head whose Tr side is larger than said Tf; and a waveform equalizing circuit according to claim 3.